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Implement review feedback. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40863 91177308-0d34-0410-b5e6-96231b3b80d8 Christopher Lamb 12 years ago
2 changed file(s) with 153 addition(s) and 138 deletion(s). Raw diff Collapse all Expand all
8989 FunctionPass *createPrologEpilogCodeInserter();
9090
9191 /// LowerSubregs Pass - This pass lowers subregs to register-register copies
92 /// which yields suboptimial, but correct code if the register allocator
92 /// which yields suboptimal, but correct code if the register allocator
9393 /// cannot coalesce all subreg operations during allocation.
9494 ///
9595 FunctionPass *createLowerSubregsPass();
3131
3232 /// runOnMachineFunction - pass entry point
3333 bool runOnMachineFunction(MachineFunction&);
34
35 bool LowerExtract(MachineInstr *MI);
36 bool LowerInsert(MachineInstr *MI);
3437 };
3538
3639 char LowerSubregsInstructionPass::ID = 0;
4043 return new LowerSubregsInstructionPass();
4144 }
4245
43 // Returns the Register Class of a physical register
46 // Returns the Register Class of a physical register.
4447 static const TargetRegisterClass *getPhysicalRegisterRegClass(
4548 const MRegisterInfo &MRI,
4649 unsigned reg) {
6669 return false;
6770 }
6871
72 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
73 MachineBasicBlock *MBB = MI->getParent();
74 MachineFunction &MF = *MBB->getParent();
75 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
76
77 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
78 MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
79 MI->getOperand(2).isImm() && "Malformed extract_subreg");
80
81 unsigned SuperReg = MI->getOperand(1).getReg();
82 unsigned SubIdx = MI->getOperand(2).getImm();
83
84 assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
85 "Extract supperg source must be a physical register");
86 unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
87 unsigned DstReg = MI->getOperand(0).getReg();
88
89 DOUT << "subreg: CONVERTING: " << *MI;
90
91 if (SrcReg != DstReg) {
92 const TargetRegisterClass *TRC = 0;
93 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
94 TRC = getPhysicalRegisterRegClass(MRI, DstReg);
95 } else {
96 TRC = MF.getSSARegMap()->getRegClass(DstReg);
97 }
98 assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
99 "Extract subreg and Dst must be of same register class");
100
101 MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC);
102 MachineBasicBlock::iterator dMI = MI;
103 DOUT << "subreg: " << *(--dMI);
104 }
105
106 DOUT << "\n";
107 MBB->erase(MI);
108 return true;
109 }
110
111
112 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
113 MachineBasicBlock *MBB = MI->getParent();
114 MachineFunction &MF = *MBB->getParent();
115 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
116 unsigned DstReg = 0;
117 unsigned SrcReg = 0;
118 unsigned InsReg = 0;
119 unsigned SubIdx = 0;
120
121 // If only have 3 operands, then the source superreg is undef
122 // and we can supress the copy from the undef value
123 if (MI->getNumOperands() == 3) {
124 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
125 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
126 MI->getOperand(2).isImm() && "Invalid extract_subreg");
127 DstReg = MI->getOperand(0).getReg();
128 SrcReg = DstReg;
129 InsReg = MI->getOperand(1).getReg();
130 SubIdx = MI->getOperand(2).getImm();
131 } else if (MI->getNumOperands() == 4) {
132 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
133 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
134 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
135 MI->getOperand(3).isImm() && "Invalid extract_subreg");
136 DstReg = MI->getOperand(0).getReg();
137 SrcReg = MI->getOperand(1).getReg();
138 InsReg = MI->getOperand(2).getReg();
139 SubIdx = MI->getOperand(3).getImm();
140 } else
141 assert(0 && "Malformed extract_subreg");
142
143 assert(SubIdx != 0 && "Invalid index for extract_subreg");
144 unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
145
146 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
147 "Insert superreg source must be in a physical register");
148 assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
149 "Insert destination must be in a physical register");
150 assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
151 "Inserted value must be in a physical register");
152
153 DOUT << "subreg: CONVERTING: " << *MI;
154
155 // If the inserted register is already allocated into a subregister
156 // of the destination, we copy the subreg into the source
157 // However, this is only safe if the insert instruction is the kill
158 // of the source register
159 bool revCopyOrder = isSubRegOf(MRI, InsReg, DstReg);
160 if (revCopyOrder) {
161 if (MI->getOperand(1).isKill()) {
162 DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
163 // Insert sub-register copy
164 const TargetRegisterClass *TRC1 = 0;
165 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
166 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
167 } else {
168 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
169 }
170
171 MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
172 MachineBasicBlock::iterator dMI = MI;
173 DOUT << "subreg: " << *(--dMI);
174 } else {
175 assert(0 && "Don't know how to convert this insert");
176 }
177 }
178
179 if (SrcReg != DstReg) {
180 // Insert super-register copy
181 const TargetRegisterClass *TRC0 = 0;
182 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
183 TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
184 } else {
185 TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
186 }
187 assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
188 "Insert superreg and Dst must be of same register class");
189
190 MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0);
191 MachineBasicBlock::iterator dMI = MI;
192 DOUT << "subreg: " << *(--dMI);
193 }
194
195 if (!revCopyOrder && InsReg != DstSubReg) {
196 // Insert sub-register copy
197 const TargetRegisterClass *TRC1 = 0;
198 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
199 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
200 } else {
201 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
202 }
203
204 MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1);
205 MachineBasicBlock::iterator dMI = MI;
206 DOUT << "subreg: " << *(--dMI);
207 }
208
209 DOUT << "\n";
210 MBB->erase(MI);
211 return true;
212 }
69213
70214 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
71215 /// copies.
72216 ///
73217 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
74218 DOUT << "Machine Function\n";
75 const TargetMachine &TM = MF.getTarget();
76 const MRegisterInfo &MRI = *TM.getRegisterInfo();
77219
78220 bool MadeChange = false;
79221
83225 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
84226 mbbi != mbbe; ++mbbi) {
85227 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
86 mi != me; ++mi) {
87
88 if (mi->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
89 assert(mi->getOperand(0).isRegister() && mi->getOperand(0).isDef() &&
90 mi->getOperand(1).isRegister() && mi->getOperand(1).isUse() &&
91 mi->getOperand(2).isImm() && "Malformed extract_subreg");
92
93 unsigned SuperReg = mi->getOperand(1).getReg();
94 unsigned SubIdx = mi->getOperand(2).getImm();
95
96 assert(MRegisterInfo::isPhysicalRegister(SuperReg) &&
97 "Extract supperg source must be a physical register");
98 unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx);
99 unsigned DstReg = mi->getOperand(0).getReg();
100
101 DOUT << "subreg: CONVERTING: " << *mi;
102
103 if (SrcReg != DstReg) {
104 const TargetRegisterClass *TRC = 0;
105 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
106 TRC = getPhysicalRegisterRegClass(MRI, DstReg);
107 } else {
108 TRC = MF.getSSARegMap()->getRegClass(DstReg);
109 }
110 assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
111 "Extract subreg and Dst must be of same register class");
112
113 MRI.copyRegToReg(*mbbi, mi, DstReg, SrcReg, TRC);
114 MachineBasicBlock::iterator dmi = mi;
115 DOUT << "subreg: " << *(--dmi);
116 }
117
118 DOUT << "\n";
119 mbbi->erase(mi);
120 MadeChange = true;
121
122 } else if (mi->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
123
124 unsigned DstReg = 0;
125 unsigned SrcReg = 0;
126 unsigned InsReg = 0;
127 unsigned SubIdx = 0;
128
129 // If only have 3 operands, then the source superreg is undef
130 // and we can supress the copy from the undef value
131 if (mi->getNumOperands() == 3) {
132 assert((mi->getOperand(0).isRegister() && mi->getOperand(0).isDef()) &&
133 (mi->getOperand(1).isRegister() && mi->getOperand(1).isUse()) &&
134 mi->getOperand(2).isImm() && "Invalid extract_subreg");
135 DstReg = mi->getOperand(0).getReg();
136 SrcReg = DstReg;
137 InsReg = mi->getOperand(1).getReg();
138 SubIdx = mi->getOperand(2).getImm();
139 } else if (mi->getNumOperands() == 4) {
140 assert((mi->getOperand(0).isRegister() && mi->getOperand(0).isDef()) &&
141 (mi->getOperand(1).isRegister() && mi->getOperand(1).isUse()) &&
142 (mi->getOperand(2).isRegister() && mi->getOperand(2).isUse()) &&
143 mi->getOperand(3).isImm() && "Invalid extract_subreg");
144 DstReg = mi->getOperand(0).getReg();
145 SrcReg = mi->getOperand(1).getReg();
146 InsReg = mi->getOperand(2).getReg();
147 SubIdx = mi->getOperand(3).getImm();
148 } else
149 assert(0 && "Malformed extract_subreg");
150
151 assert(SubIdx != 0 && "Invalid index for extract_subreg");
152 unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx);
153
154 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
155 "Insert superreg source must be in a physical register");
156 assert(MRegisterInfo::isPhysicalRegister(DstReg) &&
157 "Insert destination must be in a physical register");
158 assert(MRegisterInfo::isPhysicalRegister(InsReg) &&
159 "Inserted value must be in a physical register");
160
161 DOUT << "subreg: CONVERTING: " << *mi;
162
163 // If the inserted register is already allocated into a subregister
164 // of the destination, we copy the subreg into the source
165 // However, this is only safe if the insert instruction is the kill
166 // of the source register
167 bool revCopyOrder = isSubRegOf(MRI, InsReg, DstReg);
168 if (revCopyOrder) {
169 if (mi->getOperand(1).isKill()) {
170 DstSubReg = MRI.getSubReg(SrcReg, SubIdx);
171 // Insert sub-register copy
172 const TargetRegisterClass *TRC1 = 0;
173 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
174 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
175 } else {
176 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
177 }
178
179 MRI.copyRegToReg(*mbbi, mi, DstSubReg, InsReg, TRC1);
180 MachineBasicBlock::iterator dmi = mi;
181 DOUT << "subreg: " << *(--dmi);
182 } else {
183 assert(0 && "Don't know how to convert this insert");
184 }
185 }
186
187 if (SrcReg != DstReg) {
188 // Insert super-register copy
189 const TargetRegisterClass *TRC0 = 0;
190 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
191 TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
192 } else {
193 TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
194 }
195 assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
196 "Insert superreg and Dst must be of same register class");
197
198 MRI.copyRegToReg(*mbbi, mi, DstReg, SrcReg, TRC0);
199 MachineBasicBlock::iterator dmi = mi;
200 DOUT << "subreg: " << *(--dmi);
201 }
202
203 if (!revCopyOrder && InsReg != DstSubReg) {
204 // Insert sub-register copy
205 const TargetRegisterClass *TRC1 = 0;
206 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
207 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
208 } else {
209 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
210 }
211
212 MRI.copyRegToReg(*mbbi, mi, DstSubReg, InsReg, TRC1);
213 MachineBasicBlock::iterator dmi = mi;
214 DOUT << "subreg: " << *(--dmi);
215 }
216
217 DOUT << "\n";
218 mbbi->erase(mi);
219 MadeChange = true;
228 mi != me;) {
229 MachineInstr *MI = mi++;
230
231 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
232 MadeChange |= LowerExtract(MI);
233 } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
234 MadeChange |= LowerInsert(MI);
220235 }
221236 }
222237 }