llvm.org GIT mirror llvm / 981576c
Target independent DAG transform to use truncate for field extraction + sign extend on targets where this is profitable. Passes nightly on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48491 91177308-0d34-0410-b5e6-96231b3b80d8 Christopher Lamb 11 years ago
2 changed file(s) with 65 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
23732373 DAG.getValueType(EVT));
23742374 }
23752375
2376 // fold sra (shl X, m), result_size - n
2377 // -> (sign_extend (trunc (shl X, result_size - n - m))) for
2378 // result_size - n != m. If truncate is free for the target sext(shl) is
2379 // likely to result in better code.
2380 if (N0.getOpcode() == ISD::SHL) {
2381 // Get the two constanst of the shifts, CN0 = m, CN = n.
2382 const ConstantSDNode *N01C = dyn_cast(N0.getOperand(1));
2383 if (N01C && N1C) {
2384 // Determine if the truncate type's bitsize would correspond to
2385 // an integer type for this target.
2386 unsigned VTValSize = MVT::getSizeInBits(VT);
2387 MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue());
2388 unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
2389
2390 // If the shift wouldn't be a noop, the truncated type is an actual type,
2391 // and the truncate is free, then proceed with the transform.
2392 if (ShiftAmt != 0 &&
2393 !MVT::isExtendedVT(TruncVT) && TLI.isTruncateFree(VT, TruncVT)) {
2394 SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
2395 SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt);
2396 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift);
2397 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc);
2398 }
2399 }
2400 }
2401
23762402 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
23772403 if (N1C && N0.getOpcode() == ISD::SRA) {
23782404 if (ConstantSDNode *C1 = dyn_cast(N0.getOperand(1))) {
0 ; RUN: llvm-as < %s | llc -march=x86 | grep sar | count 1
1 ; RUN: llvm-as < %s | llc -march=x86-64 | not grep sar
2
3 define i32 @test(i32 %f12) {
4 %tmp7.25 = lshr i32 %f12, 16
5 %tmp7.26 = trunc i32 %tmp7.25 to i8
6 %tmp78.2 = sext i8 %tmp7.26 to i32
7 ret i32 %tmp78.2
8 }
9
10 define i32 @test2(i32 %f12) {
11 %f11 = shl i32 %f12, 8
12 %tmp7.25 = ashr i32 %f11, 24
13 ret i32 %tmp7.25
14 }
15
16 define i32 @test3(i32 %f12) {
17 %f11 = shl i32 %f12, 13
18 %tmp7.25 = ashr i32 %f11, 24
19 ret i32 %tmp7.25
20 }
21
22 define i64 @test4(i64 %f12) {
23 %f11 = shl i64 %f12, 32
24 %tmp7.25 = ashr i64 %f11, 32
25 ret i64 %tmp7.25
26 }
27
28 define i16 @test5(i16 %f12) {
29 %f11 = shl i16 %f12, 2
30 %tmp7.25 = ashr i16 %f11, 8
31 ret i16 %tmp7.25
32 }
33
34 define i16 @test6(i16 %f12) {
35 %f11 = shl i16 %f12, 8
36 %tmp7.25 = ashr i16 %f11, 8
37 ret i16 %tmp7.25
38 }