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Merging r214865: ------------------------------------------------------------------------ r214865 | thomas.stellard | 2014-08-05 10:40:52 -0400 (Tue, 05 Aug 2014) | 5 lines R600/SI: Avoid generating REGISTER_LOAD instructions. SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code path for 8-bit and 16-bit private loads. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@214895 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 5 years ago
2 changed file(s) with 4 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
11751175 return DAG.getMergeValues(Ops, DL);
11761176 }
11771177
1178 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1178 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1179 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
11791180 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
11801181 return SDValue();
11811182
117117
118118 ; SI-PROMOTE: BUFFER_STORE_SHORT v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s{{[0-9]+}}
119119 ; SI-PROMOTE: BUFFER_STORE_SHORT v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s{{[0-9]+}}
120 ; SI_PROMOTE: BUFFER_LOAD_SSHORT v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}] + v{{[0-9]+}}, s{{[0-9]+}}
120 ; SI-PROMOTE-NOT: MOVREL
121 ; SI-PROMOTE: BUFFER_LOAD_SSHORT v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}] + v{{[0-9]+}} + s{{[0-9]+}}
121122 define void @short_array(i32 addrspace(1)* %out, i32 %index) {
122123 entry:
123124 %0 = alloca [2 x i16]