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ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63509 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
1 changed file(s) with 8 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
75147514 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
75157515 switch (Opc) {
75167516 default: break;
7517 case X86ISD::ADD:
7518 case X86ISD::SUB:
7519 case X86ISD::SMUL:
7520 case X86ISD::UMUL:
7521 // These nodes' second result is a boolean.
7522 if (Op.getResNo() == 0)
7523 break;
7524 // Fallthrough
75177525 case X86ISD::SETCC:
75187526 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
75197527 Mask.getBitWidth() - 1);