llvm.org GIT mirror llvm / 97b0729
Merging r167855 into 3.2 relase branch Do not consider a machine instruction that uses and defines the same physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168334 91177308-0d34-0410-b5e6-96231b3b80d8 Pawel Wodnicki 6 years ago
2 changed file(s) with 62 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
8383 bool hasLivePhysRegDefUses(const MachineInstr *MI,
8484 const MachineBasicBlock *MBB,
8585 SmallSet &PhysRefs,
86 SmallVector &PhysDefs) const;
86 SmallVector &PhysDefs,
87 bool &PhysUseDef) const;
8788 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
8889 SmallSet &PhysRefs,
8990 SmallVector &PhysDefs,
193194 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
194195 const MachineBasicBlock *MBB,
195196 SmallSet &PhysRefs,
196 SmallVector &PhysDefs) const{
197 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
197 SmallVector &PhysDefs,
198 bool &PhysUseDef) const{
199 // First, add all uses to PhysRefs.
198200 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
199201 const MachineOperand &MO = MI->getOperand(i);
200 if (!MO.isReg())
202 if (!MO.isReg() || MO.isDef())
201203 continue;
202204 unsigned Reg = MO.getReg();
203205 if (!Reg)
204206 continue;
205207 if (TargetRegisterInfo::isVirtualRegister(Reg))
206 continue;
207 // If the def is dead, it's ok. But the def may not marked "dead". That's
208 // common since this pass is run before livevariables. We can scan
209 // forward a few instructions and check if it is obviously dead.
210 if (MO.isDef() &&
211 (MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end())))
212208 continue;
213209 // Reading constant physregs is ok.
214210 if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
215211 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
216212 PhysRefs.insert(*AI);
217 if (MO.isDef())
213 }
214
215 // Next, collect all defs into PhysDefs. If any is already in PhysRefs
216 // (which currently contains only uses), set the PhysUseDef flag.
217 PhysUseDef = false;
218 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
219 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
220 const MachineOperand &MO = MI->getOperand(i);
221 if (!MO.isReg() || !MO.isDef())
222 continue;
223 unsigned Reg = MO.getReg();
224 if (!Reg)
225 continue;
226 if (TargetRegisterInfo::isVirtualRegister(Reg))
227 continue;
228 // Check against PhysRefs even if the def is "dead".
229 if (PhysRefs.count(Reg))
230 PhysUseDef = true;
231 // If the def is dead, it's ok. But the def may not marked "dead". That's
232 // common since this pass is run before livevariables. We can scan
233 // forward a few instructions and check if it is obviously dead.
234 if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
218235 PhysDefs.push_back(Reg);
219236 }
237
238 // Finally, add all defs to PhysRefs as well.
239 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
240 for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
241 PhysRefs.insert(*AI);
220242
221243 return !PhysRefs.empty();
222244 }
458480 bool CrossMBBPhysDef = false;
459481 SmallSet PhysRefs;
460482 SmallVector PhysDefs;
461 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs, PhysDefs)) {
483 bool PhysUseDef = false;
484 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs,
485 PhysDefs, PhysUseDef)) {
462486 FoundCSE = false;
463487
464488 // ... Unless the CS is local or is in the sole predecessor block
465489 // and it also defines the physical register which is not clobbered
466490 // in between and the physical register uses were not clobbered.
467 unsigned CSVN = VNT.lookup(MI);
468 MachineInstr *CSMI = Exps[CSVN];
469 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
470 FoundCSE = true;
491 // This can never be the case if the instruction both uses and
492 // defines the same physical register, which was detected above.
493 if (!PhysUseDef) {
494 unsigned CSVN = VNT.lookup(MI);
495 MachineInstr *CSMI = Exps[CSVN];
496 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
497 FoundCSE = true;
498 }
471499 }
472500
473501 if (!FoundCSE) {
0 ; RUN: llc < %s | FileCheck %s
1 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 define void @test(i64 %n) nounwind {
5 entry:
6 %0 = alloca i8, i64 %n, align 1
7 %1 = alloca i8, i64 %n, align 1
8 call void @use(i8* %0, i8* %1) nounwind
9 ret void
10 }
11
12 declare void @use(i8*, i8*)
13
14 ; Check we actually have two instances of dynamic stack allocation,
15 ; identified by the stdux used to update the back-chain link.
16 ; CHECK: stdux
17 ; CHECK: stdux