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[AArch64 NEON] Add patterns for concat_vector on v2i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200111 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Qin 6 years ago
2 changed file(s) with 56 addition(s) and 21 deletion(s). Raw diff Collapse all Expand all
70737073 defm : Concat_Vector_Pattern;
70747074 defm : Concat_Vector_Pattern;
70757075
7076 def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), undef)),
7077 (v2i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32))>;
7078 def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
7079 (EXTRACT_SUBREG
7080 (v4i32 (INSELs
7081 (v4i32 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)),
7082 (v4i32 (SUBREG_TO_REG (i64 0), FPR32:$Rm, sub_32)),
7083 (i64 1),
7084 (i64 0))),
7085 sub_64)>;
70767086 def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rn))),
7077 (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
7078 def : Pat<(v2i32 (concat_vectors undef, (v1i32 FPR32:$Rn))),
70797087 (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
70807088
70817089 //patterns for EXTRACT_SUBVECTOR
947947 ret <2 x i32> %vecinit1.i
948948 }
949949
950 define <2 x i32> @test_concat_undef_v1i32(<1 x i32> %a) {
951 ; CHECK-LABEL: test_concat_undef_v1i32:
952 ; CHECK: dup v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]
953 entry:
954 %0 = extractelement <1 x i32> %a, i32 0
955 %vecinit1.i = insertelement <2 x i32> undef, i32 %0, i32 1
956 ret <2 x i32> %vecinit1.i
957 }
958
959 define <2 x i32> @test_concat_v1i32_v1i32(<1 x i32> %a) {
960 ; CHECK-LABEL: test_concat_v1i32_v1i32:
961 ; CHECK: dup v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]
962 entry:
963 %0 = extractelement <1 x i32> %a, i32 0
964 %vecinit.i = insertelement <2 x i32> undef, i32 %0, i32 0
965 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %0, i32 1
966 ret <2 x i32> %vecinit1.i
967 }
968
969950
970951 define <2 x float> @test_scalar_to_vector_f32_to_v2f32(<2 x float> %a) {
971952 ; CHECK-LABEL: test_scalar_to_vector_f32_to_v2f32:
999980 entry:
1000981 %vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32>
1001982 ret <16 x i8> %vecinit30
983 }
984
985 define <2 x i32> @test_concat_undef_v1i32(<1 x i32> %a) {
986 ; CHECK-LABEL: test_concat_undef_v1i32:
987 ; CHECK: ins v{{[0-9]+}}.s[1], v{{[0-9]+}}.s[0]
988 entry:
989 %0 = extractelement <1 x i32> %a, i32 0
990 %vecinit1.i = insertelement <2 x i32> undef, i32 %0, i32 1
991 ret <2 x i32> %vecinit1.i
992 }
993
994 declare <1 x i32> @llvm.arm.neon.vqabs.v1i32(<1 x i32>) #4
995
996 define <2 x i32> @test_concat_v1i32_undef(<1 x i32> %a) {
997 ; CHECK-LABEL: test_concat_v1i32_undef:
998 ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
999 ; CHECK-NEXT: ret
1000 entry:
1001 %b = tail call <1 x i32> @llvm.arm.neon.vqabs.v1i32(<1 x i32> %a)
1002 %0 = extractelement <1 x i32> %b, i32 0
1003 %vecinit.i432 = insertelement <2 x i32> undef, i32 %0, i32 0
1004 ret <2 x i32> %vecinit.i432
1005 }
1006
1007 define <2 x i32> @test_concat_same_v1i32_v1i32(<1 x i32> %a) {
1008 ; CHECK-LABEL: test_concat_same_v1i32_v1i32:
1009 ; CHECK: dup v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]
1010 entry:
1011 %0 = extractelement <1 x i32> %a, i32 0
1012 %vecinit.i = insertelement <2 x i32> undef, i32 %0, i32 0
1013 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %0, i32 1
1014 ret <2 x i32> %vecinit1.i
1015 }
1016
1017 define <2 x i32> @test_concat_diff_v1i32_v1i32(<1 x i32> %a, <1 x i32> %b) {
1018 ; CHECK-LABEL: test_concat_diff_v1i32_v1i32:
1019 ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}
1020 ; CHECK-NEXT: sqabs s{{[0-9]+}}, s{{[0-9]+}}
1021 ; CHECK-NEXT: ins v0.s[1], v1.s[0]
1022 entry:
1023 %c = tail call <1 x i32> @llvm.arm.neon.vqabs.v1i32(<1 x i32> %a)
1024 %d = extractelement <1 x i32> %c, i32 0
1025 %e = tail call <1 x i32> @llvm.arm.neon.vqabs.v1i32(<1 x i32> %b)
1026 %f = extractelement <1 x i32> %e, i32 0
1027 %h = shufflevector <1 x i32> %c, <1 x i32> %e, <2 x i32>
1028 ret <2 x i32> %h
10021029 }
10031030
10041031 define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {