llvm.org GIT mirror llvm / 96f678f
Added the MachineSchedulerPass skeleton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148105 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 8 years ago
9 changed file(s) with 259 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
8383 /// RegisteCoalescer pass - This pass merges live ranges to eliminate copies.
8484 extern char &RegisterCoalescerPassID;
8585
86 /// MachineScheduler pass - This pass schedules machine instructions.
87 extern char &MachineSchedulerPassID;
88
8689 /// SpillPlacement analysis. Suggest optimal placement of spill code between
8790 /// basic blocks.
8891 ///
155155 void initializeMachineLoopInfoPass(PassRegistry&);
156156 void initializeMachineLoopRangesPass(PassRegistry&);
157157 void initializeMachineModuleInfoPass(PassRegistry&);
158 void initializeMachineSchedulerPassPass(PassRegistry&);
158159 void initializeMachineSinkingPass(PassRegistry&);
159160 void initializeMachineVerifierPassPass(PassRegistry&);
160161 void initializeMemCpyOptPass(PassRegistry&);
3232 /// StrongPHIElim - This flag enables more aggressive PHI elimination
3333 /// wth earlier copy coalescing.
3434 extern bool StrongPHIElim;
35
36 /// EnableMachineSched - temporary flag to enable the machine scheduling pass
37 /// until we complete the register allocation pass configuration cleanup.
38 extern bool EnableMachineSched;
3539
3640 class TargetOptions {
3741 public:
5656 MachinePassRegistry.cpp
5757 MachineRegisterInfo.cpp
5858 MachineSSAUpdater.cpp
59 MachineScheduler.cpp
5960 MachineSink.cpp
6061 MachineVerifier.cpp
6162 OcamlGC.cpp
4242 initializeProcessImplicitDefsPass(Registry);
4343 initializePEIPass(Registry);
4444 initializeRegisterCoalescerPass(Registry);
45 initializeMachineSchedulerPassPass(Registry);
4546 initializeRenderMachineFunctionPass(Registry);
4647 initializeSlotIndexesPass(Registry);
4748 initializeStackProtectorPass(Registry);
0 //===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // MachineScheduler schedules machine instructions after phi elimination. It
10 // preserves LiveIntervals so it can be invoked before register allocation.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "misched"
15
16 #include "ScheduleDAGInstrs.h"
17 #include "LiveDebugVariables.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachinePassRegistry.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/ADT/OwningPtr.h"
27
28 using namespace llvm;
29
30 namespace {
31 /// MachineSchedulerPass runs after coalescing and before register allocation.
32 class MachineSchedulerPass : public MachineFunctionPass {
33 public:
34 MachineFunction *MF;
35 const MachineLoopInfo *MLI;
36 const MachineDominatorTree *MDT;
37
38 MachineSchedulerPass();
39
40 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
41
42 virtual void releaseMemory() {}
43
44 virtual bool runOnMachineFunction(MachineFunction&);
45
46 virtual void print(raw_ostream &O, const Module* = 0) const;
47
48 static char ID; // Class identification, replacement for typeinfo
49 };
50 } // namespace
51
52 char MachineSchedulerPass::ID = 0;
53
54 char &llvm::MachineSchedulerPassID = MachineSchedulerPass::ID;
55
56 INITIALIZE_PASS_BEGIN(MachineSchedulerPass, "misched",
57 "Machine Instruction Scheduler", false, false)
58 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
59 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
60 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
61 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
62 INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
63 INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
64 INITIALIZE_PASS_END(MachineSchedulerPass, "misched",
65 "Machine Instruction Scheduler", false, false)
66
67 MachineSchedulerPass::MachineSchedulerPass()
68 : MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
69 initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
70 }
71
72 void MachineSchedulerPass::getAnalysisUsage(AnalysisUsage &AU) const {
73 AU.setPreservesCFG();
74 AU.addRequiredID(MachineDominatorsID);
75 AU.addRequired();
76 AU.addRequired();
77 AU.addPreserved();
78 AU.addRequired();
79 AU.addPreserved();
80 AU.addRequired();
81 AU.addPreserved();
82 AU.addRequired();
83 AU.addPreserved();
84 if (StrongPHIElim) {
85 AU.addRequiredID(StrongPHIEliminationID);
86 AU.addPreservedID(StrongPHIEliminationID);
87 }
88 AU.addRequiredID(RegisterCoalescerPassID);
89 AU.addPreservedID(RegisterCoalescerPassID);
90 MachineFunctionPass::getAnalysisUsage(AU);
91 }
92
93 namespace {
94 /// Currently force DAG building but don't reschedule anything. This is a
95 /// temporarily useful framework that provides a place to hook in experimental
96 /// code that requires a dependence graph prior to register allocation.
97 class MachineScheduler : public ScheduleDAGInstrs {
98 public:
99 MachineScheduler(MachineSchedulerPass *P)
100 : ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT)
101 {}
102
103 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
104 /// time to do some work.
105 virtual void Schedule();
106 };
107 } // namespace
108
109 namespace {
110 /// MachineSchedRegistry provides a selection of available machine instruction
111 /// schedulers.
112 class MachineSchedRegistry : public MachinePassRegistryNode {
113 public:
114 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedulerPass *);
115
116 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
117 typedef ScheduleDAGCtor FunctionPassCtor;
118
119 static MachinePassRegistry Registry;
120
121 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
122 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
123 Registry.Add(this);
124 }
125 ~MachineSchedRegistry() { Registry.Remove(this); }
126
127 // Accessors.
128 //
129 MachineSchedRegistry *getNext() const {
130 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
131 }
132 static MachineSchedRegistry *getList() {
133 return (MachineSchedRegistry *)Registry.getList();
134 }
135 static ScheduleDAGCtor getDefault() {
136 return (ScheduleDAGCtor)Registry.getDefault();
137 }
138 static void setDefault(ScheduleDAGCtor C) {
139 Registry.setDefault((MachinePassCtor)C);
140 }
141 static void setListener(MachinePassRegistryListener *L) {
142 Registry.setListener(L);
143 }
144 };
145 } // namespace
146
147 MachinePassRegistry MachineSchedRegistry::Registry;
148
149 static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P);
150
151 /// MachineSchedOpt allows command line selection of the scheduler.
152 static cl::opt
153 RegisterPassParser >
154 MachineSchedOpt("misched",
155 cl::init(&createDefaultMachineSched), cl::Hidden,
156 cl::desc("Machine instruction scheduler to use"));
157
158 static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P) {
159 return new MachineScheduler(P);
160 }
161 static MachineSchedRegistry
162 SchedDefaultRegistry("default", "Activate the scheduler pass, "
163 "but don't reorder instructions",
164 createDefaultMachineSched);
165
166 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
167 /// time to do some work.
168 void MachineScheduler::Schedule() {
169 DEBUG(dbgs() << "********** MI Scheduling **********\n");
170 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
171 SUnits[su].dumpAll(this));
172 // TODO: Put interesting things here.
173 }
174
175 bool MachineSchedulerPass::runOnMachineFunction(MachineFunction &mf) {
176 // Initialize the context of the pass.
177 MF = &mf;
178 MLI = &getAnalysis();
179 MDT = &getAnalysis();
180
181 // Select the scheduler, or set the default.
182 MachineSchedRegistry::ScheduleDAGCtor Ctor =
183 MachineSchedRegistry::getDefault();
184 if (!Ctor) {
185 Ctor = MachineSchedOpt;
186 MachineSchedRegistry::setDefault(Ctor);
187 }
188 // Instantiate the selected scheduler.
189 OwningPtr Scheduler(Ctor(this));
190
191 // Visit all machine basic blocks.
192 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end();
193 MBB != MBBEnd; ++MBB) {
194
195 DEBUG(dbgs() << "MachineScheduling " << MF->getFunction()->getName()
196 << ":BB#" << MBB->getNumber() << "\n");
197
198 // Inform ScheduleDAGInstrs of the region being scheduler. It calls back
199 // to our Schedule() method.
200 Scheduler->Run(MBB, MBB->begin(), MBB->end(), MBB->size());
201 }
202 return true;
203 }
204
205 void MachineSchedulerPass::print(raw_ostream &O, const Module* m) const {
206 // unimplemented
207 }
208
209 #ifndef NDEBUG
210 namespace {
211 /// Reorder instructions as much as possible.
212 class InstructionShuffler : public ScheduleDAGInstrs {
213 public:
214 InstructionShuffler(MachineSchedulerPass *P)
215 : ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT)
216 {}
217
218 /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
219 /// time to do some work.
220 virtual void Schedule() {
221 llvm_unreachable("unimplemented");
222 }
223 };
224 } // namespace
225
226 static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedulerPass *P) {
227 return new InstructionShuffler(P);
228 }
229 static MachineSchedRegistry ShufflerRegistry("shuffle",
230 "Shuffle machine instructions",
231 createInstructionShuffler);
232 #endif // !NDEBUG
128128 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
129129 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
130130 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
131 initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
131132 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
132133 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
133134 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
147148 if (StrongPHIElim)
148149 AU.addRequiredID(StrongPHIEliminationID);
149150 AU.addRequiredTransitiveID(RegisterCoalescerPassID);
151 if (EnableMachineSched)
152 AU.addRequiredID(MachineSchedulerPassID);
150153 AU.addRequired();
151154 AU.addRequired();
152155 AU.addPreserved();
308308 initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
309309 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
310310 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
311 initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
311312 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
312313 initializeLiveStacksPass(*PassRegistry::getPassRegistry());
313314 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
329330 if (StrongPHIElim)
330331 AU.addRequiredID(StrongPHIEliminationID);
331332 AU.addRequiredTransitiveID(RegisterCoalescerPassID);
333 if (EnableMachineSched)
334 AU.addRequiredID(MachineSchedulerPassID);
332335 AU.addRequired();
333336 AU.addRequired();
334337 AU.addPreserved();
2222
2323 namespace llvm {
2424 bool StrongPHIElim;
25 bool EnableMachineSched;
2526 bool HasDivModLibcall;
2627 bool AsmVerbosityDefault(false);
2728 }
3435 FunctionSections("ffunction-sections",
3536 cl::desc("Emit functions into separate sections"),
3637 cl::init(false));
37
38
39 /// EnableMachineSched - temporary flag to enable the machine scheduling pass
40 /// until we complete the register allocation pass configuration cleanup.
41 static cl::opt
42 MachineSchedOpt("enable-misched",
43 cl::desc("Enable the machine instruction scheduling pass."),
44 cl::location(EnableMachineSched),
45 cl::init(false), cl::Hidden);
46
3847 //---------------------------------------------------------------------------
3948 // TargetMachine Class
4049 //