llvm.org GIT mirror llvm / 96ed12f
[CodeGen] Print RegClasses on MI in verbose mode r322086 removed the trailing information describing reg classes for each register. This patch adds printing reg classes next to every register when individual operands/instructions/basic blocks are printed. In the case of dumping MIR or printing a full function, by default don't print it. Differential Revision: https://reviews.llvm.org/D42239 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322867 91177308-0d34-0410-b5e6-96231b3b80d8 Francis Visoiu Mistrih 2 years ago
19 changed file(s) with 107 addition(s) and 96 deletion(s). Raw diff Collapse all Expand all
724724
725725 // Debugging methods.
726726 void dump() const;
727 void print(raw_ostream &OS, const SlotIndexes* = nullptr) const;
727 void print(raw_ostream &OS, const SlotIndexes * = nullptr,
728 bool IsVerbose = true) const;
728729 void print(raw_ostream &OS, ModuleSlotTracker &MST,
729 const SlotIndexes* = nullptr) const;
730 const SlotIndexes * = nullptr, bool IsVerbose = true) const;
730731
731732 // Printing method used by LoopInfo.
732733 void printAsOperand(raw_ostream &OS, bool PrintType = true) const;
12321232 bool hasComplexRegisterTies() const;
12331233
12341234 /// Print this MI to \p OS.
1235 /// Don't print information that can be inferred from other instructions if
1236 /// \p IsVerbose is false. It is usually true when only a fragment of the
1237 /// function is printed.
12351238 /// Only print the defs and the opcode if \p SkipOpers is true.
12361239 /// Otherwise, also print operands if \p SkipDebugLoc is true.
12371240 /// Otherwise, also print the debug loc, with a terminating newline.
12381241 /// \p TII is used to print the opcode name. If it's not present, but the
12391242 /// MI is in a function, the opcode will be printed using the function's TII.
1240 void print(raw_ostream &OS, bool SkipOpers = false, bool SkipDebugLoc = false,
1243 void print(raw_ostream &OS, bool IsVerbose = true, bool SkipOpers = false,
1244 bool SkipDebugLoc = false,
12411245 const TargetInstrInfo *TII = nullptr) const;
1242 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool SkipOpers = false,
1243 bool SkipDebugLoc = false,
1246 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsVerbose = true,
1247 bool SkipOpers = false, bool SkipDebugLoc = false,
12441248 const TargetInstrInfo *TII = nullptr) const;
12451249 void dump() const;
12461250 /// @}
269269 /// \param PrintDef - whether we want to print `def` on an operand which
270270 /// isDef. Sometimes, if the operand is printed before '=', we don't print
271271 /// `def`.
272 /// \param IsVerbose - whether we want a verbose output of the MO. This
273 /// prints extra information that can be easily inferred when printing the
274 /// whole function, but not when printing only a fragment of it.
272275 /// \param ShouldPrintRegisterTies - whether we want to print register ties.
273276 /// Sometimes they are easily determined by the instruction's descriptor
274277 /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
279282 /// information from it's parent.
280283 /// \param IntrinsicInfo - same as \p TRI.
281284 void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
282 bool PrintDef, bool ShouldPrintRegisterTies,
285 bool PrintDef, bool IsVerbose, bool ShouldPrintRegisterTies,
283286 unsigned TiedOperandIdx, const TargetRegisterInfo *TRI,
284287 const TargetIntrinsicInfo *IntrinsicInfo) const;
285288
767767 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
768768 TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
769769 const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
770 Op.print(OS, MST, TypeToPrint, PrintDef, ShouldPrintRegisterTies,
771 TiedOperandIdx, TRI, TII);
770 Op.print(OS, MST, TypeToPrint, PrintDef, /*IsVerbose=*/false,
771 ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
772772 break;
773773 }
774774 case MachineOperand::MO_FrameIndex:
258258 return Name;
259259 }
260260
261 void MachineBasicBlock::print(raw_ostream &OS, const SlotIndexes *Indexes)
262 const {
261 void MachineBasicBlock::print(raw_ostream &OS, const SlotIndexes *Indexes,
262 bool IsVerbose) const {
263263 const MachineFunction *MF = getParent();
264264 if (!MF) {
265265 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
269269 const Function &F = MF->getFunction();
270270 const Module *M = F.getParent();
271271 ModuleSlotTracker MST(M);
272 print(OS, MST, Indexes);
272 print(OS, MST, Indexes, IsVerbose);
273273 }
274274
275275 void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
276 const SlotIndexes *Indexes) const {
276 const SlotIndexes *Indexes,
277 bool IsVerbose) const {
277278 const MachineFunction *MF = getParent();
278279 if (!MF) {
279280 OS << "Can't print out MachineBasicBlock because parent MachineFunction"
329330 OS << '\t';
330331 if (I.isInsideBundle())
331332 OS << " * ";
332 I.print(OS, MST);
333 I.print(OS, MST, IsVerbose);
333334 }
334335
335336 // Print the successors of this block according to the CFG.
521521 MST.incorporateFunction(getFunction());
522522 for (const auto &BB : *this) {
523523 OS << '\n';
524 BB.print(OS, MST, Indexes);
524 // If we print the whole function, don't print any verbose information,
525 // since that information is already present.
526 BB.print(OS, MST, Indexes, /*IsVerbose=*/false);
525527 }
526528
527529 OS << "\n# End machine code for function " << getName() << ".\n\n";
12281228 }
12291229 #endif
12301230
1231 void MachineInstr::print(raw_ostream &OS, bool SkipOpers, bool SkipDebugLoc,
1232 const TargetInstrInfo *TII) const {
1231 void MachineInstr::print(raw_ostream &OS, bool IsVerbose, bool SkipOpers,
1232 bool SkipDebugLoc, const TargetInstrInfo *TII) const {
12331233 const Module *M = nullptr;
12341234 const Function *F = nullptr;
12351235 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
12401240 ModuleSlotTracker MST(M);
12411241 if (F)
12421242 MST.incorporateFunction(*F);
1243 print(OS, MST, SkipOpers, SkipDebugLoc, TII);
1243 print(OS, MST, IsVerbose, SkipOpers, SkipDebugLoc, TII);
12441244 }
12451245
12461246 void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1247 bool SkipOpers, bool SkipDebugLoc,
1247 bool IsVerbose, bool SkipOpers, bool SkipDebugLoc,
12481248 const TargetInstrInfo *TII) const {
12491249 // We can be a bit tidier if we know the MachineFunction.
12501250 const MachineFunction *MF = nullptr;
12801280
12811281 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
12821282 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1283 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, ShouldPrintRegisterTies,
1284 TiedOperandIdx, TRI, IntrinsicInfo);
1283 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsVerbose,
1284 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
12851285 ++StartOp;
12861286 }
12871287
13131313 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
13141314 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
13151315 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1316 getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true,
1316 getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsVerbose,
13171317 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
13181318 IntrinsicInfo);
13191319
13521352 else {
13531353 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
13541354 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1355 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true,
1355 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsVerbose,
13561356 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
13571357 }
13581358 } else if (i == AsmDescOp && MO.isImm()) {
14191419 if (MO.isImm() && isOperandSubregIdx(i))
14201420 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
14211421 else
1422 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true,
1422 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsVerbose,
14231423 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
14241424 }
14251425 }
640640 const TargetIntrinsicInfo *IntrinsicInfo) const {
641641 tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
642642 ModuleSlotTracker DummyMST(nullptr);
643 print(OS, DummyMST, LLT{}, /*PrintDef=*/false,
643 print(OS, DummyMST, LLT{}, /*PrintDef=*/false, /*IsVerbose=*/true,
644644 /*ShouldPrintRegisterTies=*/true,
645645 /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
646646 }
647647
648648 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
649 LLT TypeToPrint, bool PrintDef,
649 LLT TypeToPrint, bool PrintDef, bool IsVerbose,
650650 bool ShouldPrintRegisterTies,
651651 unsigned TiedOperandIdx,
652652 const TargetRegisterInfo *TRI,
686686 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
687687 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
688688 const MachineRegisterInfo &MRI = MF->getRegInfo();
689 if (!PrintDef || MRI.def_empty(Reg)) {
689 if (IsVerbose || !PrintDef || MRI.def_empty(Reg)) {
690690 OS << ':';
691691 OS << printRegClassOrBank(Reg, MRI, TRI);
692692 }
2626 Key = MKey;
2727
2828 raw_string_ostream OS(Val);
29 MI.print(OS, /*SkipOpers=*/false, /*SkipDebugLoc=*/true);
29 MI.print(OS, /*IsVerbose=*/true, /*SkipOpers=*/false, /*SkipDebugLoc=*/true);
3030 }
3131
3232 Optional
4545 ; The key problem here is that we may fail to create an MBB referenced by a
4646 ; PHI. If so, we cannot complete the G_PHI and mustn't try or bad things
4747 ; happen.
48 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: G_STORE %6(s32), %2(p0); mem:ST4[%addr] (in function: pending_phis)
48 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: G_STORE %6:gpr(s32), %2:gpr(p0); mem:ST4[%addr] (in function: pending_phis)
4949 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for pending_phis
5050 ; FALLBACK-WITH-REPORT-OUT-LABEL: pending_phis:
5151 define i32 @pending_phis(i1 %tst, i32 %val, i32* %addr) {
6565 }
6666
6767 ; General legalizer inability to handle types whose size wasn't a power of 2.
68 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1(s42), %0(p0); mem:ST6[%addr](align=8) (in function: odd_type)
68 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1:_(s42), %0:_(p0); mem:ST6[%addr](align=8) (in function: odd_type)
6969 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type
7070 ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type:
7171 define void @odd_type(i42* %addr) {
7474 ret void
7575 }
7676
77 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1(<7 x s32>), %0(p0); mem:ST28[%addr](align=32) (in function: odd_vector)
77 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1:_(<7 x s32>), %0:_(p0); mem:ST28[%addr](align=32) (in function: odd_vector)
7878 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector
7979 ; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector:
8080 define void @odd_vector(<7 x i32>* %addr) {
9393 }
9494
9595 ; Just to make sure we don't accidentally emit a normal load/store.
96 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: %2:gpr(s64) = G_LOAD %0(p0); mem:LD8[%addr] (in function: atomic_ops)
96 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: %2:gpr(s64) = G_LOAD %0:gpr(p0); mem:LD8[%addr] (in function: atomic_ops)
9797 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for atomic_ops
9898 ; FALLBACK-WITH-REPORT-LABEL: atomic_ops:
9999 define i64 @atomic_ops(i64* %addr) {
141141 ret fp128 0xL00000000000000004000000000000000
142142 }
143143
144 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %0:_(p0) = G_EXTRACT_VECTOR_ELT %1(<2 x p0>), %2(s32) (in function: vector_of_pointers_extractelement)
144 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %0:_(p0) = G_EXTRACT_VECTOR_ELT %1:_(<2 x p0>), %2:_(s32) (in function: vector_of_pointers_extractelement)
145145 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_extractelement
146146 ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_extractelement:
147147 @var = global <2 x i16*> zeroinitializer
158158 br label %block
159159 }
160160
161 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0(<2 x p0>), %4(p0); mem:ST16[undef] (in function: vector_of_pointers_insertelement)
161 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0:_(<2 x p0>), %4:_(p0); mem:ST16[undef] (in function: vector_of_pointers_insertelement)
162162 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement
163163 ; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement:
164164 define void @vector_of_pointers_insertelement() {
174174 br label %block
175175 }
176176
177 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1(s96), %3(p0); mem:ST12[undef](align=4) (in function: nonpow2_insertvalue_narrowing)
177 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1:_(s96), %3:_(p0); mem:ST12[undef](align=4) (in function: nonpow2_insertvalue_narrowing)
178178 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_insertvalue_narrowing
179179 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_insertvalue_narrowing:
180180 %struct96 = type { float, float, float }
215215 ret void
216216 }
217217
218 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %3(s96), %0(p0); mem:ST12[%c](align=16) (in function: nonpow2_store_narrowing
218 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %3:_(s96), %0:_(p0); mem:ST12[%c](align=16) (in function: nonpow2_store_narrowing
219219 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_store_narrowing
220220 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_store_narrowing:
221221 define void @nonpow2_store_narrowing(i96* %c) {
225225 ret void
226226 }
227227
228 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0(s96), %1(p0); mem:ST12[undef](align=16) (in function: nonpow2_constant_narrowing)
228 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %0:_(s96), %1:_(p0); mem:ST12[undef](align=16) (in function: nonpow2_constant_narrowing)
229229 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_constant_narrowing
230230 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_constant_narrowing:
231231 define void @nonpow2_constant_narrowing() {
235235
236236 ; Currently can't handle vector lengths that aren't an exact multiple of
237237 ; natively supported vector lengths. Test that the fall-back works for those.
238 ; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: :0:0: unable to legalize instruction: %1(<7 x s64>) = G_ADD %0, %0; (in function: nonpow2_vector_add_fewerelements
239 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %2:_(s64) = G_EXTRACT_VECTOR_ELT %1(<7 x s64>), %3(s64) (in function: nonpow2_vector_add_fewerelements)
238 ; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: :0:0: unable to legalize instruction: %1:_(<7 x s64>) = G_ADD %0, %0; (in function: nonpow2_vector_add_fewerelements
239 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %2:_(s64) = G_EXTRACT_VECTOR_ELT %1:_(<7 x s64>), %3:_(s64) (in function: nonpow2_vector_add_fewerelements)
240240 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_vector_add_fewerelements
241241 ; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_vector_add_fewerelements:
242242 define void @nonpow2_vector_add_fewerelements() {
44 ; CHECK-LABEL: stp_i64_scale:%bb.0
55 ; CHECK:Cluster ld/st SU(4) - SU(3)
66 ; CHECK:Cluster ld/st SU(2) - SU(5)
7 ; CHECK:SU(4): STRXui %1, %0, 1
8 ; CHECK:SU(3): STRXui %1, %0, 2
9 ; CHECK:SU(2): STRXui %1, %0, 3
10 ; CHECK:SU(5): STRXui %1, %0, 4
7 ; CHECK:SU(4): STRXui %1:gpr64, %0:gpr64common, 1
8 ; CHECK:SU(3): STRXui %1:gpr64, %0:gpr64common, 2
9 ; CHECK:SU(2): STRXui %1:gpr64, %0:gpr64common, 3
10 ; CHECK:SU(5): STRXui %1:gpr64, %0:gpr64common, 4
1111 define i64 @stp_i64_scale(i64* nocapture %P, i64 %v) {
1212 entry:
1313 %arrayidx = getelementptr inbounds i64, i64* %P, i64 3
2525 ; CHECK-LABEL: stp_i32_scale:%bb.0
2626 ; CHECK:Cluster ld/st SU(4) - SU(3)
2727 ; CHECK:Cluster ld/st SU(2) - SU(5)
28 ; CHECK:SU(4): STRWui %1, %0, 1
29 ; CHECK:SU(3): STRWui %1, %0, 2
30 ; CHECK:SU(2): STRWui %1, %0, 3
31 ; CHECK:SU(5): STRWui %1, %0, 4
28 ; CHECK:SU(4): STRWui %1:gpr32, %0:gpr64common, 1
29 ; CHECK:SU(3): STRWui %1:gpr32, %0:gpr64common, 2
30 ; CHECK:SU(2): STRWui %1:gpr32, %0:gpr64common, 3
31 ; CHECK:SU(5): STRWui %1:gpr32, %0:gpr64common, 4
3232 define i32 @stp_i32_scale(i32* nocapture %P, i32 %v) {
3333 entry:
3434 %arrayidx = getelementptr inbounds i32, i32* %P, i32 3
4646 ; CHECK-LABEL:stp_i64_unscale:%bb.0 entry
4747 ; CHECK:Cluster ld/st SU(5) - SU(2)
4848 ; CHECK:Cluster ld/st SU(4) - SU(3)
49 ; CHECK:SU(5): STURXi %1, %0, -32
50 ; CHECK:SU(2): STURXi %1, %0, -24
51 ; CHECK:SU(4): STURXi %1, %0, -16
52 ; CHECK:SU(3): STURXi %1, %0, -8
49 ; CHECK:SU(5): STURXi %1:gpr64, %0:gpr64common, -32
50 ; CHECK:SU(2): STURXi %1:gpr64, %0:gpr64common, -24
51 ; CHECK:SU(4): STURXi %1:gpr64, %0:gpr64common, -16
52 ; CHECK:SU(3): STURXi %1:gpr64, %0:gpr64common, -8
5353 define void @stp_i64_unscale(i64* nocapture %P, i64 %v) #0 {
5454 entry:
5555 %arrayidx = getelementptr inbounds i64, i64* %P, i64 -3
6767 ; CHECK-LABEL:stp_i32_unscale:%bb.0 entry
6868 ; CHECK:Cluster ld/st SU(5) - SU(2)
6969 ; CHECK:Cluster ld/st SU(4) - SU(3)
70 ; CHECK:SU(5): STURWi %1, %0, -16
71 ; CHECK:SU(2): STURWi %1, %0, -12
72 ; CHECK:SU(4): STURWi %1, %0, -8
73 ; CHECK:SU(3): STURWi %1, %0, -4
70 ; CHECK:SU(5): STURWi %1:gpr32, %0:gpr64common, -16
71 ; CHECK:SU(2): STURWi %1:gpr32, %0:gpr64common, -12
72 ; CHECK:SU(4): STURWi %1:gpr32, %0:gpr64common, -8
73 ; CHECK:SU(3): STURWi %1:gpr32, %0:gpr64common, -4
7474 define void @stp_i32_unscale(i32* nocapture %P, i32 %v) #0 {
7575 entry:
7676 %arrayidx = getelementptr inbounds i32, i32* %P, i32 -3
8888 ; CHECK-LABEL:stp_double:%bb.0
8989 ; CHECK:Cluster ld/st SU(3) - SU(4)
9090 ; CHECK:Cluster ld/st SU(2) - SU(5)
91 ; CHECK:SU(3): STRDui %1, %0, 1
92 ; CHECK:SU(4): STRDui %1, %0, 2
93 ; CHECK:SU(2): STRDui %1, %0, 3
94 ; CHECK:SU(5): STRDui %1, %0, 4
91 ; CHECK:SU(3): STRDui %1:fpr64, %0:gpr64common, 1
92 ; CHECK:SU(4): STRDui %1:fpr64, %0:gpr64common, 2
93 ; CHECK:SU(2): STRDui %1:fpr64, %0:gpr64common, 3
94 ; CHECK:SU(5): STRDui %1:fpr64, %0:gpr64common, 4
9595 define void @stp_double(double* nocapture %P, double %v) {
9696 entry:
9797 %arrayidx = getelementptr inbounds double, double* %P, i64 3
109109 ; CHECK-LABEL:stp_float:%bb.0
110110 ; CHECK:Cluster ld/st SU(3) - SU(4)
111111 ; CHECK:Cluster ld/st SU(2) - SU(5)
112 ; CHECK:SU(3): STRSui %1, %0, 1
113 ; CHECK:SU(4): STRSui %1, %0, 2
114 ; CHECK:SU(2): STRSui %1, %0, 3
115 ; CHECK:SU(5): STRSui %1, %0, 4
112 ; CHECK:SU(3): STRSui %1:fpr32, %0:gpr64common, 1
113 ; CHECK:SU(4): STRSui %1:fpr32, %0:gpr64common, 2
114 ; CHECK:SU(2): STRSui %1:fpr32, %0:gpr64common, 3
115 ; CHECK:SU(5): STRSui %1:fpr32, %0:gpr64common, 4
116116 define void @stp_float(float* nocapture %P, float %v) {
117117 entry:
118118 %arrayidx = getelementptr inbounds float, float* %P, i64 3
129129 ; CHECK: ********** MI Scheduling **********
130130 ; CHECK-LABEL: stp_volatile:%bb.0
131131 ; CHECK-NOT: Cluster ld/st
132 ; CHECK:SU(2): STRXui %1, %0, 3; mem:Volatile
133 ; CHECK:SU(3): STRXui %1, %0, 2; mem:Volatile
134 ; CHECK:SU(4): STRXui %1, %0, 1; mem:Volatile
135 ; CHECK:SU(5): STRXui %1, %0, 4; mem:Volatile
132 ; CHECK:SU(2): STRXui %1:gpr64, %0:gpr64common, 3; mem:Volatile
133 ; CHECK:SU(3): STRXui %1:gpr64, %0:gpr64common, 2; mem:Volatile
134 ; CHECK:SU(4): STRXui %1:gpr64, %0:gpr64common, 1; mem:Volatile
135 ; CHECK:SU(5): STRXui %1:gpr64, %0:gpr64common, 4; mem:Volatile
136136 define i64 @stp_volatile(i64* nocapture %P, i64 %v) {
137137 entry:
138138 %arrayidx = getelementptr inbounds i64, i64* %P, i64 3
55 ;
66 ; CHECK: ********** MI Scheduling **********
77 ; CHECK: shiftable
8 ; CHECK: SU(2): %2:gpr64common = SUBXri %1, 20, 0
8 ; CHECK: SU(2): %2:gpr64common = SUBXri %1:gpr64common, 20, 0
99 ; CHECK: Successors:
1010 ; CHECK-NEXT: SU(4): Data Latency=1 Reg=%2
1111 ; CHECK-NEXT: SU(3): Data Latency=2 Reg=%2
44 ;
55 ; CHECK: ********** MI Scheduling **********
66 ; CHECK: misched_bug:%bb.0 entry
7 ; CHECK: SU(2): %2:gpr32 = LDRWui %0, 1; mem:LD4[%ptr1_plus1]
7 ; CHECK: SU(2): %2:gpr32 = LDRWui %0:gpr64common, 1; mem:LD4[%ptr1_plus1]
88 ; CHECK: Successors:
99 ; CHECK-NEXT: SU(5): Data Latency=4 Reg=%2
1010 ; CHECK-NEXT: SU(4): Ord Latency=0
11 ; CHECK: SU(3): STRWui %wzr, %0, 0; mem:ST4[%ptr1]
11 ; CHECK: SU(3): STRWui %wzr, %0:gpr64common, 0; mem:ST4[%ptr1]
1212 ; CHECK: Successors:
1313 ; CHECK: SU(4): Ord Latency=0
14 ; CHECK: SU(4): STRWui %wzr, %1, 0; mem:ST4[%ptr2]
14 ; CHECK: SU(4): STRWui %wzr, %1:gpr64common, 0; mem:ST4[%ptr2]
1515 ; CHECK: SU(5): %w0 = COPY %2
1616 ; CHECK: ** ScheduleDAGMI::schedule picking next node
1717 define i32 @misched_bug(i32* %ptr1, i32* %ptr2) {
4141 # CHECK_SWIFT: Latency : 2
4242 # CHECK_R52: Latency : 2
4343 #
44 # CHECK: SU(3): %3:rgpr = t2LDRi12 %2, 0, 14, %noreg; mem:LD4[@g1](dereferenceable)
44 # CHECK: SU(3): %3:rgpr = t2LDRi12 %2:rgpr, 0, 14, %noreg; mem:LD4[@g1](dereferenceable)
4545 # CHECK_A9: Latency : 1
4646 # CHECK_SWIFT: Latency : 3
4747 # CHECK_R52: Latency : 4
4848 #
49 # CHECK : SU(6): %6 = t2ADDrr %3, %3, 14, %noreg, %noreg
49 # CHECK : SU(6): %6 = t2ADDrr %3:rgpr, %3:rgpr, 14, %noreg, %noreg
5050 # CHECK_A9: Latency : 1
5151 # CHECK_SWIFT: Latency : 1
5252 # CHECK_R52: Latency : 3
5353
54 # CHECK: SU(7): %7:rgpr = t2SDIV %6, %5, 14, %noreg
54 # CHECK: SU(7): %7:rgpr = t2SDIV %6:rgpr, %5:rgpr, 14, %noreg
5555 # CHECK_A9: Latency : 0
5656 # CHECK_SWIFT: Latency : 14
5757 # CHECK_R52: Latency : 8
5858
59 # CHECK: SU(8): t2STRi12 %7, %2, 0, 14, %noreg; mem:ST4[@g1]
59 # CHECK: SU(8): t2STRi12 %7:rgpr, %2:rgpr, 0, 14, %noreg; mem:ST4[@g1]
6060 # CHECK_A9: Latency : 1
6161 # CHECK_SWIFT: Latency : 0
6262 # CHECK_R52: Latency : 4
6363 #
64 # CHECK: SU(9): %8:rgpr = t2SMULBB %1, %1, 14, %noreg
64 # CHECK: SU(9): %8:rgpr = t2SMULBB %1:rgpr, %1:rgpr, 14, %noreg
6565 # CHECK_A9: Latency : 2
6666 # CHECK_SWIFT: Latency : 4
6767 # CHECK_R52: Latency : 4
6868 #
69 # CHECK: SU(10): %9:rgpr = t2SMLABB %0, %0, %8, 14, %noreg
69 # CHECK: SU(10): %9:rgpr = t2SMLABB %0:rgpr, %0:rgpr, %8:rgpr, 14, %noreg
7070 # CHECK_A9: Latency : 2
7171 # CHECK_SWIFT: Latency : 4
7272 # CHECK_R52: Latency : 4
7373 #
74 # CHECK: SU(11): %10:rgpr = t2UXTH %9, 0, 14, %noreg
74 # CHECK: SU(11): %10:rgpr = t2UXTH %9:rgpr, 0, 14, %noreg
7575 # CHECK_A9: Latency : 1
7676 # CHECK_SWIFT: Latency : 1
7777 # CHECK_R52: Latency : 3
7878 #
79 # CHECK: SU(12): %11:rgpr = t2MUL %10, %7, 14, %noreg
79 # CHECK: SU(12): %11:rgpr = t2MUL %10:rgpr, %7:rgpr, 14, %noreg
8080 # CHECK_A9: Latency : 2
8181 # CHECK_SWIFT: Latency : 4
8282 # CHECK_R52: Latency : 4
8383 #
84 # CHECK: SU(13): %12:rgpr = t2MLA %11, %11, %11, 14, %noreg
84 # CHECK: SU(13): %12:rgpr = t2MLA %11:rgpr, %11:rgpr, %11:rgpr, 14, %noreg
8585 # CHECK_A9: Latency : 2
8686 # CHECK_SWIFT: Latency : 4
8787 # CHECK_R52: Latency : 4
8888 #
89 # CHECK: SU(14): %13:rgpr, %14:rgpr = t2UMULL %12, %12, 14, %noreg
89 # CHECK: SU(14): %13:rgpr, %14:rgpr = t2UMULL %12:rgpr, %12:rgpr, 14, %noreg
9090 # CHECK_A9: Latency : 3
9191 # CHECK_SWIFT: Latency : 5
9292 # CHECK_R52: Latency : 4
9393 #
94 # CHECK: SU(18): %19:rgpr, %20:rgpr = t2UMLAL %12, %12, %19, %20, 14, %noreg
94 # CHECK: SU(18): %19:rgpr, %20:rgpr = t2UMLAL %12:rgpr, %12:rgpr, %19:rgpr, %20:rgpr, 14, %noreg
9595 # CHECK_A9: Latency : 3
9696 # CHECK_SWIFT: Latency : 7
9797 # CHECK_R52: Latency : 4
2727 }
2828
2929 # CHECK: ********** MI Scheduling **********
30 # CHECK: SU(2): %2:gpr = SMULBB %1, %1, 14, %noreg
30 # CHECK: SU(2): %2:gpr = SMULBB %1:gpr, %1:gpr, 14, %noreg
3131 # CHECK_A9: Latency : 2
3232 # CHECK_SWIFT: Latency : 4
3333 # CHECK_R52: Latency : 4
3434 #
35 # CHECK: SU(3): %3:gprnopc = SMLABB %0, %0, %2, 14, %noreg
35 # CHECK: SU(3): %3:gprnopc = SMLABB %0:gprnopc, %0:gprnopc, %2:gpr, 14, %noreg
3636 # CHECK_A9: Latency : 2
3737 # CHECK_SWIFT: Latency : 4
3838 # CHECK_R52: Latency : 4
3939 #
40 # CHECK: SU(4): %4:gprnopc = UXTH %3, 0, 14, %noreg
40 # CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, %noreg
4141 # CHECK_A9: Latency : 1
4242 # CHECK_SWIFT: Latency : 1
4343 # CHECK_R52: Latency : 3
4444 #
45 # CHECK: SU(5): %5:gprnopc = MUL %4, %4, 14, %noreg, %noreg
45 # CHECK: SU(5): %5:gprnopc = MUL %4:gprnopc, %4:gprnopc, 14, %noreg, %noreg
4646 # CHECK_A9: Latency : 2
4747 # CHECK_SWIFT: Latency : 4
4848 # CHECK_R52: Latency : 4
4949 #
50 # CHECK: SU(6): %6:gprnopc = MLA %5, %5, %5, 14, %noreg, %noreg
50 # CHECK: SU(6): %6:gprnopc = MLA %5:gprnopc, %5:gprnopc, %5:gprnopc, 14, %noreg, %noreg
5151 # CHECK_A9: Latency : 2
5252 # CHECK_SWIFT: Latency : 4
5353 # CHECK_R52: Latency : 4
5454 #
55 # CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6, %6, 14, %noreg, %noreg
55 # CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6:gprnopc, %6:gprnopc, 14, %noreg, %noreg
5656 # CHECK_A9: Latency : 3
5757 # CHECK_SWIFT: Latency : 5
5858 # CHECK_R52: Latency : 4
5959 #
60 # CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6, %6, %13, %14, 14, %noreg, %noreg
60 # CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr, %14:gprnopc, 14, %noreg, %noreg
6161 # CHECK_SWIFT: Latency : 7
6262 # CHECK_A9: Latency : 3
6363 # CHECK_R52: Latency : 4
1919
2020 # CHECK: ********** MI Scheduling **********
2121 # CHECK: ScheduleDAGMILive::schedule starting
22 # CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0, 8, 14, %noreg; mem:LD32[%A](align=8)
22 # CHECK: SU(1): %1:qqpr = VLD4d8Pseudo %0:gpr, 8, 14, %noreg; mem:LD32[%A](align=8)
2323 # CHECK: Latency : 8
2424 # CHECK: Single Issue : true;
25 # CHECK: SU(2): %4:dpr = VADDv8i8 %1.dsub_0, %1.dsub_1, 14, %noreg
25 # CHECK: SU(2): %4:dpr = VADDv8i8 %1.dsub_0:qqpr, %1.dsub_1:qqpr, 14, %noreg
2626 # CHECK: Latency : 5
2727 # CHECK: Single Issue : false;
28 # CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4, 14, %noreg
28 # CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, %noreg
2929 # CHECK: Latency : 4
3030 # CHECK: Single Issue : false;
3131
77 ; the fallback path.
88
99 ; Check that we fallback on invoke translation failures.
10 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1(s80), %0(p0); mem:ST10[%ptr](align=16) (in function: test_x86_fp80_dump)
10 ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: G_STORE %1:_(s80), %0:_(p0); mem:ST10[%ptr](align=16) (in function: test_x86_fp80_dump)
1111 ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_x86_fp80_dump
1212 ; FALLBACK-WITH-REPORT-OUT-LABEL: test_x86_fp80_dump:
1313 define void @test_x86_fp80_dump(x86_fp80* %ptr){
99 ;
1010 ; CHECK: *** Final schedule for %bb.1 ***
1111 ; CHECK: %eax = COPY
12 ; CHECK-NEXT: MUL32r %{{[0-9]+}}, implicit-def %eax, implicit-def %edx, implicit-def dead %eflags, implicit %eax
12 ; CHECK-NEXT: MUL32r %{{[0-9]+}}:gr32, implicit-def %eax, implicit-def %edx, implicit-def dead %eflags, implicit %eax
1313 ; CHECK-NEXT: COPY %e{{[ad]}}x
1414 ; CHECK-NEXT: COPY %e{{[ad]}}x
1515 ; CHECK: DIVSSrm
117117 // TRI and IntrinsicInfo we can print the operand as a subreg index.
118118 std::string str;
119119 raw_string_ostream OS(str);
120 ModuleSlotTracker DummyMST(nullptr);
121120 MachineOperand::printSubRegIdx(OS, MO.getImm(), nullptr);
122121 ASSERT_TRUE(OS.str() == "%subreg.3");
123122 }
295294 LLVMContext Ctx;
296295 Module M("MachineOperandMDNodeTest", Ctx);
297296 NamedMDNode *MD = M.getOrInsertNamedMetadata("namedmd");
298 ModuleSlotTracker DummyMST(&M);
297 ModuleSlotTracker MST(&M);
299298 Metadata *MDS = MDString::get(Ctx, "foo");
300299 MDNode *Node = MDNode::get(Ctx, MDS);
301300 MD->addOperand(Node);
311310 std::string str;
312311 // Print a MachineOperand containing a metadata node.
313312 raw_string_ostream OS(str);
314 MO.print(OS, DummyMST, LLT{}, false, false, 0, /*TRI=*/nullptr,
313 MO.print(OS, MST, LLT{}, /*PrintDef=*/false, /*IsVerbose=*/false,
314 /*ShouldPrintRegisterTies=*/false, 0, /*TRI=*/nullptr,
315315 /*IntrinsicInfo=*/nullptr);
316316 ASSERT_TRUE(OS.str() == "!0");
317317 }