llvm.org GIT mirror llvm / 96a74c5
remove support for a bunch of obsolete instruction encodings and other backward compatibility hacks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133273 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 9 years ago
21 changed file(s) with 19 addition(s) and 348 deletion(s). Raw diff Collapse all Expand all
222222 FUNC_CODE_INST_UNREACHABLE = 15, // UNREACHABLE
223223
224224 FUNC_CODE_INST_PHI = 16, // PHI: [ty, val0,bb0, ...]
225 FUNC_CODE_INST_MALLOC = 17, // MALLOC: [instty, op, align]
226 FUNC_CODE_INST_FREE = 18, // FREE: [opty, op]
225 // 17 is unused.
226 // 18 is unused.
227227 FUNC_CODE_INST_ALLOCA = 19, // ALLOCA: [instty, op, align]
228228 FUNC_CODE_INST_LOAD = 20, // LOAD: [opty, op, align, vol]
229 // FIXME: Remove STORE in favor of STORE2 in LLVM 3.0
230 FUNC_CODE_INST_STORE = 21, // STORE: [valty,val,ptr, align, vol]
231 // FIXME: Remove CALL in favor of CALL2 in LLVM 3.0
232 FUNC_CODE_INST_CALL = 22, // CALL with potentially invalid metadata
229 // 21 is unused.
230 // 22 is unused.
233231 FUNC_CODE_INST_VAARG = 23, // VAARG: [valistty, valist, instty]
234232 // This store code encodes the pointer type, rather than the value type
235233 // this is so information only available in the pointer type (e.g. address
236234 // spaces) is retained.
237235 FUNC_CODE_INST_STORE2 = 24, // STORE: [ptrty,ptr,val, align, vol]
238 // FIXME: Remove GETRESULT in favor of EXTRACTVAL in LLVM 3.0
239 FUNC_CODE_INST_GETRESULT = 25, // GETRESULT: [ty, opval, n]
236 // 25 is unused.
240237 FUNC_CODE_INST_EXTRACTVAL = 26, // EXTRACTVAL: [n x operands]
241238 FUNC_CODE_INST_INSERTVAL = 27, // INSERTVAL: [n x operands]
242239 // fcmp/icmp returning Int1TY or vector of Int1Ty. Same as CMP, exists to
246243 FUNC_CODE_INST_VSELECT = 29, // VSELECT: [ty,opval,opval,predty,pred]
247244 FUNC_CODE_INST_INBOUNDS_GEP= 30, // INBOUNDS_GEP: [n x operands]
248245 FUNC_CODE_INST_INDIRECTBR = 31, // INDIRECTBR: [opty, op0, op1, ...]
249
250 // FIXME: Remove DEBUG_LOC in favor of DEBUG_LOC2 in LLVM 3.0
251 FUNC_CODE_DEBUG_LOC = 32, // DEBUG_LOC with potentially invalid metadata
246 // 32 is unused.
252247 FUNC_CODE_DEBUG_LOC_AGAIN = 33, // DEBUG_LOC_AGAIN
253248
254249 FUNC_CODE_INST_CALL2 = 34, // CALL2: [attr, fnty, fnid, args...]
20862086 break;
20872087 }
20882088
2089 case bitc::FUNC_CODE_INST_GETRESULT: { // GETRESULT: [ty, val, n]
2090 if (Record.size() != 2)
2091 return Error("Invalid GETRESULT record");
2092 unsigned OpNum = 0;
2093 Value *Op;
2094 getValueTypePair(Record, OpNum, NextValueNo, Op);
2095 unsigned Index = Record[1];
2096 I = ExtractValueInst::Create(Op, Index);
2097 InstructionList.push_back(I);
2098 break;
2099 }
2100
21012089 case bitc::FUNC_CODE_INST_RET: // RET: [opty,opval]
21022090 {
21032091 unsigned Size = Record.size();
21082096 }
21092097
21102098 unsigned OpNum = 0;
2111 SmallVector Vs;
2112 do {
2113 Value *Op = NULL;
2114 if (getValueTypePair(Record, OpNum, NextValueNo, Op))
2115 return Error("Invalid RET record");
2116 Vs.push_back(Op);
2117 } while(OpNum != Record.size());
2118
2119 const Type *ReturnType = F->getReturnType();
2120 // Handle multiple return values. FIXME: Remove in LLVM 3.0.
2121 if (Vs.size() > 1 ||
2122 (ReturnType->isStructTy() &&
2123 (Vs.empty() || Vs[0]->getType() != ReturnType))) {
2124 Value *RV = UndefValue::get(ReturnType);
2125 for (unsigned i = 0, e = Vs.size(); i != e; ++i) {
2126 I = InsertValueInst::Create(RV, Vs[i], i, "mrv");
2127 InstructionList.push_back(I);
2128 CurBB->getInstList().push_back(I);
2129 ValueList.AssignValue(I, NextValueNo++);
2130 RV = I;
2131 }
2132 I = ReturnInst::Create(Context, RV);
2133 InstructionList.push_back(I);
2134 break;
2135 }
2136
2137 I = ReturnInst::Create(Context, Vs[0]);
2099 Value *Op = NULL;
2100 if (getValueTypePair(Record, OpNum, NextValueNo, Op))
2101 return Error("Invalid RET record");
2102 if (OpNum != Record.size())
2103 return Error("Invalid RET record");
2104
2105 I = ReturnInst::Create(Context, Op);
21382106 InstructionList.push_back(I);
21392107 break;
21402108 }
22812249 break;
22822250 }
22832251
2284 case bitc::FUNC_CODE_INST_MALLOC: { // MALLOC: [instty, op, align]
2285 // Autoupgrade malloc instruction to malloc call.
2286 // FIXME: Remove in LLVM 3.0.
2287 if (Record.size() < 3)
2288 return Error("Invalid MALLOC record");
2252 case bitc::FUNC_CODE_INST_ALLOCA: { // ALLOCA: [instty, opty, op, align]
2253 if (Record.size() != 4)
2254 return Error("Invalid ALLOCA record");
22892255 const PointerType *Ty =
22902256 dyn_cast_or_null(getTypeByID(Record[0]));
2291 Value *Size = getFnValueByID(Record[1], Type::getInt32Ty(Context));
2292 if (!Ty || !Size) return Error("Invalid MALLOC record");
2293 if (!CurBB) return Error("Invalid malloc instruction with no BB");
2294 const Type *Int32Ty = IntegerType::getInt32Ty(CurBB->getContext());
2295 Constant *AllocSize = ConstantExpr::getSizeOf(Ty->getElementType());
2296 AllocSize = ConstantExpr::getTruncOrBitCast(AllocSize, Int32Ty);
2297 I = CallInst::CreateMalloc(CurBB, Int32Ty, Ty->getElementType(),
2298 AllocSize, Size, NULL);
2299 InstructionList.push_back(I);
2300 break;
2301 }
2302 case bitc::FUNC_CODE_INST_FREE: { // FREE: [op, opty]
2303 unsigned OpNum = 0;
2304 Value *Op;
2305 if (getValueTypePair(Record, OpNum, NextValueNo, Op) ||
2306 OpNum != Record.size())
2307 return Error("Invalid FREE record");
2308 if (!CurBB) return Error("Invalid free instruction with no BB");
2309 I = CallInst::CreateFree(Op, CurBB);
2310 InstructionList.push_back(I);
2311 break;
2312 }
2313 case bitc::FUNC_CODE_INST_ALLOCA: { // ALLOCA: [instty, opty, op, align]
2314 // For backward compatibility, tolerate a lack of an opty, and use i32.
2315 // Remove this in LLVM 3.0.
2316 if (Record.size() < 3 || Record.size() > 4)
2317 return Error("Invalid ALLOCA record");
2318 unsigned OpNum = 0;
2319 const PointerType *Ty =
2320 dyn_cast_or_null(getTypeByID(Record[OpNum++]));
2321 const Type *OpTy = Record.size() == 4 ? getTypeByID(Record[OpNum++]) :
2322 Type::getInt32Ty(Context);
2323 Value *Size = getFnValueByID(Record[OpNum++], OpTy);
2324 unsigned Align = Record[OpNum++];
2257 const Type *OpTy = getTypeByID(Record[1]);
2258 Value *Size = getFnValueByID(Record[2], OpTy);
2259 unsigned Align = Record[3];
23252260 if (!Ty || !Size) return Error("Invalid ALLOCA record");
23262261 I = new AllocaInst(Ty->getElementType(), Size, (1 << Align) >> 1);
23272262 InstructionList.push_back(I);
23512286 InstructionList.push_back(I);
23522287 break;
23532288 }
2354 case bitc::FUNC_CODE_INST_STORE: { // STORE:[val, valty, ptr, align, vol]
2355 // FIXME: Legacy form of store instruction. Should be removed in LLVM 3.0.
2356 unsigned OpNum = 0;
2357 Value *Val, *Ptr;
2358 if (getValueTypePair(Record, OpNum, NextValueNo, Val) ||
2359 getValue(Record, OpNum,
2360 PointerType::getUnqual(Val->getType()), Ptr)||
2361 OpNum+2 != Record.size())
2362 return Error("Invalid STORE record");
2363
2364 I = new StoreInst(Val, Ptr, Record[OpNum+1], (1 << Record[OpNum]) >> 1);
2365 InstructionList.push_back(I);
2366 break;
2367 }
2368 // FIXME: Remove this in LLVM 3.0.
2369 case bitc::FUNC_CODE_INST_CALL:
23702289 case bitc::FUNC_CODE_INST_CALL2: {
23712290 // CALL: [paramattrs, cc, fnty, fnid, arg0, arg1...]
23722291 if (Record.size() < 3)
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test/Bitcode/AutoUpgradeIntrinsics.ll less more
None ; This isn't really an assembly file. It just runs test on bitcode to ensure
1 ; it is auto-upgraded.
2 ; RUN: llvm-dis < %s.bc | FileCheck %s
3 ; CHECK-NOT: {i32 @llvm\\.ct}
4 ; CHECK-NOT: {llvm\\.part\\.set\\.i\[0-9\]*\\.i\[0-9\]*\\.i\[0-9\]*}
5 ; CHECK-NOT: {llvm\\.part\\.select\\.i\[0-9\]*\\.i\[0-9\]*}
6 ; CHECK-NOT: {llvm\\.bswap\\.i\[0-9\]*\\.i\[0-9\]*}
7
test/Bitcode/AutoUpgradeIntrinsics.ll.bc less more
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test/Bitcode/neon-intrinsics.ll less more
None ; RUN: llvm-dis < %s.bc | FileCheck %s
1
2 ; vmovls should be auto-upgraded to sext
3
4 ; CHECK: vmovls8
5 ; CHECK-NOT: arm.neon.vmovls.v8i16
6 ; CHECK: sext <8 x i8>
7
8 ; CHECK: vmovls16
9 ; CHECK-NOT: arm.neon.vmovls.v4i32
10 ; CHECK: sext <4 x i16>
11
12 ; CHECK: vmovls32
13 ; CHECK-NOT: arm.neon.vmovls.v2i64
14 ; CHECK: sext <2 x i32>
15
16 ; vmovlu should be auto-upgraded to zext
17
18 ; CHECK: vmovlu8
19 ; CHECK-NOT: arm.neon.vmovlu.v8i16
20 ; CHECK: zext <8 x i8>
21
22 ; CHECK: vmovlu16
23 ; CHECK-NOT: arm.neon.vmovlu.v4i32
24 ; CHECK: zext <4 x i16>
25
26 ; CHECK: vmovlu32
27 ; CHECK-NOT: arm.neon.vmovlu.v2i64
28 ; CHECK: zext <2 x i32>
29
30 ; vaddl/vaddw should be auto-upgraded to add with sext/zext
31
32 ; CHECK: vaddls16
33 ; CHECK-NOT: arm.neon.vaddls.v4i32
34 ; CHECK: sext <4 x i16>
35 ; CHECK-NEXT: sext <4 x i16>
36 ; CHECK-NEXT: add <4 x i32>
37
38 ; CHECK: vaddlu32
39 ; CHECK-NOT: arm.neon.vaddlu.v2i64
40 ; CHECK: zext <2 x i32>
41 ; CHECK-NEXT: zext <2 x i32>
42 ; CHECK-NEXT: add <2 x i64>
43
44 ; CHECK: vaddws8
45 ; CHECK-NOT: arm.neon.vaddws.v8i16
46 ; CHECK: sext <8 x i8>
47 ; CHECK-NEXT: add <8 x i16>
48
49 ; CHECK: vaddwu16
50 ; CHECK-NOT: arm.neon.vaddwu.v4i32
51 ; CHECK: zext <4 x i16>
52 ; CHECK-NEXT: add <4 x i32>
53
54 ; vsubl/vsubw should be auto-upgraded to subtract with sext/zext
55
56 ; CHECK: vsubls16
57 ; CHECK-NOT: arm.neon.vsubls.v4i32
58 ; CHECK: sext <4 x i16>
59 ; CHECK-NEXT: sext <4 x i16>
60 ; CHECK-NEXT: sub <4 x i32>
61
62 ; CHECK: vsublu32
63 ; CHECK-NOT: arm.neon.vsublu.v2i64
64 ; CHECK: zext <2 x i32>
65 ; CHECK-NEXT: zext <2 x i32>
66 ; CHECK-NEXT: sub <2 x i64>
67
68 ; CHECK: vsubws8
69 ; CHECK-NOT: arm.neon.vsubws.v8i16
70 ; CHECK: sext <8 x i8>
71 ; CHECK-NEXT: sub <8 x i16>
72
73 ; CHECK: vsubwu16
74 ; CHECK-NOT: arm.neon.vsubwu.v4i32
75 ; CHECK: zext <4 x i16>
76 ; CHECK-NEXT: sub <4 x i32>
77
78 ; vmull* intrinsics will remain intrinsics
79
80 ; CHECK: vmulls8
81 ; CHECK: arm.neon.vmulls.v8i16
82
83 ; CHECK: vmullu16
84 ; CHECK: arm.neon.vmullu.v4i32
85
86 ; CHECK: vmullp8
87 ; CHECK: arm.neon.vmullp.v8i16
88
89 ; vmlal should be auto-upgraded to multiply/add with sext/zext
90
91 ; CHECK: vmlals32
92 ; CHECK-NOT: arm.neon.vmlals.v2i64
93 ; CHECK: sext <2 x i32>
94 ; CHECK-NEXT: sext <2 x i32>
95 ; CHECK-NEXT: mul <2 x i64>
96 ; CHECK-NEXT: add <2 x i64>
97
98 ; CHECK: vmlalu8
99 ; CHECK-NOT: arm.neon.vmlalu.v8i16
100 ; CHECK: zext <8 x i8>
101 ; CHECK-NEXT: zext <8 x i8>
102 ; CHECK-NEXT: mul <8 x i16>
103 ; CHECK-NEXT: add <8 x i16>
104
105 ; vmlsl should be auto-upgraded to multiply/sub with sext/zext
106
107 ; CHECK: vmlsls16
108 ; CHECK-NOT: arm.neon.vmlsls.v4i32
109 ; CHECK: sext <4 x i16>
110 ; CHECK-NEXT: sext <4 x i16>
111 ; CHECK-NEXT: mul <4 x i32>
112 ; CHECK-NEXT: sub <4 x i32>
113
114 ; CHECK: vmlslu32
115 ; CHECK-NOT: arm.neon.vmlslu.v2i64
116 ; CHECK: zext <2 x i32>
117 ; CHECK-NEXT: zext <2 x i32>
118 ; CHECK-NEXT: mul <2 x i64>
119 ; CHECK-NEXT: sub <2 x i64>
120
121 ; vaba should be auto-upgraded to vabd + add
122
123 ; CHECK: vabas32
124 ; CHECK-NOT: arm.neon.vabas.v2i32
125 ; CHECK: arm.neon.vabds.v2i32
126 ; CHECK-NEXT: add <2 x i32>
127
128 ; CHECK: vabaQu8
129 ; CHECK-NOT: arm.neon.vabau.v16i8
130 ; CHECK: arm.neon.vabdu.v16i8
131 ; CHECK-NEXT: add <16 x i8>
132
133 ; vabal should be auto-upgraded to vabd with zext + add
134
135 ; CHECK: vabals16
136 ; CHECK-NOT: arm.neon.vabals.v4i32
137 ; CHECK: arm.neon.vabds.v4i16
138 ; CHECK-NEXT: zext <4 x i16>
139 ; CHECK-NEXT: add <4 x i32>
140
141 ; CHECK: vabalu32
142 ; CHECK-NOT: arm.neon.vabalu.v2i64
143 ; CHECK: arm.neon.vabdu.v2i32
144 ; CHECK-NEXT: zext <2 x i32>
145 ; CHECK-NEXT: add <2 x i64>
146
147 ; vabdl should be auto-upgraded to vabd with zext
148
149 ; CHECK: vabdls8
150 ; CHECK-NOT: arm.neon.vabdls.v8i16
151 ; CHECK: arm.neon.vabds.v8i8
152 ; CHECK-NEXT: zext <8 x i8>
153
154 ; CHECK: vabdlu16
155 ; CHECK-NOT: arm.neon.vabdlu.v4i32
156 ; CHECK: arm.neon.vabdu.v4i16
157 ; CHECK-NEXT: zext <4 x i16>
158
159 ; vmovn should be auto-upgraded to trunc
160
161 ; CHECK: vmovni16
162 ; CHECK-NOT: arm.neon.vmovn.v8i8
163 ; CHECK: trunc <8 x i16>
164
165 ; CHECK: vmovni32
166 ; CHECK-NOT: arm.neon.vmovn.v4i16
167 ; CHECK: trunc <4 x i32>
168
169 ; CHECK: vmovni64
170 ; CHECK-NOT: arm.neon.vmovn.v2i32
171 ; CHECK: trunc <2 x i64>
172
173 ; vld* and vst* intrinsic calls need an alignment argument (defaulted to 1)
174
175 ; CHECK: vld1i8
176 ; CHECK: i32 1
177 ; CHECK: vld2Qi16
178 ; CHECK: i32 1
179 ; CHECK: vld3i32
180 ; CHECK: i32 1
181 ; CHECK: vld4Qf
182 ; CHECK: i32 1
183
184 ; CHECK: vst1i8
185 ; CHECK: i32 1
186 ; CHECK: vst2Qi16
187 ; CHECK: i32 1
188 ; CHECK: vst3i32
189 ; CHECK: i32 1
190 ; CHECK: vst4Qf
191 ; CHECK: i32 1
192
193 ; CHECK: vld2laneQi16
194 ; CHECK: i32 1
195 ; CHECK: vld3lanei32
196 ; CHECK: i32 1
197 ; CHECK: vld4laneQf
198 ; CHECK: i32 1
199
200 ; CHECK: vst2laneQi16
201 ; CHECK: i32 1
202 ; CHECK: vst3lanei32
203 ; CHECK: i32 1
204 ; CHECK: vst4laneQf
205 ; CHECK: i32 1
test/Bitcode/neon-intrinsics.ll.bc less more
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test/Bitcode/sse2_loadl_pd.ll less more
None ; RUN: llvm-dis < %s.bc | FileCheck %s
1 ; CHECK-NOT: {i32 @llvm\\.loadl.pd}
2 ; CHECK: shufflevector
test/Bitcode/sse2_loadl_pd.ll.bc less more
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test/Bitcode/sse2_movl_dq.ll less more
None ; RUN: llvm-dis < %s.bc | FileCheck %s
1 ; CHECK-NOT: {i32 @llvm\\.movl.dq}
2 ; CHECK: shufflevector
test/Bitcode/sse2_movl_dq.ll.bc less more
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test/Bitcode/sse2_movs_d.ll less more
None ; RUN: llvm-dis < %s.bc | FileCheck %s
1 ; CHECK-NOT: {i32 @llvm\\.movs.d}
2 ; CHECK: shufflevector
test/Bitcode/sse2_movs_d.ll.bc less more
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test/Bitcode/sse2_punpck_qdq.ll less more
None ; RUN: llvm-dis < %s.bc | FileCheck %s
1 ; CHECK-NOT: {i32 @llvm\\.punpckh.qdq}
2 ; CHECK-NOT: {i32 @llvm\\.punpckl.qdq}
3 ; CHECK: shufflevector
test/Bitcode/sse2_punpck_qdq.ll.bc less more
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test/Bitcode/sse2_shuf_pd.ll less more
None ; RUN: llvm-dis < %s.bc | FileCheck %s
1 ; CHECK-NOT: {i32 @llvm\\.shuf.pd}
2 ; CHECK: shufflevector
test/Bitcode/sse2_shuf_pd.ll.bc less more
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test/Bitcode/sse2_unpck_pd.ll less more
None ; RUN: llvm-dis < %s.bc | FileCheck %s
1 ; CHECK-NOT: {i32 @llvm\\.unpckh.pd}
2 ; CHECK-NOT: {i32 @llvm\\.unpckl.pd}
3 ; CHECK: shufflevector
test/Bitcode/sse2_unpck_pd.ll.bc less more
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test/Bitcode/sse41_pmulld.ll less more
None ; RUN: llvm-dis < %s.bc | FileCheck %s
1 ; CHECK-NOT: {i32 @llvm\\.pmulld}
2 ; CHECK: mul
test/Bitcode/sse41_pmulld.ll.bc less more
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229229 case bitc::FUNC_CODE_INST_UNREACHABLE: return "INST_UNREACHABLE";
230230
231231 case bitc::FUNC_CODE_INST_PHI: return "INST_PHI";
232 case bitc::FUNC_CODE_INST_MALLOC: return "INST_MALLOC";
233 case bitc::FUNC_CODE_INST_FREE: return "INST_FREE";
234232 case bitc::FUNC_CODE_INST_ALLOCA: return "INST_ALLOCA";
235233 case bitc::FUNC_CODE_INST_LOAD: return "INST_LOAD";
236 case bitc::FUNC_CODE_INST_STORE: return "INST_STORE";
237 case bitc::FUNC_CODE_INST_CALL: return "INST_CALL";
238234 case bitc::FUNC_CODE_INST_VAARG: return "INST_VAARG";
239235 case bitc::FUNC_CODE_INST_STORE2: return "INST_STORE2";
240 case bitc::FUNC_CODE_INST_GETRESULT: return "INST_GETRESULT";
241236 case bitc::FUNC_CODE_INST_EXTRACTVAL: return "INST_EXTRACTVAL";
242237 case bitc::FUNC_CODE_INST_INSERTVAL: return "INST_INSERTVAL";
243238 case bitc::FUNC_CODE_INST_CMP2: return "INST_CMP2";
244239 case bitc::FUNC_CODE_INST_VSELECT: return "INST_VSELECT";
245 case bitc::FUNC_CODE_DEBUG_LOC: return "DEBUG_LOC";
246240 case bitc::FUNC_CODE_DEBUG_LOC_AGAIN: return "DEBUG_LOC_AGAIN";
247241 case bitc::FUNC_CODE_INST_CALL2: return "INST_CALL2";
248242 case bitc::FUNC_CODE_DEBUG_LOC2: return "DEBUG_LOC2";