llvm.org GIT mirror llvm / 969c9ef
Mark the invoke call instruction as implicitly defining the callee-saved registers. The callee-saved registers cannot be live across an invoke call because the control flow may continue along the exceptional edge. When this happens, all of the callee-saved registers are no longer valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142018 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 8 years ago
1 changed file(s) with 31 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
58825882 PrevMBB = CurMBB;
58835883 }
58845884
5885 // Remove the landing pad successor from the invoke block and replace it with
5886 // the new dispatch block.
5885 const ARMBaseInstrInfo *AII = static_cast(TII);
5886 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
5887 const unsigned *SavedRegs = RI.getCalleeSavedRegs(MF);
58875888 for (SmallPtrSet::iterator
58885889 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
58895890 MachineBasicBlock *BB = *I;
5891
5892 // Remove the landing pad successor from the invoke block and replace it
5893 // with the new dispatch block.
58905894 for (MachineBasicBlock::succ_iterator
58915895 SI = BB->succ_begin(), SE = BB->succ_end(); SI != SE; ++SI) {
58925896 MachineBasicBlock *SMBB = *SI;
58975901 }
58985902
58995903 BB->addSuccessor(DispatchBB);
5904
5905 // Find the invoke call and mark all of the callee-saved registers as
5906 // 'implicit defined' so that they're spilled. This prevents code from
5907 // moving instructions to before the EH block, where they will never be
5908 // executed.
5909 for (MachineBasicBlock::reverse_iterator
5910 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
5911 if (!II->getDesc().isCall()) continue;
5912
5913 DenseMap DefRegs;
5914 for (MachineInstr::mop_iterator
5915 OI = II->operands_begin(), OE = II->operands_end();
5916 OI != OE; ++OI) {
5917 if (!OI->isReg()) continue;
5918 DefRegs[OI->getReg()] = true;
5919 }
5920
5921 MachineInstrBuilder MIB(&*II);
5922
5923 for (unsigned i = 0; SavedRegs[i] != 0; ++i)
5924 if (!DefRegs[SavedRegs[i]])
5925 MIB.addReg(SavedRegs[i], RegState::Implicit | RegState::Define);
5926
5927 break;
5928 }
59005929 }
59015930
59025931 // The instruction is gone now.