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[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621 Reviewers: vpykhtin, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D35902 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310251 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitry Preobrazhensky 2 years ago
9 changed file(s) with 538 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
163163 ImmTyOpSelHi,
164164 ImmTyNegLo,
165165 ImmTyNegHi,
166 ImmTySwizzle
166 ImmTySwizzle,
167 ImmTyHigh
167168 };
168169
169170 struct TokOp {
311312 bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
312313 bool isNegLo() const { return isImmTy(ImmTyNegLo); }
313314 bool isNegHi() const { return isImmTy(ImmTyNegHi); }
315 bool isHigh() const { return isImmTy(ImmTyHigh); }
314316
315317 bool isMod() const {
316318 return isClampSI() || isOModSI();
672674 case ImmTyNegLo: OS << "NegLo"; break;
673675 case ImmTyNegHi: OS << "NegHi"; break;
674676 case ImmTySwizzle: OS << "Swizzle"; break;
677 case ImmTyHigh: OS << "High"; break;
675678 }
676679 }
677680
10621065 void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
10631066 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
10641067 void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
1068
1069 void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
10651070
10661071 void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
10671072 bool IsAtomic = false);
40194024 {"glc", AMDGPUOperand::ImmTyGLC, true, nullptr},
40204025 {"slc", AMDGPUOperand::ImmTySLC, true, nullptr},
40214026 {"tfe", AMDGPUOperand::ImmTyTFE, true, nullptr},
4027 {"high", AMDGPUOperand::ImmTyHigh, true, nullptr},
40224028 {"clamp", AMDGPUOperand::ImmTyClampSI, true, nullptr},
40234029 {"omod", AMDGPUOperand::ImmTyOModSI, false, ConvertOmodMul},
40244030 {"unorm", AMDGPUOperand::ImmTyUNorm, true, nullptr},
41194125 && Desc.OpInfo[OpNum + 1].RegClass != -1
41204126 // 4. Next register is not tied to any other operand
41214127 && Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1;
4128 }
4129
4130 void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands) {
4131
4132 OptionalImmIndexMap OptionalIdx;
4133 unsigned Opc = Inst.getOpcode();
4134
4135 unsigned I = 1;
4136 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
4137 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
4138 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
4139 }
4140
4141 for (unsigned E = Operands.size(); I != E; ++I) {
4142 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
4143 if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
4144 Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
4145 } else if (Op.isInterpSlot() ||
4146 Op.isInterpAttr() ||
4147 Op.isAttrChan()) {
4148 Inst.addOperand(MCOperand::createImm(Op.Imm.Val));
4149 } else if (Op.isImmModifier()) {
4150 OptionalIdx[Op.getImmTy()] = I;
4151 } else {
4152 llvm_unreachable("unhandled operand type");
4153 }
4154 }
4155
4156 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::high) != -1) {
4157 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyHigh);
4158 }
4159
4160 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
4161 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
4162 }
4163
4164 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
4165 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
4166 }
41224167 }
41234168
41244169 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
980980 printIfSet(MI, OpNo, O, "_SAT");
981981 }
982982
983 void AMDGPUInstPrinter::printHigh(const MCInst *MI, unsigned OpNo,
984 const MCSubtargetInfo &STI,
985 raw_ostream &O) {
986 if (MI->getOperand(OpNo).getImm())
987 O << " high";
988 }
989
983990 void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo,
984991 const MCSubtargetInfo &STI,
985992 raw_ostream &O) {
169169 char Asm);
170170 void printAbs(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
171171 raw_ostream &O);
172 void printHigh(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
173 raw_ostream &O);
172174 void printClamp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
173175 raw_ostream &O);
174176 void printClampSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
555555
556556 def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
557557 def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
558 def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>;
558559
559560 def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
560561 def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
15101511 field bit HasClamp = HasModifiers;
15111512 field bit HasSDWAClamp = EmitDst;
15121513 field bit HasFPClamp = BitAnd.ret, HasClamp>.ret;
1514 field bit HasHigh = 0;
15131515
15141516 field bit IsPacked = isPackedType.ret;
15151517 field bit HasOpSel = IsPacked;
171171
172172 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
173173 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
174 }
175
176 //===----------------------------------------------------------------------===//
177 // VOP3 INTERP
178 //===----------------------------------------------------------------------===//
179
180 class VOP3Interp : VOP3_Pseudo {
181 let AsmMatchConverter = "cvtVOP3Interp";
182 }
183
184 def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
185 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
186 Attr:$attr, AttrChan:$attrchan,
187 clampmod:$clamp, omod:$omod);
188
189 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
190 }
191
192 def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
193 let Ins64 = (ins InterpSlot:$src0,
194 Attr:$attr, AttrChan:$attrchan,
195 clampmod:$clamp, omod:$omod);
196
197 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
198
199 let HasClamp = 1;
200 }
201
202 class getInterp16Asm {
203 string src2 = !if(HasSrc2, ", $src2_modifiers", "");
204 string omod = !if(HasOMod, "$omod", "");
205 string ret =
206 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
207 }
208
209 class getInterp16Ins
210 Operand Src0Mod, Operand Src2Mod> {
211 dag ret = !if(HasSrc2,
212 !if(HasOMod,
213 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
214 Attr:$attr, AttrChan:$attrchan,
215 Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
216 highmod:$high, clampmod:$clamp, omod:$omod),
217 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
218 Attr:$attr, AttrChan:$attrchan,
219 Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
220 highmod:$high, clampmod:$clamp)
221 ),
222 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
223 Attr:$attr, AttrChan:$attrchan,
224 highmod:$high, clampmod:$clamp, omod:$omod)
225 );
226 }
227
228 class VOP3_INTERP16 ArgVT> : VOPProfile {
229
230 let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1);
231 let HasHigh = 1;
232
233 let Outs64 = (outs VGPR_32:$vdst);
234 let Ins64 = getInterp16Ins.ret;
235 let Asm64 = getInterp16Asm.ret;
174236 }
175237
176238 //===----------------------------------------------------------------------===//
314376 let isCommutable = 1 in {
315377
316378 def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile, fma>;
317 def V_INTERP_P1LL_F16 : VOP3Inst <"v_interp_p1ll_f16", VOP3_Profile>;
318 def V_INTERP_P1LV_F16 : VOP3Inst <"v_interp_p1lv_f16", VOP3_Profile>;
319 def V_INTERP_P2_F16 : VOP3Inst <"v_interp_p2_f16", VOP3_Profile>;
379
380 def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
381 def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
382 def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
383
320384 def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile, fmad>;
321385
322386 def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile>;
326390 } // End SubtargetPredicate = Has16BitInsts
327391
328392 let SubtargetPredicate = isVI in {
393 def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
394 def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
395 def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
396
329397 def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile>;
330398 } // End SubtargetPredicate = isVI
331399
511579 VOP3OpSel_gfx9 (NAME).Pfl>;
512580 }
513581
582 multiclass VOP3Interp_Real_vi op> {
583 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
584 VOP3Interp_vi (NAME).Pfl>;
585 }
586
514587 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
515588
516589 defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
566639 defm V_FMA_F16 : VOP3_Real_vi <0x1ee>;
567640 defm V_DIV_FIXUP_F16 : VOP3_Real_vi <0x1ef>;
568641
569 defm V_INTERP_P1LL_F16 : VOP3_Real_vi <0x274>;
570 defm V_INTERP_P1LV_F16 : VOP3_Real_vi <0x275>;
571 defm V_INTERP_P2_F16 : VOP3_Real_vi <0x276>;
642 defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>;
643 defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>;
644 defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
645
646 defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>;
647 defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>;
648 defm V_INTERP_P2_F16 : VOP3Interp_Real_vi <0x276>;
572649 defm V_ADD_F64 : VOP3_Real_vi <0x280>;
573650 defm V_MUL_F64 : VOP3_Real_vi <0x281>;
574651 defm V_MIN_F64 : VOP3_Real_vi <0x282>;
203203 let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0);
204204 }
205205
206 // NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
207 class VOP3Interp_vi op, VOPProfile P> : VOP3e_vi {
208 bits<2> attrchan;
209 bits<6> attr;
210 bits<1> high;
211
212 let Inst{8} = 0; // No modifiers for src0
213 let Inst{61} = 0;
214
215 let Inst{9} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0);
216 let Inst{62} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
217
218 let Inst{37-32} = attr;
219 let Inst{39-38} = attrchan;
220 let Inst{40} = !if(P.HasHigh, high, 0);
221
222 let Inst{49-41} = src0;
223 }
224
206225 class VOP3be : Enc64 {
207226 bits<8> vdst;
208227 bits<2> src0_modifiers;
4343 // GCN: error: invalid operand for instruction
4444
4545 v_cvt_u32_f32_e64 v0, v1 div:2
46 // GCN: error: invalid operand for instruction
46 // GCN: error: invalid operand for instruction
47
48 //
49 // v_interp*
50 //
51
52 v_interp_mov_f32_e64 v5, p10, attr0.x high
53 // GCN: error: invalid operand for instruction
54
55 v_interp_mov_f32_e64 v5, p10, attr0.x v0
56 // GCN: error: invalid operand for instruction
57
58 v_interp_p1_f32_e64 v5, v2, attr0.x high
59 // GCN: error: invalid operand for instruction
60
61 v_interp_p1_f32_e64 v5, v2, attr0.x v0
62 // GCN: error: invalid operand for instruction
63
64 v_interp_p2_f32_e64 v255, v2, attr0.x high
65 // GCN: error: invalid operand for instruction
66
67 v_interp_p2_f32_e64 v255, v2, attr0.x v0
68 // GCN: error: invalid operand for instruction
69
70 v_interp_p1ll_f16 v5, p0, attr31.x
71 // GCN: error: invalid operand for instruction
72
73 v_interp_p1ll_f16 v5, v2, attr31.x v0
74 // GCN: error: invalid operand for instruction
75
76 v_interp_p2_f16 v5, v2, attr1.x, v3 mul:2
77 // GFX67: error: not a valid operand
78 // GFX89: error: invalid operand for instruction
434434 v_cubeid_f32 v0, |-1|, |-1.0|, |1.0|
435435 // SICI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0x88,0xd2,0xc1,0xe6,0xc9,0x03]
436436 // VI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0xc4,0xd1,0xc1,0xe6,0xc9,0x03]
437
438 //
439 // v_interp*
440 //
441
442 v_interp_mov_f32_e64 v5, p10, attr0.x
443 // NOSICI: error: instruction not supported on this GPU
444 // VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
445
446 v_interp_mov_f32_e64 v5, p10, attr32.x
447 // NOSICI: error: instruction not supported on this GPU
448 // VI: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
449
450 v_interp_mov_f32_e64 v5, p20, attr0.x
451 // NOSICI: error: instruction not supported on this GPU
452 // VI: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
453
454 v_interp_mov_f32_e64 v5, p10, attr0.w
455 // NOSICI: error: instruction not supported on this GPU
456 // VI: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
457
458 v_interp_mov_f32_e64 v5, p10, attr0.x clamp
459 // NOSICI: error: invalid operand for instruction
460 // VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
461
462 v_interp_mov_f32 v5, p10, attr0.x clamp
463 // NOSICI: error: invalid operand for instruction
464 // VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
465
466 v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
467 // NOSICI: error: not a valid operand
468 // VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
469
470 v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
471 // NOSICI: error: not a valid operand
472 // VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
473
474 v_interp_mov_f32_e64 v5, p10, attr0.x div:2
475 // NOSICI: error: not a valid operand
476 // VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
477
478 v_interp_mov_f32 v5, p10, attr0.x div:2
479 // NOSICI: error: not a valid operand
480 // VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
481
482
483 v_interp_p1_f32_e64 v5, v2, attr0.x
484 // NOSICI: error: instruction not supported on this GPU
485 // VI: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
486
487 v_interp_p1_f32_e64 v5, v2, attr0.y
488 // NOSICI: error: instruction not supported on this GPU
489 // VI: v_interp_p1_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x70,0xd2,0x40,0x04,0x02,0x00]
490
491 v_interp_p1_f32_e64 v5, -v2, attr0.x
492 // NOSICI: error: invalid operand for instruction
493 // VI: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
494
495 v_interp_p1_f32_e64 v5, |v2|, attr0.x
496 // NOSICI: error: not a valid operand
497 // VI: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
498
499 v_interp_p1_f32_e64 v5, v2, attr0.x clamp
500 // NOSICI: error: invalid operand for instruction
501 // VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
502
503 v_interp_p1_f32 v5, v2, attr0.x clamp
504 // NOSICI: error: invalid operand for instruction
505 // VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
506
507 v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
508 // NOSICI: error: not a valid operand
509 // VI: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
510
511
512 v_interp_p2_f32_e64 v255, v2, attr0.x
513 // NOSICI: error: instruction not supported on this GPU
514 // VI: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
515
516 v_interp_p2_f32_e64 v5, v2, attr31.x
517 // NOSICI: error: instruction not supported on this GPU
518 // VI: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
519
520 v_interp_p2_f32_e64 v5, -v2, attr0.x
521 // NOSICI: error: invalid operand for instruction
522 // VI: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
523
524 v_interp_p2_f32_e64 v5, |v2|, attr0.x
525 // NOSICI: error: not a valid operand
526 // VI: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
527
528 v_interp_p2_f32_e64 v5, v2, attr0.x clamp
529 // NOSICI: error: invalid operand for instruction
530 // VI: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
531
532 v_interp_p2_f32_e64 v5, v2, attr0.x div:2
533 // NOSICI: error: not a valid operand
534 // VI: v_interp_p2_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x18]
535
536
537 v_interp_p1ll_f16 v5, v2, attr31.x
538 // NOSICI: error: invalid operand for instruction
539 // VI: v_interp_p1ll_f16 v5, v2, attr31.x ; encoding: [0x05,0x00,0x74,0xd2,0x1f,0x04,0x02,0x00]
540
541 v_interp_p1ll_f16 v5, v2, attr0.w
542 // NOSICI: error: invalid operand for instruction
543 // VI: v_interp_p1ll_f16 v5, v2, attr0.w ; encoding: [0x05,0x00,0x74,0xd2,0xc0,0x04,0x02,0x00]
544
545 v_interp_p1ll_f16 v5, -v2, attr0.x
546 // NOSICI: error: invalid operand for instruction
547 // VI: v_interp_p1ll_f16 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
548
549 v_interp_p1ll_f16 v5, |v2|, attr0.x
550 // NOSICI: error: not a valid operand
551 // VI: v_interp_p1ll_f16 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
552
553 v_interp_p1ll_f16 v5, v2, attr0.x high
554 // NOSICI: error: invalid operand for instruction
555 // VI: v_interp_p1ll_f16 v5, v2, attr0.x high ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
556
557 v_interp_p1ll_f16 v5, v2, attr0.x clamp
558 // NOSICI: error: invalid operand for instruction
559 // VI: v_interp_p1ll_f16 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
560
561 v_interp_p1ll_f16 v5, v2, attr0.x mul:4
562 // NOSICI: error: not a valid operand
563 // VI: v_interp_p1ll_f16 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x10]
564
565
566 v_interp_p1lv_f16 v5, v2, attr1.x, v3
567 // NOSICI: error: invalid operand for instruction
568 // VI: v_interp_p1lv_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x01,0x04,0x0e,0x04]
569
570 v_interp_p1lv_f16 v5, v2, attr0.z, v3
571 // NOSICI: error: invalid operand for instruction
572 // VI: v_interp_p1lv_f16 v5, v2, attr0.z, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x80,0x04,0x0e,0x04]
573
574 v_interp_p1lv_f16 v5, -v2, attr0.x, v3
575 // NOSICI: error: invalid operand for instruction
576 // VI: v_interp_p1lv_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
577
578 v_interp_p1lv_f16 v5, v2, attr0.x, -v3
579 // NOSICI: error: invalid operand for instruction
580 // VI: v_interp_p1lv_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
581
582 v_interp_p1lv_f16 v5, |v2|, attr0.x, v3
583 // NOSICI: error: not a valid operand
584 // VI: v_interp_p1lv_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
585
586 v_interp_p1lv_f16 v5, v2, attr0.x, |v3|
587 // NOSICI: error: not a valid operand
588 // VI: v_interp_p1lv_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
589
590 v_interp_p1lv_f16 v5, v2, attr0.x, v3 high
591 // NOSICI: error: invalid operand for instruction
592 // VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
593
594 v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp
595 // NOSICI: error: invalid operand for instruction
596 // VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
597
598 v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2
599 // NOSICI: error: not a valid operand
600 // VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x0c]
601
602 v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2
603 // NOSICI: error: not a valid operand
604 // VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x1c]
605
606
607 v_interp_p2_f16 v5, v2, attr1.x, v3
608 // NOSICI: error: invalid operand for instruction
609 // VI: v_interp_p2_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
610
611 v_interp_p2_f16 v5, v2, attr32.x, v3
612 // NOSICI: error: invalid operand for instruction
613 // VI: v_interp_p2_f16 v5, v2, attr32.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x20,0x04,0x0e,0x04]
614
615 v_interp_p2_f16 v5, v2, attr0.w, v3
616 // NOSICI: error: invalid operand for instruction
617 // VI: v_interp_p2_f16 v5, v2, attr0.w, v3 ; encoding: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
618
619 v_interp_p2_f16 v5, -v2, attr0.x, v3
620 // NOSICI: error: invalid operand for instruction
621 // VI: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
622
623 v_interp_p2_f16 v5, v2, attr0.x, -v3
624 // NOSICI: error: invalid operand for instruction
625 // VI: v_interp_p2_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
626
627 v_interp_p2_f16 v5, |v2|, attr0.x, v3
628 // NOSICI: error: not a valid operand
629 // VI: v_interp_p2_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
630
631 v_interp_p2_f16 v5, v2, attr0.x, |v3|
632 // NOSICI: error: not a valid operand
633 // VI: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
634
635 v_interp_p2_f16 v5, v2, attr0.x, v3 high
636 // NOSICI: error: invalid operand for instruction
637 // VI: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
638
639 v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
640 // NOSICI: error: invalid operand for instruction
641 // VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
238238
239239 # VI: v_ceil_f32_e64 v0, neg(-1.0) ; encoding: [0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20]
240240 0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20
241
242 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
243 0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00
244
245 # VI: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
246 0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00
247
248 # VI: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
249 0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00
250
251 # VI: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
252 0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00
253
254 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
255 0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00
256
257 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
258 0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08
259
260 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
261 0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10
262
263 # VI: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
264 0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18
265
266 # VI: v_interp_p1_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
267 0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00
268
269 # VI: v_interp_p1_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00]
270 0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00
271
272 # VI: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
273 0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40
274
275 # VI: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
276 0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00
277
278 # VI: v_interp_p1_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00]
279 0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00
280
281 # VI: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
282 0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00
283
284 # VI: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
285 0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08
286
287 # VI: v_interp_p2_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
288 0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00
289
290 # VI: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
291 0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00
292
293 # VI: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
294 0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40
295
296 # VI: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
297 0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00
298
299 # VI: v_interp_p2_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00]
300 0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00
301
302 # VI: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
303 0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00
304
305 # VI: v_interp_p2_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10]
306 0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10
307
308 # VI: v_interp_p1ll_f16 v5, v2, attr0.x ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
309 0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00
310
311 # VI: v_interp_p1ll_f16 v5, v2, attr1.x ; encoding: [0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00]
312 0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00
313
314 # VI: v_interp_p1ll_f16 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
315 0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40
316
317 # VI: v_interp_p1ll_f16 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
318 0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00
319
320 # VI: v_interp_p1ll_f16 v5, v2, attr0.y ; encoding: [0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00]
321 0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00
322
323 # VI: v_interp_p1ll_f16 v5, v2, attr0.x high ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
324 0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00
325
326 # VI: v_interp_p1ll_f16 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
327 0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00
328
329 # VI: v_interp_p1ll_f16 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18]
330 0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18
331
332 # VI: v_interp_p1lv_f16 v255, v2, attr0.x, v3 ; encoding: [0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
333 0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04
334
335 # VI: v_interp_p1lv_f16 v5, v2, attr32.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04]
336 0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04
337
338 # VI: v_interp_p1lv_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
339 0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44
340
341 # VI: v_interp_p1lv_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
342 0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84
343
344 # VI: v_interp_p1lv_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
345 0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04
346
347 # VI: v_interp_p1lv_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
348 0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04
349
350 # VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
351 0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04
352
353 # VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
354 0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04
355
356 # VI: v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:4 ; encoding: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14]
357 0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14
358
359 # VI: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
360 0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04
361
362 # VI: v_interp_p2_f16 v5, v2, attr1.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
363 0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04
364
365 # VI: v_interp_p2_f16 v5, -v2, attr0.x, v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
366 0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44
367
368 # VI: v_interp_p2_f16 v5, v2, attr0.x, -v3 ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
369 0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84
370
371 # VI: v_interp_p2_f16 v5, |v2|, attr0.x, v3 ; encoding: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
372 0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04
373
374 # VI: v_interp_p2_f16 v5, v2, attr0.x, |v3| ; encoding: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
375 0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04
376
377 # VI: v_interp_p2_f16 v5, v2, attr0.x, v3 high ; encoding: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
378 0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04
379
380 # VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
381 0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04