llvm.org GIT mirror llvm / 96597a7
Add missing HWEncoding to base register class. This change gives tblgen the information needed to fill in the HexagonRegEncodingTable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217500 91177308-0d34-0410-b5e6-96231b3b80d8 Sid Manning 6 years ago
1 changed file(s) with 10 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
1212
1313 let Namespace = "Hexagon" in {
1414
15 class HexagonReg<string n> : Register {
15 class HexagonReg<bits<5> num, string n> : Register {
1616 field bits<5> Num;
17 let HWEncoding{4-0} = num;
1718 }
1819
19 class HexagonDoubleReg<string n, list subregs> :
20 class HexagonDoubleReg<bits<5> num, string n, list subregs> :
2021 RegisterWithSubRegs {
2122 field bits<5> Num;
23 let HWEncoding{4-0} = num;
2224 }
2325
2426 // Registers are identified with 5-bit ID numbers.
2527 // Ri - 32-bit integer registers.
26 class Ri num, string n> : HexagonReg> {
28 class Ri num, string n> : HexagonRegum, n> {
2729 let Num = num;
2830 }
2931
3032 // Rf - 32-bit floating-point registers.
31 class Rf num, string n> : HexagonReg> {
33 class Rf num, string n> : HexagonRegum, n> {
3234 let Num = num;
3335 }
3436
3537
3638 // Rd - 64-bit registers.
3739 class Rd num, string n, list subregs> :
38 HexagonDoubleReg, subregs> {
40 HexagonDoubleRegum, n, subregs> {
3941 let Num = num;
4042 let SubRegs = subregs;
4143 }
4244
4345 // Rp - predicate registers
44 class Rp num, string n> : HexagonReg> {
46 class Rp num, string n> : HexagonRegum, n> {
4547 let Num = num;
4648 }
4749
4850 // Rc - control registers
49 class Rc num, string n> : HexagonReg> {
51 class Rc num, string n> : HexagonRegum, n> {
5052 let Num = num;
5153 }
5254
5355 // Rj - aliased integer registers
54 class Rj: HexagonReg<n> {
56 class Rj: HexagonReg<R.Num, n> {
5557 let Num = R.Num;
5658 let Aliases = [R];
5759 }