llvm.org GIT mirror llvm / 9651b57
[GlobalISel][X86] Remove hand-written G_FADD/F_SUB selection. Now it handle by TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302793 91177308-0d34-0410-b5e6-96231b3b80d8 Igor Breger 3 years ago
1 changed file(s) with 0 addition(s) and 105 deletion(s). Raw diff Collapse all Expand all
5555 bool selectImpl(MachineInstr &I) const;
5656
5757 // TODO: remove after suported by Tablegen-erated instruction selection.
58 unsigned getFAddOp(LLT &Ty, const RegisterBank &RB) const;
59 unsigned getFSubOp(LLT &Ty, const RegisterBank &RB) const;
6058 unsigned getLoadStoreOp(LLT &Ty, const RegisterBank &RB, unsigned Opc,
6159 uint64_t Alignment) const;
6260
63 bool selectBinaryOp(MachineInstr &I, MachineRegisterInfo &MRI,
64 MachineFunction &MF) const;
6561 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
6662 MachineFunction &MF) const;
6763 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
234230 DEBUG(dbgs() << " C++ instruction selection: "; I.print(dbgs()));
235231
236232 // TODO: This should be implemented by tblgen.
237 if (selectBinaryOp(I, MRI, MF))
238 return true;
239233 if (selectLoadStoreOp(I, MRI, MF))
240234 return true;
241235 if (selectFrameIndexOrGep(I, MRI, MF))
250244 return true;
251245
252246 return false;
253 }
254
255 unsigned X86InstructionSelector::getFAddOp(LLT &Ty,
256 const RegisterBank &RB) const {
257
258 if (X86::VECRRegBankID != RB.getID())
259 return TargetOpcode::G_FADD;
260
261 if (Ty == LLT::scalar(32)) {
262 if (STI.hasAVX512()) {
263 return X86::VADDSSZrr;
264 } else if (STI.hasAVX()) {
265 return X86::VADDSSrr;
266 } else if (STI.hasSSE1()) {
267 return X86::ADDSSrr;
268 }
269 } else if (Ty == LLT::scalar(64)) {
270 if (STI.hasAVX512()) {
271 return X86::VADDSDZrr;
272 } else if (STI.hasAVX()) {
273 return X86::VADDSDrr;
274 } else if (STI.hasSSE2()) {
275 return X86::ADDSDrr;
276 }
277 } else if (Ty == LLT::vector(4, 32)) {
278 if ((STI.hasAVX512()) && (STI.hasVLX())) {
279 return X86::VADDPSZ128rr;
280 } else if (STI.hasAVX()) {
281 return X86::VADDPSrr;
282 } else if (STI.hasSSE1()) {
283 return X86::ADDPSrr;
284 }
285 }
286
287 return TargetOpcode::G_FADD;
288 }
289
290 unsigned X86InstructionSelector::getFSubOp(LLT &Ty,
291 const RegisterBank &RB) const {
292
293 if (X86::VECRRegBankID != RB.getID())
294 return TargetOpcode::G_FSUB;
295
296 if (Ty == LLT::scalar(32)) {
297 if (STI.hasAVX512()) {
298 return X86::VSUBSSZrr;
299 } else if (STI.hasAVX()) {
300 return X86::VSUBSSrr;
301 } else if (STI.hasSSE1()) {
302 return X86::SUBSSrr;
303 }
304 } else if (Ty == LLT::scalar(64)) {
305 if (STI.hasAVX512()) {
306 return X86::VSUBSDZrr;
307 } else if (STI.hasAVX()) {
308 return X86::VSUBSDrr;
309 } else if (STI.hasSSE2()) {
310 return X86::SUBSDrr;
311 }
312 } else if (Ty == LLT::vector(4, 32)) {
313 if ((STI.hasAVX512()) && (STI.hasVLX())) {
314 return X86::VSUBPSZ128rr;
315 } else if (STI.hasAVX()) {
316 return X86::VSUBPSrr;
317 } else if (STI.hasSSE1()) {
318 return X86::SUBPSrr;
319 }
320 }
321
322 return TargetOpcode::G_FSUB;
323 }
324
325 bool X86InstructionSelector::selectBinaryOp(MachineInstr &I,
326 MachineRegisterInfo &MRI,
327 MachineFunction &MF) const {
328
329 const unsigned DefReg = I.getOperand(0).getReg();
330 LLT Ty = MRI.getType(DefReg);
331 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
332
333 unsigned NewOpc = I.getOpcode();
334
335 switch (NewOpc) {
336 case TargetOpcode::G_FADD:
337 NewOpc = getFAddOp(Ty, RB);
338 break;
339 case TargetOpcode::G_FSUB:
340 NewOpc = getFSubOp(Ty, RB);
341 break;
342 default:
343 break;
344 }
345
346 if (NewOpc == I.getOpcode())
347 return false;
348
349 I.setDesc(TII.get(NewOpc));
350
351 return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
352247 }
353248
354249 unsigned X86InstructionSelector::getLoadStoreOp(LLT &Ty, const RegisterBank &RB,