llvm.org GIT mirror llvm / 96303e0
[ARM] Do not test for CPUs, use SubtargetFeatures (Part 3). NFCI This is a follow-up for r273544 and r273853. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also marks them as obsolete. Differential Revision: http://reviews.llvm.org/D21796 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274616 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 4 years ago
5 changed file(s) with 40 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
131131 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
132132 "true", "Prefer ISHST barriers">;
133133
134 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
135 def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true",
136 "Has muxed AGU and NEON/FPU">;
137
138 // On some targets, a VLDM/VSTM starting with an odd register number needs more
139 // microops than single VLDRS.
140 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
141 "true", "VLDM/VSTM starting with an odd register is slow">;
142
143 // Some targets have a renaming dependency when loading into D subregisters.
144 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
145 "SlowLoadDSubregister", "true",
146 "Loading into D subregs is slow">;
147
134148 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
135149 // VFP to NEON, as an execution domain optimization.
136150 def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",
577591 FeatureFP16,
578592 FeatureAvoidPartialCPSR,
579593 FeaturePreferVMOVSR,
594 FeatureMuxedUnits,
580595 FeatureNEONForFPMovs,
581596 FeatureCheckVLDnAlign,
582597 FeatureMP]>;
597612 // FIXME: A15 has currently the same Schedule model as A9.
598613 def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
599614 FeatureHasRetAddrStack,
615 FeatureMuxedUnits,
600616 FeatureTrustZone,
601617 FeatureT2XtPk,
602618 FeatureVFP4,
625641 // division features.
626642 def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
627643 FeatureHasRetAddrStack,
644 FeatureMuxedUnits,
628645 FeatureCheckVLDnAlign,
629646 FeatureVMLxForwarding,
630647 FeatureT2XtPk,
647664 FeatureHasSlowFPVMLx,
648665 FeatureProfUnpredicate,
649666 FeaturePrefISHSTBarrier,
667 FeatureSlowOddRegister,
668 FeatureSlowLoadDSubreg,
650669 FeatureSlowVGETLNi32,
651670 FeatureSlowVDUP32]>;
652671
4949
5050 // Skip over one non-VFP / NEON instruction.
5151 if (!LastMI->isBarrier() &&
52 // On A9, AGU and NEON/FPU are muxed.
53 !(TII.getSubtarget().isLikeA9() && LastMI->mayLoadOrStore()) &&
52 !(TII.getSubtarget().hasMuxedUnits() && LastMI->mayLoadOrStore()) &&
5453 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
5554 MachineBasicBlock::iterator I = LastMI;
5655 if (I != LastMI->getParent()->begin()) {
981981 bool CanMergeToLSMulti = true;
982982 // On swift vldm/vstm starting with an odd register number as that needs
983983 // more uops than single vldrs.
984 if (STI->isSwift() && !isNotVFP && (PRegNum % 2) == 1)
984 if (STI->hasSlowOddRegister() && !isNotVFP && (PRegNum % 2) == 1)
985985 CanMergeToLSMulti = false;
986986
987987 // LDRD/STRD do not allow SP/PC. LDM/STM do not support it or have it
248248 /// If true, ISHST barriers will be used for Release semantics.
249249 bool PreferISHST = false;
250250
251 /// If true, a VLDM/VSTM starting with an odd register number is considered to
252 /// take more microops than single VLDRS/VSTRS.
253 bool SlowOddRegister = false;
254
255 /// If true, loading into a D subregister will be penalized.
256 bool SlowLoadDSubregister = false;
257
258 /// If true, the AGU and NEON/FPU units are multiplexed.
259 bool HasMuxedUnits = false;
260
251261 /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
252262 bool UseNEONForFPMovs = false;
253263
381391 bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
382392 bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
383393
394 /// @{
395 /// These functions are obsolete, please consider adding subtarget features
396 /// or properties instead of calling them.
384397 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
385398 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
386399 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
391404 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
392405 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
393406 bool isKrait() const { return ARMProcFamily == Krait; }
407 /// @}
394408
395409 bool hasARMOps() const { return !NoARM; }
396410
430444 bool hasSlowVDUP32() const { return HasSlowVDUP32; }
431445 bool preferVMOVSR() const { return PreferVMOVSR; }
432446 bool preferISHSTBarriers() const { return PreferISHST; }
447 bool hasSlowOddRegister() const { return SlowOddRegister; }
448 bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
449 bool hasMuxedUnits() const { return HasMuxedUnits; }
433450 bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
434451 bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
435452 bool nonpipelinedVFP() const { return NonpipelinedVFP; }
258258 unsigned Index) {
259259 // Penalize inserting into an D-subregister. We end up with a three times
260260 // lower estimated throughput on swift.
261 if (ST->isSwift() &&
262 Opcode == Instruction::InsertElement &&
263 ValTy->isVectorTy() &&
264 ValTy->getScalarSizeInBits() <= 32)
261 if (ST->hasSlowLoadDSubregister() && Opcode == Instruction::InsertElement &&
262 ValTy->isVectorTy() && ValTy->getScalarSizeInBits() <= 32)
265263 return 3;
266264
267265 if ((Opcode == Instruction::InsertElement ||