llvm.org GIT mirror llvm / 95f1e2d
AVX doesn't support mm operations neither its instrinsics. The AVX versions of PALIGN and PABS* should only exist for 128-bit. Remove the unnecessary stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112944 91177308-0d34-0410-b5e6-96231b3b80d8 Bruno Cardoso Lopes 10 years ago
2 changed file(s) with 34 addition(s) and 58 deletion(s). Raw diff Collapse all Expand all
35313531 // SSSE3 - Packed Absolute Instructions
35323532 //===---------------------------------------------------------------------===//
35333533
3534 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3535 multiclass SS3I_unop_rm_int opc, string OpcodeStr,
3536 PatFrag mem_frag64, PatFrag mem_frag128,
3537 Intrinsic IntId64, Intrinsic IntId128> {
3534 /// SS3I_unop_rm_int_mm - Simple SSSE3 unary whose type can be v*{i8,i16,i32}.
3535 multiclass SS3I_unop_rm_int_mm opc, string OpcodeStr,
3536 PatFrag mem_frag64, Intrinsic IntId64> {
35383537 def rr64 : SS38I
35393538 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
35403539 [(set VR64:$dst, (IntId64 VR64:$src))]>;
35433542 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
35443543 [(set VR64:$dst,
35453544 (IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
3546
3545 }
3546
3547 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3548 multiclass SS3I_unop_rm_int opc, string OpcodeStr,
3549 PatFrag mem_frag128, Intrinsic IntId128> {
35473550 def rr128 : SS38I
35483551 (ins VR128:$src),
35493552 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
35593562 }
35603563
35613564 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3562 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
3563 int_x86_ssse3_pabs_b,
3565 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
35643566 int_x86_ssse3_pabs_b_128>, VEX;
3565 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
3566 int_x86_ssse3_pabs_w,
3567 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
35673568 int_x86_ssse3_pabs_w_128>, VEX;
3568 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
3569 int_x86_ssse3_pabs_d,
3569 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
35703570 int_x86_ssse3_pabs_d_128>, VEX;
35713571 }
35723572
3573 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
3574 int_x86_ssse3_pabs_b,
3575 int_x86_ssse3_pabs_b_128>;
3576 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv4i16, memopv8i16,
3577 int_x86_ssse3_pabs_w,
3578 int_x86_ssse3_pabs_w_128>;
3579 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32,
3580 int_x86_ssse3_pabs_d,
3581 int_x86_ssse3_pabs_d_128>;
3573 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3574 int_x86_ssse3_pabs_b_128>,
3575 SS3I_unop_rm_int_mm<0x1C, "pabsb", memopv8i8,
3576 int_x86_ssse3_pabs_b>;
3577
3578 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3579 int_x86_ssse3_pabs_w_128>,
3580 SS3I_unop_rm_int_mm<0x1D, "pabsw", memopv4i16,
3581 int_x86_ssse3_pabs_w>;
3582
3583 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3584 int_x86_ssse3_pabs_d_128>,
3585 SS3I_unop_rm_int_mm<0x1E, "pabsd", memopv2i32,
3586 int_x86_ssse3_pabs_d>;
35823587
35833588 //===---------------------------------------------------------------------===//
35843589 // SSSE3 - Packed Binary Operator Instructions
37153720 // SSSE3 - Packed Align Instruction Patterns
37163721 //===---------------------------------------------------------------------===//
37173722
3718 multiclass sse3_palign> {
3723 multiclass ssse3_palign_mm> {
37193724 def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
37203725 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
3721 !if(Is2Addr,
3722 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3723 !strconcat(asm,
3724 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3725 []>;
3726 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
37263727 def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
37273728 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
3728 !if(Is2Addr,
3729 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3730 !strconcat(asm,
3731 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3732 []>;
3733
3729 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
3730 }
3731
3732 multiclass ssse3_palign {
37343733 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
37353734 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
37363735 !if(Is2Addr,
37483747 }
37493748
37503749 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3751 defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
3750 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
37523751 let Constraints = "$src1 = $dst" in
3753 defm PALIGN : sse3_palign<"palignr">;
3752 defm PALIGN : ssse3_palign<"palignr">,
3753 ssse3_palign_mm<"palignr">;
37543754
37553755 let AddedComplexity = 5 in {
37563756
17141714 declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnone
17151715
17161716
1717 define <8 x i8> @test_x86_ssse3_pabs_b(<8 x i8> %a0) {
1718 ; CHECK: vpabsb
1719 %res = call <8 x i8> @llvm.x86.ssse3.pabs.b(<8 x i8> %a0) ; <<8 x i8>> [#uses=1]
1720 ret <8 x i8> %res
1721 }
1722 declare <8 x i8> @llvm.x86.ssse3.pabs.b(<8 x i8>) nounwind readnone
1723
1724
17251717 define <16 x i8> @test_x86_ssse3_pabs_b_128(<16 x i8> %a0) {
17261718 ; CHECK: vpabsb
17271719 %res = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0) ; <<16 x i8>> [#uses=1]
17301722 declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
17311723
17321724
1733 define <2 x i32> @test_x86_ssse3_pabs_d(<2 x i32> %a0) {
1734 ; CHECK: vpabsd
1735 %res = call <2 x i32> @llvm.x86.ssse3.pabs.d(<2 x i32> %a0) ; <<2 x i32>> [#uses=1]
1736 ret <2 x i32> %res
1737 }
1738 declare <2 x i32> @llvm.x86.ssse3.pabs.d(<2 x i32>) nounwind readnone
1739
1740
17411725 define <4 x i32> @test_x86_ssse3_pabs_d_128(<4 x i32> %a0) {
17421726 ; CHECK: vpabsd
17431727 %res = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0) ; <<4 x i32>> [#uses=1]
17441728 ret <4 x i32> %res
17451729 }
17461730 declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
1747
1748
1749 define <4 x i16> @test_x86_ssse3_pabs_w(<4 x i16> %a0) {
1750 ; CHECK: vpabsw
1751 %res = call <4 x i16> @llvm.x86.ssse3.pabs.w(<4 x i16> %a0) ; <<4 x i16>> [#uses=1]
1752 ret <4 x i16> %res
1753 }
1754 declare <4 x i16> @llvm.x86.ssse3.pabs.w(<4 x i16>) nounwind readnone
17551731
17561732
17571733 define <8 x i16> @test_x86_ssse3_pabs_w_128(<8 x i16> %a0) {