llvm.org GIT mirror llvm / 951c9d9
CodeGen: Refactor regallocator command line and target selection This will allow targets more flexibility to replace the register allocator core passes. In a future commit, AMDGPU will run the core register assignment passes twice, and will also want to disallow using the standard -regalloc option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356506 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 1 year, 8 months ago
5 changed file(s) with 72 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
359359
360360 /// addFastRegAlloc - Add the minimum set of target-independent passes that
361361 /// are required for fast register allocation.
362 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
362 virtual void addFastRegAlloc();
363363
364364 /// addOptimizedRegAlloc - Add passes related to register allocation.
365365 /// LLVMTargetMachine provides standard regalloc passes for most targets.
366 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
366 virtual void addOptimizedRegAlloc();
367367
368368 /// addPreRewrite - Add passes to the optimized register allocation pipeline
369369 /// after register allocation is complete, but before virtual registers are
373373 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
374374 /// When these passes run, VirtRegMap contains legal physreg assignments for
375375 /// all virtual registers.
376 ///
377 /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
378 /// be honored. This is also not generally used for the the fast variant,
379 /// where the allocation and rewriting are done in one pass.
376380 virtual bool addPreRewrite() {
377381 return false;
378382 }
430434
431435 /// addMachinePasses helper to create the target-selected or overriden
432436 /// regalloc pass.
433 FunctionPass *createRegAllocPass(bool Optimized);
437 virtual FunctionPass *createRegAllocPass(bool Optimized);
438
439 /// Add core register alloator passes which do the actual register assignment
440 /// and rewriting. \returns true if any passes were added.
441 virtual bool addRegAssignmentFast();
442 virtual bool addRegAssignmentOptimized();
434443 };
435444
436445 } // end namespace llvm
896896 // Run register allocation and passes that are tightly coupled with it,
897897 // including phi elimination and scheduling.
898898 if (getOptimizeRegAlloc())
899 addOptimizedRegAlloc(createRegAllocPass(true));
900 else {
901 if (RegAlloc != &useDefaultRegisterAllocator &&
902 RegAlloc != &createFastRegisterAllocator)
903 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
904 addFastRegAlloc(createRegAllocPass(false));
905 }
899 addOptimizedRegAlloc();
900 else
901 addFastRegAlloc();
906902
907903 // Run post-ra passes.
908904 addPostRegAlloc();
10921088 return createTargetRegisterAllocator(Optimized);
10931089 }
10941090
1091 bool TargetPassConfig::addRegAssignmentFast() {
1092 if (RegAlloc != &useDefaultRegisterAllocator &&
1093 RegAlloc != &createFastRegisterAllocator)
1094 report_fatal_error("Must use fast (default) register allocator for unoptimized regalloc.");
1095
1096 addPass(createRegAllocPass(false));
1097 return true;
1098 }
1099
1100 bool TargetPassConfig::addRegAssignmentOptimized() {
1101 // Add the selected register allocation pass.
1102 addPass(createRegAllocPass(true));
1103
1104 // Allow targets to change the register assignments before rewriting.
1105 addPreRewrite();
1106
1107 // Finally rewrite virtual registers.
1108 addPass(&VirtRegRewriterID);
1109 // Perform stack slot coloring and post-ra machine LICM.
1110 //
1111 // FIXME: Re-enable coloring with register when it's capable of adding
1112 // kill markers.
1113 addPass(&StackSlotColoringID);
1114
1115 return true;
1116 }
1117
10951118 /// Return true if the default global register allocator is in use and
10961119 /// has not be overriden on the command line with '-regalloc=...'
10971120 bool TargetPassConfig::usingDefaultRegAlloc() const {
11001123
11011124 /// Add the minimum set of target-independent passes that are required for
11021125 /// register allocation. No coalescing or scheduling.
1103 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
1126 void TargetPassConfig::addFastRegAlloc() {
11041127 addPass(&PHIEliminationID, false);
11051128 addPass(&TwoAddressInstructionPassID, false);
11061129
1107 if (RegAllocPass)
1108 addPass(RegAllocPass);
1130 addRegAssignmentFast();
11091131 }
11101132
11111133 /// Add standard target-independent passes that are tightly coupled with
11121134 /// optimized register allocation, including coalescing, machine instruction
11131135 /// scheduling, and register allocation itself.
1114 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
1136 void TargetPassConfig::addOptimizedRegAlloc() {
11151137 addPass(&DetectDeadLanesID, false);
11161138
11171139 addPass(&ProcessImplicitDefsID, false);
11431165 // PreRA instruction scheduling.
11441166 addPass(&MachineSchedulerID);
11451167
1146 if (RegAllocPass) {
1147 // Add the selected register allocation pass.
1148 addPass(RegAllocPass);
1149
1150 // Allow targets to change the register assignments before rewriting.
1151 addPreRewrite();
1152
1153 // Finally rewrite virtual registers.
1154 addPass(&VirtRegRewriterID);
1155
1156 // Perform stack slot coloring and post-ra machine LICM.
1157 //
1158 // FIXME: Re-enable coloring with register when it's capable of adding
1159 // kill markers.
1160 addPass(&StackSlotColoringID);
1161
1168 if (addRegAssignmentOptimized()) {
11621169 // Copy propagate to forward register uses and try to eliminate COPYs that
11631170 // were not coalesced.
11641171 addPass(&MachineCopyPropagationID);
578578 bool addLegalizeMachineIR() override;
579579 bool addRegBankSelect() override;
580580 bool addGlobalInstructionSelect() override;
581 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
582 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
581 void addFastRegAlloc() override;
582 void addOptimizedRegAlloc() override;
583583 void addPreRegAlloc() override;
584584 void addPostRegAlloc() override;
585585 void addPreSched2() override;
864864 addPass(createSIWholeQuadModePass());
865865 }
866866
867 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
867 void GCNPassConfig::addFastRegAlloc() {
868868 // FIXME: We have to disable the verifier here because of PHIElimination +
869869 // TwoAddressInstructions disabling it.
870870
877877 // machine-level CFG, but before register allocation.
878878 insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
879879
880 TargetPassConfig::addFastRegAlloc(RegAllocPass);
881 }
882
883 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
880 TargetPassConfig::addFastRegAlloc();
881 }
882
883 void GCNPassConfig::addOptimizedRegAlloc() {
884884 insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
885885
886886 insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
894894 // machine-level CFG, but before register allocation.
895895 insertPass(&SILowerControlFlowID, &SIFixWWMLivenessID, false);
896896
897 TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
897 TargetPassConfig::addOptimizedRegAlloc();
898898 }
899899
900900 void GCNPassConfig::addPostRegAlloc() {
165165 void addMachineSSAOptimization() override;
166166
167167 FunctionPass *createTargetRegisterAllocator(bool) override;
168 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
169 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
168 void addFastRegAlloc() override;
169 void addOptimizedRegAlloc() override;
170
171 bool addRegAssignmentFast() override {
172 llvm_unreachable("should not be used");
173 }
174
175 bool addRegAssignmentOptimized() override {
176 llvm_unreachable("should not be used");
177 }
170178
171179 private:
172180 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
321329 return nullptr; // No reg alloc
322330 }
323331
324 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
325 assert(!RegAllocPass && "NVPTX uses no regalloc!");
332 void NVPTXPassConfig::addFastRegAlloc() {
326333 addPass(&PHIEliminationID);
327334 addPass(&TwoAddressInstructionPassID);
328335 }
329336
330 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
331 assert(!RegAllocPass && "NVPTX uses no regalloc!");
332
337 void NVPTXPassConfig::addOptimizedRegAlloc() {
333338 addPass(&ProcessImplicitDefsID);
334339 addPass(&LiveVariablesID);
335340 addPass(&MachineLoopInfoID);
190190 void addPostRegAlloc() override;
191191 bool addGCPasses() override { return false; }
192192 void addPreEmitPass() override;
193
194 // No reg alloc
195 bool addRegAssignmentFast() override { return false; }
196
197 // No reg alloc
198 bool addRegAssignmentOptimized() override { return false; }
193199 };
194200 } // end anonymous namespace
195201