llvm.org GIT mirror llvm / 950d3db
Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get created from the", it broke some GCC test suite tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Dunbar 8 years ago
16 changed file(s) with 17 addition(s) and 31 deletion(s). Raw diff Collapse all Expand all
5757 STATISTIC(NumExtsMoved, "Number of [s|z]ext instructions combined with loads");
5858 STATISTIC(NumExtUses, "Number of uses of [s|z]ext instructions optimized");
5959
60 static cl::opt DisableBranchOpts(
61 "disable-cgp-branch-opts", cl::Hidden, cl::init(false),
62 cl::desc("Disable branch optimizations in CodeGenPrepare"));
63
6460 namespace {
6561 class CodeGenPrepare : public FunctionPass {
6662 /// TLI - Keep a pointer of a TargetLowering to consult for determining
132128 }
133129
134130 SunkAddrs.clear();
135
136 if (!DisableBranchOpts) {
137 MadeChange = false;
138 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
139 MadeChange |= ConstantFoldTerminator(BB);
140
141 if (MadeChange && DT)
142 DT->DT->recalculate(F);
143 EverMadeChange |= MadeChange;
144 }
145131
146132 return EverMadeChange;
147133 }
None ; RUN: llc < %s -march=arm -disable-cgp-branch-opts | FileCheck %s
0 ; RUN: llc < %s -march=arm | FileCheck %s
11
22 define i32 @f1() {
33 ; CHECK: f1
None ;RUN: llc --march=cellspu -disable-cgp-branch-opts %s -o - | FileCheck %s
0 ;RUN: llc --march=cellspu %s -o - | FileCheck %s
11 ; This is to check that emitting jumptables doesn't crash llc
22 define i32 @test(i32 %param) {
33 entry:
None ; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts | FileCheck %s
0 ; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
11
22 %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
33 %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
77 ; CHECK: sub sp, #8
88 ; CHECK: push
99 ; CHECK: add r7, sp, #4
10 ; CHECK: sub.w r4, r7, #4
10 ; CHECK: subs r4, r7, #4
1111 ; CHECK: mov sp, r4
1212 ; CHECK-NOT: mov sp, r7
1313 ; CHECK: add sp, #8
None ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-cgp-branch-opts | FileCheck %s
0 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s
11
22 %struct.pix_pos = type { i32, i32, i32, i32, i32, i32 }
33
77 define void @foo() nounwind optsize {
88 ; CHECK: foo:
99 ; CHECK: push
10 ; CHECK: mov r7, sp
10 ; CHECK: add r7, sp, #4
1111 ; CHECK: sub sp, #4
1212 entry:
1313 %m.i = alloca %struct.buf*, align 4
55 br label %bb5
66
77 bb5: ; preds = %bb5, %entry
8 ; CHECK: %bb5
9 ; CHECK: bne
810 br i1 undef, label %bb5, label %bb.nph
911
1012 bb.nph: ; preds = %bb5
None ; RUN: llc < %s -mtriple=i386-apple-darwin -disable-cgp-branch-opts | grep movw | not grep {, %e}
0 ; RUN: llc < %s -mtriple=i386-apple-darwin | grep movw | not grep {, %e}
11
22 %struct.DBC_t = type { i32, i8*, i16, %struct.DBC_t*, i8*, i8*, i8*, i8*, i8*, %struct.DBC_t*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i32*, i8, i16, %struct.DRVOPT*, i16 }
33 %struct.DRVOPT = type { i16, i32, i8, %struct.DRVOPT* }
None ; RUN: llc < %s -mtriple=x86_64-appel-darwin -disable-cgp-branch-opts -stats |& grep {machine-sink}
0 ; RUN: llc < %s -mtriple=x86_64-appel-darwin -stats |& grep {machine-sink}
11
22 define fastcc void @t() nounwind ssp {
33 entry:
None ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X64
1 ; RUN: llc < %s -mtriple=i386-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X32
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s -check-prefix=X64
1 ; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s -check-prefix=X32
22 ; PR1632
33
44 define void @_Z1fv() {
None ; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | grep movzbl
0 ; RUN: llc < %s -march=x86 | grep movzbl
11 ; PR3366
22
33 define void @_ada_c34002a() nounwind {
None ; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | FileCheck %s -check-prefix=32
1 ; RUN: llc < %s -march=x86-64 -disable-cgp-branch-opts | FileCheck %s -check-prefix=64
0 ; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=32
1 ; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=64
22 ; rdar://7573216
33 ; PR6146
44
1212 ; CHECK: %if.end
1313 ; CHECK: movl (%{{.*}}), [[REG:%[a-z]+]]
1414 ; CHECK-NOT: movl [[REG]], [[REG]]
15 ; CHECK-NEXT: testl [[REG]], [[REG]]
1615 ; CHECK-NEXT: xorb
1716 %tmp138 = select i1 undef, i32 0, i32 %tmp7.i
1817 %tmp867 = zext i32 %tmp138 to i64
None ;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding -disable-cgp-branch-opts < %s | FileCheck %s
0 ;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s
11
22
33 ;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
1313 br i1 %1, label %T, label %trap
1414
1515 ; CHECK: entry:
16 ; CHECK-NEXT: br label %T
16 ; HECK-NEXT: ret i32 4
1717
1818 trap: ; preds = %0, %entry
1919 tail call void @llvm.trap() noreturn nounwind
2020 unreachable
2121
2222 T:
23 ; CHECK: ret i32 4
2423 ret i32 4
2524 }
2625