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Merging r268295: ------------------------------------------------------------------------ r268295 | thomas.stellard | 2016-05-02 13:11:44 -0700 (Mon, 02 May 2016) | 7 lines AMDGPU/SI: Use v_readfirstlane_b32 when restoring SGPRs spilled to scratch We were using v_readlane_b32 with the lane set to zero, but this won't work if thread 0 is not active. Differential Revision: http://reviews.llvm.org/D19745 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271771 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
2 changed file(s) with 7 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
409409 .addImm(i * 4) // offset
410410 .addMemOperand(MMO);
411411 BuildMI(*MBB, MI, DL,
412 TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg)
412 TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
413413 .addReg(TmpReg, RegState::Kill)
414 .addImm(0)
415414 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
416415 }
417416 }
11
22 ; Make sure this doesn't crash.
33 ; CHECK: {{^}}test:
4 ; Make sure we are handling hazards correctly.
5 ; CHECK: buffer_load_dword [[VHI:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:16
6 ; CHECK-NEXT: s_waitcnt vmcnt(0)
7 ; CHECK-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]]
8 ; CHECK-NEXT: s_nop 4
9 ; CHECK-NEXT: buffer_store_dword v0, s[0:[[HI]]{{\]}}, 0
410 ; CHECK: s_endpgm
511 define void @test(i32 addrspace(1)* %out, i32 %in) {
612 call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" ()