llvm.org GIT mirror llvm / 946f077
[X86] Don't break CMOV pseudo instructions down by type. Just by register class. The register class is all that's important for the pseudo instructions. We can use patterns to handle the different types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343709 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 1 year, 9 months ago
2 changed file(s) with 36 addition(s) and 41 deletion(s). Raw diff Collapse all Expand all
2746227462 case X86::CMOV_RFP32:
2746327463 case X86::CMOV_RFP64:
2746427464 case X86::CMOV_RFP80:
27465 case X86::CMOV_V2F64:
27466 case X86::CMOV_V2I64:
27467 case X86::CMOV_V4F32:
27468 case X86::CMOV_V4F64:
27469 case X86::CMOV_V4I64:
27470 case X86::CMOV_V16F32:
27471 case X86::CMOV_V8F32:
27472 case X86::CMOV_V8F64:
27473 case X86::CMOV_V8I64:
27474 case X86::CMOV_V8I1:
27475 case X86::CMOV_V16I1:
27476 case X86::CMOV_V32I1:
27477 case X86::CMOV_V64I1:
27465 case X86::CMOV_VR128:
27466 case X86::CMOV_VR256:
27467 case X86::CMOV_VR512:
27468 case X86::CMOV_VK8:
27469 case X86::CMOV_VK16:
27470 case X86::CMOV_VK32:
27471 case X86::CMOV_VK64:
2747827472 return true;
2747927473
2748027474 default:
2905829052 return EmitLoweredTLSCall(MI, BB);
2905929053 case X86::CMOV_FR32:
2906029054 case X86::CMOV_FR64:
29061 case X86::CMOV_F128:
2906229055 case X86::CMOV_GR8:
2906329056 case X86::CMOV_GR16:
2906429057 case X86::CMOV_GR32:
2906529058 case X86::CMOV_RFP32:
2906629059 case X86::CMOV_RFP64:
2906729060 case X86::CMOV_RFP80:
29068 case X86::CMOV_V2F64:
29069 case X86::CMOV_V2I64:
29070 case X86::CMOV_V4F32:
29071 case X86::CMOV_V4F64:
29072 case X86::CMOV_V4I64:
29073 case X86::CMOV_V16F32:
29074 case X86::CMOV_V8F32:
29075 case X86::CMOV_V8F64:
29076 case X86::CMOV_V8I64:
29077 case X86::CMOV_V8I1:
29078 case X86::CMOV_V16I1:
29079 case X86::CMOV_V32I1:
29080 case X86::CMOV_V64I1:
29061 case X86::CMOV_VR128:
29062 case X86::CMOV_VR256:
29063 case X86::CMOV_VR512:
29064 case X86::CMOV_VK8:
29065 case X86::CMOV_VK16:
29066 case X86::CMOV_VK32:
29067 case X86::CMOV_VK64:
2908129068 return EmitLoweredSelect(MI, BB);
2908229069
2908329070 case X86::RDFLAGS32:
589589
590590 defm _FR32 : CMOVrr_PSEUDO;
591591 defm _FR64 : CMOVrr_PSEUDO;
592 defm _F128 : CMOVrr_PSEUDO;
593 defm _V4F32 : CMOVrr_PSEUDO;
594 defm _V2F64 : CMOVrr_PSEUDO;
595 defm _V2I64 : CMOVrr_PSEUDO;
596 defm _V8F32 : CMOVrr_PSEUDO;
597 defm _V4F64 : CMOVrr_PSEUDO;
598 defm _V4I64 : CMOVrr_PSEUDO;
599 defm _V8I64 : CMOVrr_PSEUDO;
600 defm _V8F64 : CMOVrr_PSEUDO;
601 defm _V16F32 : CMOVrr_PSEUDO;
602 defm _V8I1 : CMOVrr_PSEUDO;
603 defm _V16I1 : CMOVrr_PSEUDO;
604 defm _V32I1 : CMOVrr_PSEUDO;
605 defm _V64I1 : CMOVrr_PSEUDO>;
592 defm _VR128 : CMOVrr_PSEUDO>;
593 defm _VR256 : CMOVrr_PSEUDO;
594 defm _VR512 : CMOVrr_PSEUDO;
595 defm _VK8 : CMOVrr_PSEUDO;
596 defm _VK16 : CMOVrr_PSEUDO;
597 defm _VK32 : CMOVrr_PSEUDO;
598 defm _VK64 : CMOVrr_PSEUDO;
606599 } // usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS]
600
601 def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
602 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
603 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
604 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
605 def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
606 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
607 def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
608 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
609 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
610 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
611 def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),
612 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>;
613 def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),
614 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>;
607615
608616 //===----------------------------------------------------------------------===//
609617 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions