llvm.org GIT mirror llvm / 943dd9a
[ARM] Clean up choice of narrow instructions in ARMAsmParser, NFC This patch makes a couple of changes to how we decide whether to use the narrow or wide encoding of thumb2 instructions: * Common out the detection of the .w qualifier * Check for the CPSR operand in a consistent way Differential Revision: https://reviews.llvm.org/D34460 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305992 91177308-0d34-0410-b5e6-96231b3b80d8 John Brawn 3 years ago
1 changed file(s) with 27 addition(s) and 33 deletion(s). Raw diff Collapse all Expand all
68596859 bool ARMAsmParser::processInstruction(MCInst &Inst,
68606860 const OperandVector &Operands,
68616861 MCStreamer &Out) {
6862 // Check if we have the wide qualifier, because if it's present we
6863 // must avoid selecting a 16-bit thumb instruction.
6864 bool HasWideQualifier = false;
6865 for (auto &Op : Operands) {
6866 ARMOperand &ARMOp = static_cast(*Op);
6867 if (ARMOp.isToken() && ARMOp.getToken() == ".w") {
6868 HasWideQualifier = true;
6869 break;
6870 }
6871 }
6872
68626873 switch (Inst.getOpcode()) {
68636874 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
68646875 case ARM::LDRT_POST:
69386949 // Select the narrow version if the immediate will fit.
69396950 if (Inst.getOperand(1).getImm() > 0 &&
69406951 Inst.getOperand(1).getImm() <= 0xff &&
6941 !(static_cast(*Operands[2]).isToken() &&
6942 static_cast(*Operands[2]).getToken() == ".w"))
6952 !HasWideQualifier)
69436953 Inst.setOpcode(ARM::tLDRpci);
69446954 else
69456955 Inst.setOpcode(ARM::t2LDRpci);
69706980 else if (Inst.getOpcode() == ARM::t2LDRConstPool)
69716981 TmpInst.setOpcode(ARM::t2LDRpci);
69726982 const ARMOperand &PoolOperand =
6973 (static_cast(*Operands[2]).isToken() &&
6974 static_cast(*Operands[2]).getToken() == ".w") ?
6975 static_cast(*Operands[4]) :
6976 static_cast(*Operands[3]);
6983 (HasWideQualifier ?
6984 static_cast(*Operands[4]) :
6985 static_cast(*Operands[3]));
69776986 const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
69786987 // If SubExprVal is a constant we may be able to use a MOV
69796988 if (isa(SubExprVal) &&
81168125 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
81178126 isARMLowRegister(Inst.getOperand(1).getReg()) &&
81188127 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8119 !(static_cast(*Operands[3]).isToken() &&
8120 static_cast(*Operands[3]).getToken() == ".w")) {
8128 !HasWideQualifier) {
81218129 unsigned NewOpc;
81228130 switch (Inst.getOpcode()) {
81238131 default: llvm_unreachable("unexpected opcode");
84148422 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
84158423 (Inst.getOperand(2).isImm() &&
84168424 (unsigned)Inst.getOperand(2).getImm() > 255) ||
8417 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8418 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8419 (static_cast(*Operands[3]).isToken() &&
8420 static_cast(*Operands[3]).getToken() == ".w"))
8425 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
8426 HasWideQualifier)
84218427 break;
84228428 MCInst TmpInst;
84238429 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
84468452 }
84478453 if (!Transform ||
84488454 Inst.getOperand(5).getReg() != 0 ||
8449 (static_cast(*Operands[3]).isToken() &&
8450 static_cast(*Operands[3]).getToken() == ".w"))
8455 HasWideQualifier)
84518456 break;
84528457 MCInst TmpInst;
84538458 TmpInst.setOpcode(ARM::tADDhirr);
85678572 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
85688573 (Inst.getOperand(1).isImm() &&
85698574 (unsigned)Inst.getOperand(1).getImm() <= 255) &&
8570 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8571 Inst.getOperand(4).getReg() == ARM::CPSR) ||
8572 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8573 (!static_cast(*Operands[2]).isToken() ||
8574 static_cast(*Operands[2]).getToken() != ".w")) {
8575 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8576 !HasWideQualifier) {
85758577 // The operands aren't in the same order for tMOVi8...
85768578 MCInst TmpInst;
85778579 TmpInst.setOpcode(ARM::tMOVi8);
85928594 isARMLowRegister(Inst.getOperand(1).getReg()) &&
85938595 Inst.getOperand(2).getImm() == ARMCC::AL &&
85948596 Inst.getOperand(4).getReg() == ARM::CPSR &&
8595 (!static_cast(*Operands[2]).isToken() ||
8596 static_cast(*Operands[2]).getToken() != ".w")) {
8597 !HasWideQualifier) {
85978598 // The operands aren't the same for tMOV[S]r... (no cc_out)
85988599 MCInst TmpInst;
85998600 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
86158616 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
86168617 isARMLowRegister(Inst.getOperand(1).getReg()) &&
86178618 Inst.getOperand(2).getImm() == 0 &&
8618 (!static_cast(*Operands[2]).isToken() ||
8619 static_cast(*Operands[2]).getToken() != ".w")) {
8619 !HasWideQualifier) {
86208620 unsigned NewOpc;
86218621 switch (Inst.getOpcode()) {
86228622 default: llvm_unreachable("Illegal opcode!");
87158715 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
87168716 isARMLowRegister(Inst.getOperand(2).getReg())) &&
87178717 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8718 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8719 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8720 (!static_cast(*Operands[3]).isToken() ||
8721 !static_cast(*Operands[3]).getToken().equals_lower(
8722 ".w"))) {
8718 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8719 !HasWideQualifier) {
87238720 unsigned NewOpc;
87248721 switch (Inst.getOpcode()) {
87258722 default: llvm_unreachable("unexpected opcode");
87558752 isARMLowRegister(Inst.getOperand(2).getReg())) &&
87568753 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
87578754 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8758 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8759 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8760 (!static_cast(*Operands[3]).isToken() ||
8761 !static_cast(*Operands[3]).getToken().equals_lower(
8762 ".w"))) {
8755 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8756 !HasWideQualifier) {
87638757 unsigned NewOpc;
87648758 switch (Inst.getOpcode()) {
87658759 default: llvm_unreachable("unexpected opcode");