llvm.org GIT mirror llvm / 9420201
Fix live variables issues: 1. If part of a register is re-defined, an implicit kill and an implicit def are added to denote read / mod / write. However, this should only be necessary if the register is actually read later. This is a performance issue. 2. If a sub-register is being defined, and it doesn't have a previous use, do not add a implicit kill to the last use of a super-register: = EAX, AX<imp-use,kill> ... AX = In this case, EAX is live but AX is killed, this is wrong and will cause the coalescer to do bad things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48521 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
4 changed file(s) with 63 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
164164 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
165165 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
166166
167 /// hasRegisterUseBelow - Return true if the specified register is used after
168 /// the current instruction and before it's next definition.
169 bool hasRegisterUseBelow(unsigned Reg,
170 MachineBasicBlock::iterator I,
171 MachineBasicBlock *MBB);
172
167173 /// analyzePHINodes - Gather information about the PHI nodes in here. In
168174 /// particular, we want to map the variable information of a virtual
169175 /// register which is used in a PHI node. We map that to the BB the vreg
266266
267267 if (*SubRegs == 0) {
268268 // No sub-registers, just check if reg is killed by RefMI.
269 if (PhysRegInfo[Reg] == RefMI)
269 if (PhysRegInfo[Reg] == RefMI && PhysRegInfo[Reg]->readsRegister(Reg)) {
270270 return true;
271 }
271272 } else if (SubKills.empty()) {
272273 // None of the sub-registers are killed elsewhere.
273274 return true;
293294 unsigned SubReg = *SubRegs; ++SubRegs)
294295 addRegisterKills(SubReg, RefMI, SubKills);
295296
297 return false;
298 }
299
300 /// hasRegisterUseBelow - Return true if the specified register is used after
301 /// the current instruction and before it's next definition.
302 bool LiveVariables::hasRegisterUseBelow(unsigned Reg,
303 MachineBasicBlock::iterator I,
304 MachineBasicBlock *MBB) {
305 if (I == MBB->end())
306 return false;
307 ++I;
308 // FIXME: This is slow. We probably need a smarter solution. Possibilities:
309 // 1. Scan all instructions once and build def / use information of physical
310 // registers. We also need a fast way to compare relative ordering of
311 // instructions.
312 // 2. Cache information so this function only has to scan instructions that
313 // read / def physical instructions.
314 for (MachineBasicBlock::iterator E = MBB->end(); I != E; ++I) {
315 MachineInstr *MI = I;
316 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
317 const MachineOperand &MO = MI->getOperand(i);
318 if (!MO.isRegister() || MO.getReg() != Reg)
319 continue;
320 if (MO.isDef())
321 return false;
322 return true;
323 }
324 }
296325 return false;
297326 }
298327
337366 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
338367 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
339368 // The larger register is previously defined. Now a smaller part is
340 // being re-defined. Treat it as read/mod/write.
369 // being re-defined. Treat it as read/mod/write if there are uses
370 // below.
341371 // EAX =
342372 // AX = EAX, EAX
343 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
373 // ...
374 /// = EAX
375 if (MI && hasRegisterUseBelow(SuperReg, MI, MI->getParent())) {
376 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
344377 true/*IsImp*/,true/*IsKill*/));
345 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
346 true/*IsImp*/));
347 PhysRegInfo[SuperReg] = MI;
378 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
379 true/*IsImp*/));
380 PhysRegInfo[SuperReg] = MI;
381 } else {
382 PhysRegInfo[SuperReg]->addRegisterKilled(SuperReg, TRI, true);
383 PhysRegInfo[SuperReg] = NULL;
384 }
348385 PhysRegUsed[SuperReg] = false;
349386 PhysRegPartUse[SuperReg] = NULL;
350387 } else {
0 ; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc64-regscavenger
1
2 define i16 @test(i8* %d1, i16* %d2) {
3 %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 )
4 ret i16 %tmp237
5 }
0 ; RUN: llvm-as < %s | llc -march=x86-64 | grep mov | count 1
1
2 define i32 @f() nounwind {
3 tail call void @t( i32 1 ) nounwind
4 ret i32 0
5 }
6
7 declare void @t(i32)