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Merging r230235: ------------------------------------------------------------------------ r230235 | dsanders | 2015-02-23 17:22:16 +0000 (Mon, 23 Feb 2015) | 16 lines [mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled. Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@231472 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 5 years ago
3 changed file(s) with 151 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
368368 (sequence "W%u", 0, 31)>;
369369 def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
370370 (sequence "W%u", 0, 31)>;
371 def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128,
372 (decimate (sequence "W%u", 0, 31), 2)>;
371373
372374 def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
373375 MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>;
28812881 unsigned Ws = MI->getOperand(1).getReg();
28822882 unsigned Lane = MI->getOperand(2).getImm();
28832883
2884 if (Lane == 0)
2885 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
2886 else {
2887 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2884 if (Lane == 0) {
2885 unsigned Wt = Ws;
2886 if (!Subtarget.useOddSPReg()) {
2887 // We must copy to an even-numbered MSA register so that the
2888 // single-precision sub-register is also guaranteed to be even-numbered.
2889 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
2890
2891 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
2892 }
2893
2894 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
2895 } else {
2896 unsigned Wt = RegInfo.createVirtualRegister(
2897 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
2898 &Mips::MSA128WEvensRegClass);
28882899
28892900 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
28902901 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
29442955 unsigned Wd_in = MI->getOperand(1).getReg();
29452956 unsigned Lane = MI->getOperand(2).getImm();
29462957 unsigned Fs = MI->getOperand(3).getReg();
2947 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
2958 unsigned Wt = RegInfo.createVirtualRegister(
2959 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
2960 &Mips::MSA128WEvensRegClass);
29482961
29492962 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
29502963 .addImm(0)
0 ; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,-nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG
1 ; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOODDSPREG
2
3 @v4f32 = global <4 x float> zeroinitializer
4
5 define void @msa_insert_0(float %a) {
6 entry:
7 ; Force the float into an odd-numbered register using named registers and
8 ; load the vector.
9 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
10 %0 = load volatile <4 x float>* @v4f32
11
12 ; Clobber all except $f12/$w12 and $f13
13 ;
14 ; The intention is that if odd single precision registers are permitted, the
15 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
16 ; avoid the spill/reload.
17 ;
18 ; On the other hand, if odd single precision registers are not permitted, it
19 ; must copy $f13 to an even-numbered register before inserting into the
20 ; vector.
21 call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
22 %1 = insertelement <4 x float> %0, float %b, i32 0
23 store <4 x float> %1, <4 x float>* @v4f32
24 ret void
25 }
26
27 ; ALL-LABEL: msa_insert_0:
28 ; ALL: mov.s $f13, $f12
29 ; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
30 ; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
31 ; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
32 ; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0]
33 ; ODDSPREG: insve.w $w[[W0]][0], $w13[0]
34 ; ALL: # Clobber
35 ; ALL-NOT: sdc1
36 ; ALL-NOT: ldc1
37 ; ALL: st.w $w[[W0]], 0($[[R0]])
38
39 define void @msa_insert_1(float %a) {
40 entry:
41 ; Force the float into an odd-numbered register using named registers and
42 ; load the vector.
43 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
44 %0 = load volatile <4 x float>* @v4f32
45
46 ; Clobber all except $f12/$w12 and $f13
47 ;
48 ; The intention is that if odd single precision registers are permitted, the
49 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
50 ; avoid the spill/reload.
51 ;
52 ; On the other hand, if odd single precision registers are not permitted, it
53 ; must copy $f13 to an even-numbered register before inserting into the
54 ; vector.
55 call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
56 %1 = insertelement <4 x float> %0, float %b, i32 1
57 store <4 x float> %1, <4 x float>* @v4f32
58 ret void
59 }
60
61 ; ALL-LABEL: msa_insert_1:
62 ; ALL: mov.s $f13, $f12
63 ; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
64 ; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
65 ; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
66 ; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0]
67 ; ODDSPREG: insve.w $w[[W0]][1], $w13[0]
68 ; ALL: # Clobber
69 ; ALL-NOT: sdc1
70 ; ALL-NOT: ldc1
71 ; ALL: st.w $w[[W0]], 0($[[R0]])
72
73 define float @msa_extract_0() {
74 entry:
75 %0 = load volatile <4 x float>* @v4f32
76 %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
77
78 ; Clobber all except $f12, and $f13
79 ;
80 ; The intention is that if odd single precision registers are permitted, the
81 ; allocator will choose $f13/$w13 for the vector since that saves on moves.
82 ;
83 ; On the other hand, if odd single precision registers are not permitted, it
84 ; must move it to $f12/$w12.
85 call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
86
87 %2 = extractelement <4 x float> %1, i32 0
88 ret float %2
89 }
90
91 ; ALL-LABEL: msa_extract_0:
92 ; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
93 ; ALL: ld.w $w12, 0($[[R0]])
94 ; ALL: move.v $w[[W0:13]], $w12
95 ; NOODDSPREG: move.v $w[[W0:12]], $w13
96 ; ALL: # Clobber
97 ; ALL-NOT: st.w
98 ; ALL-NOT: ld.w
99 ; ALL: mov.s $f0, $f[[W0]]
100
101 define float @msa_extract_1() {
102 entry:
103 %0 = load volatile <4 x float>* @v4f32
104 %1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
105
106 ; Clobber all except $f13
107 ;
108 ; The intention is that if odd single precision registers are permitted, the
109 ; allocator will choose $f13/$w13 for the vector since that saves on moves.
110 ;
111 ; On the other hand, if odd single precision registers are not permitted, it
112 ; must be spilled.
113 call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
114
115 %2 = extractelement <4 x float> %1, i32 1
116 ret float %2
117 }
118
119 ; ALL-LABEL: msa_extract_1:
120 ; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
121 ; ALL: ld.w $w12, 0($[[R0]])
122 ; ALL: splati.w $w[[W0:[0-9]+]], $w13[1]
123 ; NOODDSPREG: st.w $w[[W0]], 0($sp)
124 ; ODDSPREG-NOT: st.w
125 ; ODDSPREG-NOT: ld.w
126 ; ALL: # Clobber
127 ; ODDSPREG-NOT: st.w
128 ; ODDSPREG-NOT: ld.w
129 ; NOODDSPREG: ld.w $w0, 0($sp)
130 ; ODDSPREG: mov.s $f0, $f[[W0]]