llvm.org GIT mirror llvm / 937f85f
[ARM|CodeGen] Improve the code in FastISel Cleaned up the code in FastISel a bit. Had to add make_range to MCInstrDesc as that was needed and seems missing. Reviewed by: @t.p.northover Differential Revision: https://reviews.llvm.org/D35494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308291 91177308-0d34-0410-b5e6-96231b3b80d8 Javed Absar 3 years ago
2 changed file(s) with 29 addition(s) and 23 deletion(s). Raw diff Collapse all Expand all
208208 /// well.
209209 unsigned getNumOperands() const { return NumOperands; }
210210
211 using const_opInfo_iterator = const MCOperandInfo *;
212
213 const_opInfo_iterator opInfo_begin() const { return OpInfo; }
214 const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
215
216 iterator_range operands() const {
217 return make_range(opInfo_begin(), opInfo_end());
218 }
219
211220 /// \brief Return the number of MachineOperands that are register
212221 /// definitions. Register definitions always occur at the start of the
213222 /// machine operand list. This is the number of "outs" in the .td file,
249249 return false;
250250
251251 // Look to see if our OptionalDef is defining CPSR or CCR.
252 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
253 const MachineOperand &MO = MI->getOperand(i);
252 for (const MachineOperand &MO : MI->operands()) {
254253 if (!MO.isReg() || !MO.isDef()) continue;
255254 if (MO.getReg() == ARM::CPSR)
256255 *CPSR = true;
266265 AFI->isThumb2Function())
267266 return MI->isPredicable();
268267
269 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
270 if (MCID.OpInfo[i].isPredicate())
268 for (const MCOperandInfo &opInfo : MCID.operands())
269 if (opInfo.isPredicate())
271270 return true;
272271
273272 return false;
19711970 break;
19721971 }
19731972 case CCValAssign::AExt:
1974 // Intentional fall-through. Handle AExt and ZExt.
1973 // Intentional fall-through. Handle AExt and ZExt.
19751974 case CCValAssign::ZExt: {
19761975 MVT DestVT = VA.getLocVT();
19771976 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
20001999 assert(VA.getLocVT() == MVT::f64 &&
20012000 "Custom lowering for v2f64 args not available");
20022001
2002 // FIXME: ArgLocs[++i] may extend beyond ArgLocs.size()
20032003 CCValAssign &NextVA = ArgLocs[++i];
20042004
20052005 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
21712171 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
21722172 TII.get(RetOpc));
21732173 AddOptionalDefs(MIB);
2174 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2175 MIB.addReg(RetRegs[i], RegState::Implicit);
2174 for (unsigned R : RetRegs)
2175 MIB.addReg(R, RegState::Implicit);
21762176 return true;
21772177 }
21782178
22322232 ArgRegs.reserve(I->getNumOperands());
22332233 ArgVTs.reserve(I->getNumOperands());
22342234 ArgFlags.reserve(I->getNumOperands());
2235 for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2236 Value *Op = I->getOperand(i);
2235 for (Value *Op : I->operands()) {
22372236 unsigned Arg = getRegForValue(Op);
22382237 if (Arg == 0) return false;
22392238
22772276 MIB.addExternalSymbol(TLI.getLibcallName(Call));
22782277
22792278 // Add implicit physical register uses to the call.
2280 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2281 MIB.addReg(RegArgs[i], RegState::Implicit);
2279 for (unsigned R : RegArgs)
2280 MIB.addReg(R, RegState::Implicit);
22822281
22832282 // Add a register mask with the call-preserved registers.
22842283 // Proper defs for return values will be added by setPhysRegsDeadExcept().
24222421 MIB.addExternalSymbol(IntrMemName, 0);
24232422
24242423 // Add implicit physical register uses to the call.
2425 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2426 MIB.addReg(RegArgs[i], RegState::Implicit);
2424 for (unsigned R : RegArgs)
2425 MIB.addReg(R, RegState::Implicit);
24272426
24282427 // Add a register mask with the call-preserved registers.
24292428 // Proper defs for return values will be added by setPhysRegsDeadExcept().
29312930
29322931 bool Found = false;
29332932 bool isZExt;
2934 for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
2935 i != e; ++i) {
2936 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
2937 (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
2938 MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
2933 for (const FoldableLoadExtendsStruct &FLE : FoldableLoadExtends) {
2934 if (FLE.Opc[isThumb2] == MI->getOpcode() &&
2935 (uint64_t)FLE.ExpectedImm == Imm &&
2936 MVT((MVT::SimpleValueType)FLE.ExpectedVT) == VT) {
29392937 Found = true;
2940 isZExt = FoldableLoadExtends[i].isZExt;
2938 isZExt = FLE.isZExt;
29412939 }
29422940 }
29432941 if (!Found) return false;
30563054 };
30573055
30583056 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3059 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3060 I != E; ++I) {
3061 unsigned ArgNo = I->getArgNo();
3057 for (const Argument &Arg : F->args()) {
3058 unsigned ArgNo = Arg.getArgNo();
30623059 unsigned SrcReg = GPRArgRegs[ArgNo];
30633060 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
30643061 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
30683065 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
30693066 TII.get(TargetOpcode::COPY),
30703067 ResultReg).addReg(DstReg, getKillRegState(true));
3071 updateValueMap(&*I, ResultReg);
3068 updateValueMap(&Arg, ResultReg);
30723069 }
30733070
30743071 return true;