llvm.org GIT mirror llvm / 9364ca1
Merging r245741: ------------------------------------------------------------------------ r245741 | hfinkel | 2015-08-21 17:34:24 -0400 (Fri, 21 Aug 2015) | 8 lines [PowerPC] PPCVSXFMAMutate should not segfault on undef input registers When PPCVSXFMAMutate would look at the input addend register, it would get its input value number. This would fail, however, if the register was undef, causing a segfault. Don't segfault (just skip such FMA instructions). Fixes the test case from PR24542 (although that may have been over-reduced). ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@252132 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
2 changed file(s) with 38 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
102102
103103 VNInfo *AddendValNo =
104104 LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn();
105 if (!AddendValNo) {
106 // This can be null if the register is undef.
107 continue;
108 }
109
105110 MachineInstr *AddendMI = LIS->getInstructionFromIndex(AddendValNo->def);
106111
107112 // The addend and this instruction must be in the same block.
0 ; RUN: llc < %s | FileCheck %s
1 target datalayout = "e-m:e-i64:64-n32:64"
2 target triple = "powerpc64le-unknown-linux-gnu"
3
4 ; Function Attrs: nounwind
5 define void @acosh_float8() #0 {
6 entry:
7 br i1 undef, label %if.then, label %if.end
8
9 if.then: ; preds = %entry
10 %0 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> undef, <4 x float> , <4 x float> undef) #0
11 %astype.i.i.74.i = bitcast <4 x float> %0 to <4 x i32>
12 %and.i.i.76.i = and <4 x i32> %astype.i.i.74.i, undef
13 %or.i.i.79.i = or <4 x i32> %and.i.i.76.i, undef
14 %astype5.i.i.80.i = bitcast <4 x i32> %or.i.i.79.i to <4 x float>
15 %1 = shufflevector <4 x float> %astype5.i.i.80.i, <4 x float> undef, <8 x i32>
16 %2 = shufflevector <8 x float> undef, <8 x float> %1, <8 x i32>
17 store <8 x float> %2, <8 x float>* undef, align 32
18 br label %if.end
19
20 ; CHECK-LABEL: @acosh_float8
21 ; CHECK: xvmaddasp
22
23 if.end: ; preds = %if.then, %entry
24 ret void
25 }
26
27 ; Function Attrs: nounwind readnone
28 declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
29
30 attributes #0 = { nounwind }
31 attributes #1 = { nounwind readnone }
32