llvm.org GIT mirror llvm / 933d2bd
Fix "the the" in comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240112 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 4 years ago
32 changed file(s) with 40 addition(s) and 40 deletion(s). Raw diff Collapse all Expand all
160160
161161 .. option:: --show-tests
162162
163 List all of the the discovered tests and exit.
163 List all of the discovered tests and exit.
164164
165165 EXIT STATUS
166166 -----------
111111 (cd pcre; ./autogen.sh; CC="clang -fsanitize=address $COV_FLAGS" ./configure --prefix=`pwd`/../inst && make -j && make install)
112112 # Build lib/Fuzzer files.
113113 clang -c -g -O2 -std=c++11 Fuzzer/*.cpp -IFuzzer
114 # Build the the actual function that does something interesting with PCRE2.
114 # Build the actual function that does something interesting with PCRE2.
115115 cat << EOF > pcre_fuzzer.cc
116116 #include
117117 #include "pcre2posix.h"
872872 ///
873873 /// \pre \a computeMassInLoop() has been called for each subloop of \c
874874 /// OuterLoop.
875 /// \pre \c Insert points at the the last loop successfully processed by \a
875 /// \pre \c Insert points at the last loop successfully processed by \a
876876 /// computeMassInLoop().
877877 /// \pre \c OuterLoop has irreducible SCCs.
878878 void computeIrreducibleMass(LoopData *OuterLoop,
123123 static ErrorOr>
124124 getFileOrSTDIN(const Twine &Filename, int64_t FileSize = -1);
125125
126 /// Map a subrange of the the specified file as a MemoryBuffer.
126 /// Map a subrange of the specified file as a MemoryBuffer.
127127 static ErrorOr>
128128 getFileSlice(const Twine &Filename, uint64_t MapSize, uint64_t Offset);
129129
23932393 /// outgoing token chain. It calls LowerCall to do the actual lowering.
23942394 std::pair LowerCallTo(CallLoweringInfo &CLI) const;
23952395
2396 /// This hook must be implemented to lower calls into the the specified
2396 /// This hook must be implemented to lower calls into the specified
23972397 /// DAG. The outgoing arguments to the call are described by the Outs array,
23982398 /// and the values to be returned by the call are described by the Ins
23992399 /// array. The implementation should fill in the InVals array with legal-type
17011701
17021702 unsigned NumElim = 0;
17031703 DenseMap ExprToIVMap;
1704 // Process phis from wide to narrow. Mapping wide phis to the their truncation
1704 // Process phis from wide to narrow. Map wide phis to their truncation
17051705 // so narrow phis can reuse them.
17061706 for (SmallVectorImpl::const_iterator PIter = Phis.begin(),
17071707 PEnd = Phis.end(); PIter != PEnd; ++PIter) {
463463 Value *ShouldStore =
464464 Builder.CreateICmpEQ(Loaded, CI->getCompareOperand(), "should_store");
465465
466 // If the the cmpxchg doesn't actually need any ordering when it fails, we can
466 // If the cmpxchg doesn't actually need any ordering when it fails, we can
467467 // jump straight past that fence instruction (if it exists).
468468 Builder.CreateCondBr(ShouldStore, TryStoreBB, FailureBB);
469469
6060 // The block the check resides in.
6161 MachineBasicBlock *CheckBlock;
6262
63 // The block branched to if the the pointer is non-null.
63 // The block branched to if the pointer is non-null.
6464 MachineBasicBlock *NotNullSucc;
6565
66 // The block branched to if the the pointer is null.
66 // The block branched to if the pointer is null.
6767 MachineBasicBlock *NullSucc;
6868
6969 NullCheck()
21492149 bool IsPostRA,
21502150 SchedBoundary &CurrZone,
21512151 SchedBoundary *OtherZone) {
2152 // Apply preemptive heuristics based on the the total latency and resources
2152 // Apply preemptive heuristics based on the total latency and resources
21532153 // inside and outside this zone. Potential stalls should be considered before
21542154 // following this policy.
21552155
22952295 // value for this block but the value is a nullptr. This means that
22962296 // we have previously analyzed the block and determined that it did
22972297 // not contain any cleanup code. Based on the earlier analysis, we
2298 // know the the block must end in either an unconditional branch, a
2298 // know the block must end in either an unconditional branch, a
22992299 // resume or a conditional branch that is predicated on a comparison
23002300 // with a selector. Either the resume or the selector dispatch
23012301 // would terminate the search for cleanup code, so the unconditional
1414
1515 bool isPrint(int UCS) {
1616 #if LLVM_ON_WIN32
17 // Restrict characters that we'll try to print to the the lower part of ASCII
17 // Restrict characters that we'll try to print to the lower part of ASCII
1818 // except for the control characters (0x20 - 0x7E). In general one can not
1919 // reliably output code points U+0080 and higher using narrow character C/C++
2020 // output functions in Windows, because the meaning of the upper 128 codes is
14231423 ConstantSDNode *CFVal = dyn_cast(FVal);
14241424 ConstantSDNode *CTVal = dyn_cast(TVal);
14251425
1426 // The the values aren't constants, this isn't the pattern we're looking for.
1426 // The values aren't constants, this isn't the pattern we're looking for.
14271427 if (!CFVal || !CTVal)
14281428 return Op;
14291429
34193419 EltVT = MVT::i64;
34203420 VecVT = MVT::v2i64;
34213421
3422 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3422 // We want to materialize a mask with the high bit set, but the AdvSIMD
34233423 // immediate moves cannot materialize that in a single instruction for
34243424 // 64-bit elements. Instead, materialize zero and then negate it.
34253425 EltMask = 0;
5151 /// returns zero and isBranch is Success then a symbol look up for
5252 /// Address + Value is done and if a symbol is found an MCExpr is created with
5353 /// that, else an MCExpr with Address + Value is created. If GetOpInfo()
54 /// returns zero and isBranch is Fail then the the Opcode of the MCInst is
54 /// returns zero and isBranch is Fail then the Opcode of the MCInst is
5555 /// tested and for ADRP an other instructions that help to load of pointers
5656 /// a symbol look up is done to see it is returns a specific reference type
5757 /// to add to the comment stream. This function returns Success if it adds
131131 /// private memory do not exceed this size. For example, if the
132132 /// element size is 4 (32-bits or dword) and a 64-bit value must be
133133 /// loaded, the finalizer will generate two 32-bit loads. This
134 /// ensures that the interleaving will get the the work-item
134 /// ensures that the interleaving will get the work-item
135135 /// specific dword for both halves of the 64-bit value. If it just
136136 /// did a 64-bit load then it would get one dword which belonged to
137137 /// its own work-item, but the second dword would belong to the
18051805 }
18061806
18071807 MachineBasicBlock &MBB = *MI->getParent();
1808 // Extract the the ptr from the resource descriptor.
1808 // Extract the ptr from the resource descriptor.
18091809
18101810 // SRsrcPtrLo = srsrc:sub0
18111811 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
58405840 // do and don't have a cc_out optional-def operand. With some spot-checks
58415841 // of the operand list, we can figure out which variant we're trying to
58425842 // parse and adjust accordingly before actually matching. We shouldn't ever
5843 // try to remove a cc_out operand that was explicitly set on the the
5843 // try to remove a cc_out operand that was explicitly set on the
58445844 // mnemonic, of course (CarrySetting == true). Reason number #317 the
58455845 // table driven matcher doesn't fit well with the ARM instruction set.
58465846 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
10641064 // it's just a plain immediate expression, previously those evaluated to
10651065 // the lower 16 bits of the expression regardless of whether
10661066 // we have a movt or a movw, but that led to misleadingly results.
1067 // This is now disallowed in the the AsmParser in validateInstruction()
1067 // This is disallowed in the AsmParser in validateInstruction()
10681068 // so this should never happen.
10691069 llvm_unreachable("expression without :upper16: or :lower16:");
10701070 }
270270 /// register DI/EDI/ESI.
271271 RawFrmDst = 9,
272272
273 /// RawFrmSrc - This form is for instructions that use the the source index
273 /// RawFrmSrc - This form is for instructions that use the source index
274274 /// register SI/ESI/ERI with a possible segment override, and also the
275275 /// destination index register DI/ESI/RDI.
276276 RawFrmDstSrc = 10,
4343 /// \brief Given a machine register, look for the instruction
4444 /// which writes it in the current basic block. If found,
4545 /// try to replace it with an equivalent LEA instruction.
46 /// If replacement succeeds, then also process the the newly created
46 /// If replacement succeeds, then also process the newly created
4747 /// instruction.
4848 void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
4949 MachineFunction::iterator MFI);
54455445 ///
54465446 /// Otherwise, the first horizontal binop dag node takes as input the lower
54475447 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5448 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5448 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
54495449 /// Example:
54505450 /// HADD V0_LO, V1_LO
54515451 /// HADD V0_HI, V1_HI
211211 break;
212212
213213 // Now we know that we have not seen either the store or the release. If I
214 // is the the release, mark that we saw the release and continue.
214 // is the release, mark that we saw the release and continue.
215215 Instruction *Inst = &*I;
216216 if (Inst == Release) {
217217 SawRelease = true;
758758
759759 if (CmpInst *CondCmp = dyn_cast(CondInst)) {
760760 // If we're branching on a conditional, LVI might be able to determine
761 // it's value at the the branch instruction. We only handle comparisons
761 // it's value at the branch instruction. We only handle comparisons
762762 // against a constant at this time.
763763 // TODO: This should be extended to handle switches as well.
764764 BranchInst *CondBr = dyn_cast(BB->getTerminator());
281281 /// \brief Find equivalence classes for the given block.
282282 ///
283283 /// This finds all the blocks that are guaranteed to execute the same
284 /// number of times as \p BB1. To do this, it traverses all the the
284 /// number of times as \p BB1. To do this, it traverses all the
285285 /// descendants of \p BB1 in the dominator or post-dominator tree.
286286 ///
287287 /// A block BB2 will be in the same equivalence class as \p BB1 if
40574057 return false;
40584058
40594059 // Figure out the corresponding result for each case value and phi node in the
4060 // common destination, as well as the the min and max case values.
4060 // common destination, as well as the min and max case values.
40614061 assert(SI->case_begin() != SI->case_end());
40624062 SwitchInst::CaseIt CI = SI->case_begin();
40634063 ConstantInt *MinCaseVal = CI.getCaseValue();
2323 }
2424
2525 ; Check that we manage to form a zextload is an operation with only one
26 ; argument to explicitly extend is in the the way.
26 ; argument to explicitly extend is in the way.
2727 ; OPTALL-LABEL: @promoteOneArg
2828 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
2929 ; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
4848 }
4949
5050 ; Check that we manage to form a sextload is an operation with only one
51 ; argument to explicitly extend is in the the way.
51 ; argument to explicitly extend is in the way.
5252 ; Version with sext.
5353 ; OPTALL-LABEL: @promoteOneArgSExt
5454 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
7373 }
7474
7575 ; Check that we manage to form a zextload is an operation with two
76 ; arguments to explicitly extend is in the the way.
76 ; arguments to explicitly extend is in the way.
7777 ; Extending %add will create two extensions:
7878 ; 1. One for %b.
7979 ; 2. One for %t.
112112 }
113113
114114 ; Check that we manage to form a sextload is an operation with two
115 ; arguments to explicitly extend is in the the way.
115 ; arguments to explicitly extend is in the way.
116116 ; Version with sext.
117117 ; OPTALL-LABEL: @promoteTwoArgSExt
118118 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
1313
1414 ; EG: {{^}}local_memory_two_objects:
1515
16 ; We would like to check the the lds writes are using different
16 ; We would like to check the lds writes are using different
1717 ; addresses, but due to variations in the scheduler, we can't do
1818 ; this consistently on evergreen GPUs.
1919 ; EG: LDS_WRITE
33 ; RUN: llc -mtriple thumb-unknown-linux-gnueabi -filetype asm -o - %s -disable-fp-elim | FileCheck %s --check-prefix=CHECK-THUMB-FP-ELIM
44
55 ; Tests that the initial space allocated to the varargs on the stack is
6 ; taken into account in the the .cfi_ directives.
6 ; taken into account in the .cfi_ directives.
77
88 ; Generated from the C program:
99 ; #include
1717 ; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64-INV %s
1818 ; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64-INV %s
1919
20 ; Test the the callee-saved registers are callee-saved as specified by section
20 ; Test the callee-saved registers are callee-saved as specified by section
2121 ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec.
2222
2323 define void @gpr_clobber() nounwind {
2929 }
3030
3131 ; Check that we manage to form a zextload is an operation with only one
32 ; argument to explicitly extend is in the the way.
32 ; argument to explicitly extend is in the way.
3333 ; OPTALL-LABEL: @promoteOneArg
3434 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
3535 ; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32
5454 }
5555
5656 ; Check that we manage to form a sextload is an operation with only one
57 ; argument to explicitly extend is in the the way.
57 ; argument to explicitly extend is in the way.
5858 ; Version with sext.
5959 ; OPTALL-LABEL: @promoteOneArgSExt
6060 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
7979 }
8080
8181 ; Check that we manage to form a zextload is an operation with two
82 ; arguments to explicitly extend is in the the way.
82 ; arguments to explicitly extend is in the way.
8383 ; Extending %add will create two extensions:
8484 ; 1. One for %b.
8585 ; 2. One for %t.
118118 }
119119
120120 ; Check that we manage to form a sextload is an operation with two
121 ; arguments to explicitly extend is in the the way.
121 ; arguments to explicitly extend is in the way.
122122 ; Version with sext.
123123 ; OPTALL-LABEL: @promoteTwoArgSExt
124124 ; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p
787787 // Set the size of the literal pointer.
788788 uint32_t lp_size = O->is64Bit() ? 8 : 4;
789789
790 // Collect the external relocation symbols for the the literal pointers.
790 // Collect the external relocation symbols for the literal pointers.
791791 std::vector> Relocs;
792792 for (const RelocationRef &Reloc : Section.relocations()) {
793793 DataRefImpl Rel;
9696 return result.size();
9797 }
9898
99 /// @brief Return the the printing format for the Radix.
99 /// @brief Return the printing format for the Radix.
100100 static const char *getRadixFmt(void) {
101101 switch (Radix) {
102102 case octal:
128128
129129 // Aligning the current slab pointer is likely to move it past the end of the
130130 // slab, which would confuse any unsigned comparisons with the difference of
131 // the the end pointer and the aligned pointer.
131 // the end pointer and the aligned pointer.
132132 Alloc.Allocate(1024, 8192);
133133
134134 EXPECT_EQ(2U, Alloc.GetNumSlabs());