llvm.org GIT mirror llvm / 92e2862
[mips] Refine octeon instructions seq/seqi/sne/snei This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225968 91177308-0d34-0410-b5e6-96231b3b80d8 Kai Nacke 5 years ago
2 changed file(s) with 70 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
289289 class SetCC64_R :
290290 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
291291 !strconcat(opstr, "\t$rd, $rs, $rt"),
292 [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
292 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
293 GPR64Opnd:$rt)))],
293294 II_SEQ_SNE, FrmR, opstr> {
294295 let TwoOperandAliasConstraint = "$rd = $rs";
295296 }
297298 class SetCC64_I:
298299 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
299300 !strconcat(opstr, "\t$rt, $rs, $imm10"),
300 [(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
301 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
302 immSExt10_64:$imm10)))],
301303 II_SEQI_SNEI, FrmI, opstr> {
302304 let TwoOperandAliasConstraint = "$rt = $rs";
303305 }
2626 %res = mul i64 %a, %b
2727 ret i64 %res
2828 }
29
30 define i64 @cmpeq(i64 %a, i64 %b) nounwind {
31 entry:
32 ; OCTEON-LABEL: cmpeq:
33 ; OCTEON: jr $ra
34 ; OCTEON: seq $2, $4, $5
35 ; MIPS64-LABEL: cmpeq:
36 ; MIPS64: xor $1, $4, $5
37 ; MIPS64: sltiu $1, $1, 1
38 ; MIPS64: dsll $1, $1, 32
39 ; MIPS64: jr $ra
40 ; MIPS64: dsrl $2, $1, 32
41 %res = icmp eq i64 %a, %b
42 %res2 = zext i1 %res to i64
43 ret i64 %res2
44 }
45
46 define i64 @cmpeqi(i64 %a) nounwind {
47 entry:
48 ; OCTEON-LABEL: cmpeqi:
49 ; OCTEON: jr $ra
50 ; OCTEON: seqi $2, $4, 42
51 ; MIPS64-LABEL: cmpeqi:
52 ; MIPS64: daddiu $1, $zero, 42
53 ; MIPS64: xor $1, $4, $1
54 ; MIPS64: sltiu $1, $1, 1
55 ; MIPS64: dsll $1, $1, 32
56 ; MIPS64: jr $ra
57 ; MIPS64: dsrl $2, $1, 32
58 %res = icmp eq i64 %a, 42
59 %res2 = zext i1 %res to i64
60 ret i64 %res2
61 }
62
63 define i64 @cmpne(i64 %a, i64 %b) nounwind {
64 entry:
65 ; OCTEON-LABEL: cmpne:
66 ; OCTEON: jr $ra
67 ; OCTEON: sne $2, $4, $5
68 ; MIPS64-LABEL: cmpne:
69 ; MIPS64: xor $1, $4, $5
70 ; MIPS64: sltu $1, $zero, $1
71 ; MIPS64: dsll $1, $1, 32
72 ; MIPS64: jr $ra
73 ; MIPS64: dsrl $2, $1, 32
74 %res = icmp ne i64 %a, %b
75 %res2 = zext i1 %res to i64
76 ret i64 %res2
77 }
78
79 define i64 @cmpnei(i64 %a) nounwind {
80 entry:
81 ; OCTEON-LABEL: cmpnei:
82 ; OCTEON: jr $ra
83 ; OCTEON: snei $2, $4, 42
84 ; MIPS64-LABEL: cmpnei:
85 ; MIPS64: daddiu $1, $zero, 42
86 ; MIPS64: xor $1, $4, $1
87 ; MIPS64: sltu $1, $zero, $1
88 ; MIPS64: dsll $1, $1, 32
89 ; MIPS64: jr $ra
90 ; MIPS64: dsrl $2, $1, 32
91 %res = icmp ne i64 %a, 42
92 %res2 = zext i1 %res to i64
93 ret i64 %res2
94 }