llvm.org GIT mirror llvm / 92dfe20
Remove isReg, isImm, and isMBB, and change all their users to use isRegister, isImmediate, and isMachineBasicBlock, which are equivalent, and more popular. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41958 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 13 years ago
17 changed file(s) with 57 addition(s) and 61 deletion(s). Raw diff Collapse all Expand all
228228 bool Removed = false;
229229 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
230230 MachineOperand &MO = MI->getOperand(i);
231 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
231 if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) {
232232 MO.unsetIsKill();
233233 Removed = true;
234234 break;
265265 bool Removed = false;
266266 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
267267 MachineOperand &MO = MI->getOperand(i);
268 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
268 if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) {
269269 MO.unsetIsDead();
270270 Removed = true;
271271 break;
130130
131131 /// Accessors that tell you what kind of MachineOperand you're looking at.
132132 ///
133 bool isReg() const { return opType == MO_Register; }
134 bool isImm() const { return opType == MO_Immediate; }
135 bool isMBB() const { return opType == MO_MachineBasicBlock; }
136
137133 bool isRegister() const { return opType == MO_Register; }
138134 bool isImmediate() const { return opType == MO_Immediate; }
139135 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
144140 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
145141
146142 int64_t getImm() const {
147 assert(isImm() && "Wrong MachineOperand accessor");
143 assert(isImmediate() && "Wrong MachineOperand accessor");
148144 return contents.immedVal;
149145 }
150146
151147 int64_t getImmedValue() const {
152 assert(isImm() && "Wrong MachineOperand accessor");
148 assert(isImmediate() && "Wrong MachineOperand accessor");
153149 return contents.immedVal;
154150 }
155151 MachineBasicBlock *getMBB() const {
256252 }
257253
258254 void setImmedValue(int64_t immVal) {
259 assert(isImm() && "Wrong MachineOperand mutator");
255 assert(isImmediate() && "Wrong MachineOperand mutator");
260256 contents.immedVal = immVal;
261257 }
262258 void setImm(int64_t immVal) {
263 assert(isImm() && "Wrong MachineOperand mutator");
259 assert(isImmediate() && "Wrong MachineOperand mutator");
264260 contents.immedVal = immVal;
265261 }
266262
981981
982982 // Count the number of register definitions.
983983 unsigned NumDefs = 0;
984 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
984 for (; MI->getOperand(NumDefs).isRegister() && MI->getOperand(NumDefs).isDef();
985985 ++NumDefs)
986986 assert(NumDefs != NumOperands-1 && "No asm string?");
987987
412412 bool HasUse = mop.isUse();
413413 bool HasDef = mop.isDef();
414414 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) {
415 if (MI->getOperand(j).isReg() &&
415 if (MI->getOperand(j).isRegister() &&
416416 MI->getOperand(j).getReg() == li.reg) {
417417 MI->getOperand(j).setReg(NewVReg);
418418 HasUse |= MI->getOperand(j).isUse();
7777 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
7878 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
7979 MachineOperand &MO = MI->getOperand(i);
80 if (MO.isReg() && MO.isKill()) {
80 if (MO.isRegister() && MO.isKill()) {
8181 if ((MO.getReg() == Reg) ||
8282 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
8383 MRegisterInfo::isPhysicalRegister(Reg) &&
9191 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
9292 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
9393 MachineOperand &MO = MI->getOperand(i);
94 if (MO.isReg() && MO.isDead()) {
94 if (MO.isRegister() && MO.isDead()) {
9595 if ((MO.getReg() == Reg) ||
9696 (MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
9797 MRegisterInfo::isPhysicalRegister(Reg) &&
105105 bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
106106 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
107107 MachineOperand &MO = MI->getOperand(i);
108 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
108 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
109109 return true;
110110 }
111111 return false;
189189 bool Found = false;
190190 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
191191 MachineOperand &MO = MI->getOperand(i);
192 if (MO.isReg() && MO.isUse()) {
192 if (MO.isRegister() && MO.isUse()) {
193193 unsigned Reg = MO.getReg();
194194 if (!Reg)
195195 continue;
220220 bool Found = false;
221221 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
222222 MachineOperand &MO = MI->getOperand(i);
223 if (MO.isReg() && MO.isDef()) {
223 if (MO.isRegister() && MO.isDef()) {
224224 unsigned Reg = MO.getReg();
225225 if (!Reg)
226226 continue;
613613 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
614614 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
615615 MachineOperand &MO = MI->getOperand(i);
616 if (MO.isReg() && MO.isKill()) {
616 if (MO.isRegister() && MO.isKill()) {
617617 MO.unsetIsKill();
618618 unsigned Reg = MO.getReg();
619619 if (MRegisterInfo::isVirtualRegister(Reg)) {
629629 void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
630630 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
631631 MachineOperand &MO = MI->getOperand(i);
632 if (MO.isReg() && MO.isDead()) {
632 if (MO.isRegister() && MO.isDead()) {
633633 MO.unsetIsDead();
634634 unsigned Reg = MO.getReg();
635635 if (MRegisterInfo::isVirtualRegister(Reg)) {
6565
6666 assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
6767 MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
68 MI->getOperand(2).isImm() && "Malformed extract_subreg");
68 MI->getOperand(2).isImmediate() && "Malformed extract_subreg");
6969
7070 unsigned SuperReg = MI->getOperand(1).getReg();
7171 unsigned SubIdx = MI->getOperand(2).getImm();
112112 if (MI->getNumOperands() == 3) {
113113 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
114114 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
115 MI->getOperand(2).isImm() && "Invalid extract_subreg");
115 MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
116116 DstReg = MI->getOperand(0).getReg();
117117 SrcReg = DstReg;
118118 InsReg = MI->getOperand(1).getReg();
121121 assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
122122 (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
123123 (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
124 MI->getOperand(3).isImm() && "Invalid extract_subreg");
124 MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
125125 DstReg = MI->getOperand(0).getReg();
126126 SrcReg = MI->getOperand(1).getReg();
127127 InsReg = MI->getOperand(2).getReg();
187187 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
188188 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
189189 const MachineOperand &MO = getOperand(i);
190 if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
190 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
191191 if (!isKill || MO.isKill())
192192 return i;
193193 }
199199 MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
200200 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
201201 MachineOperand &MO = getOperand(i);
202 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
202 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
203203 return &MO;
204204 }
205205 return NULL;
224224 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
225225 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
226226 const MachineOperand &MO = MI->getOperand(i);
227 if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
227 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
228228 continue;
229229 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
230230 MachineOperand &MOp = getOperand(j);
247247 if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
248248 const MachineOperand &MO = MI->getOperand(i);
249249 // Predicated operands must be last operands.
250 if (MO.isReg())
250 if (MO.isRegister())
251251 addRegOperand(MO.getReg(), false);
252252 else {
253253 addImmOperand(MO.getImm());
318318 unsigned StartOp = 0;
319319
320320 // Specialize printing if op#0 is definition
321 if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
321 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
322322 ::print(getOperand(0), OS, TM);
323323 if (getOperand(0).isDead())
324324 OS << "";
336336 OS << " ";
337337 ::print(mop, OS, TM);
338338
339 if (mop.isReg()) {
339 if (mop.isRegister()) {
340340 if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
341341 OS << "<";
342342 bool NeedComma = false;
380380
381381 for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
382382 os << "\t" << getOperand(i);
383 if (getOperand(i).isReg() && getOperand(i).isDef())
383 if (getOperand(i).isRegister() && getOperand(i).isDef())
384384 os << "";
385385 }
386386
101101 BitVector ChangedRegs(NumPhysRegs);
102102 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
103103 const MachineOperand &MO = MI->getOperand(i);
104 if (!MO.isReg() || !MO.isUse())
104 if (!MO.isRegister() || !MO.isUse())
105105 continue;
106106 unsigned Reg = MO.getReg();
107107 if (Reg == 0)
124124 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
125125 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
126126 const MachineOperand &MO = MI->getOperand(i);
127 if (!MO.isReg() || !MO.isDef())
127 if (!MO.isRegister() || !MO.isDef())
128128 continue;
129129 unsigned Reg = MO.getReg();
130130 // If it's dead upon def, then it is now free.
154154 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
155155 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
156156 const MachineOperand &MO = MI->getOperand(i);
157 if (!MO.isReg() || !MO.isDef())
157 if (!MO.isRegister() || !MO.isDef())
158158 continue;
159159 // Skip two-address destination operand.
160160 if (TID->findTiedToSrcOperand(i) != -1)
169169 BitVector ChangedRegs(NumPhysRegs);
170170 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
171171 const MachineOperand &MO = MI->getOperand(i);
172 if (!MO.isReg() || !MO.isUse())
172 if (!MO.isRegister() || !MO.isUse())
173173 continue;
174174 unsigned Reg = MO.getReg();
175175 if (Reg == 0)
256256 // Exclude all the registers being used by the instruction.
257257 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
258258 MachineOperand &MO = I->getOperand(i);
259 if (MO.isReg())
259 if (MO.isRegister())
260260 Candidates.reset(MO.getReg());
261261 }
262262
985985
986986 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
987987 MachineOperand &MO = MI->getOperand(i);
988 if (MO.isReg() && MO.isUse() && MO.getReg() &&
988 if (MO.isRegister() && MO.isUse() && MO.getReg() &&
989989 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
990990 MOU = &MO;
991991 return MI;
10041004 MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsigned Reg) {
10051005 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
10061006 MachineOperand &MO = MI->getOperand(i);
1007 if (MO.isReg() && MO.isDef() &&
1007 if (MO.isRegister() && MO.isDef() &&
10081008 mri_->regsOverlap(rep(MO.getReg()), Reg))
10091009 return &MO;
10101010 }
10161016 void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
10171017 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
10181018 MachineOperand &MO = MI->getOperand(i);
1019 if (MO.isReg() && MO.isKill() && MO.getReg() &&
1019 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
10201020 mri_->regsOverlap(rep(MO.getReg()), Reg))
10211021 MO.unsetIsKill();
10221022 }
10401040
10411041 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
10421042 MachineOperand &MO = MI->getOperand(i);
1043 if (MO.isReg() && MO.isKill() && MO.getReg() &&
1043 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
10441044 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
10451045 MO.unsetIsKill();
10461046 }
10551055 bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) {
10561056 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
10571057 MachineOperand &MO = MI->getOperand(i);
1058 if (MO.isReg() && MO.isDef() &&
1058 if (MO.isRegister() && MO.isDef() &&
10591059 mri_->regsOverlap(rep(MO.getReg()), Reg))
10601060 return true;
10611061 }
445445 SmallVector *KillRegs = NULL) {
446446 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
447447 MachineOperand &MO = MI.getOperand(i);
448 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
448 if (!MO.isRegister() || !MO.isUse() || !MO.isKill())
449449 continue;
450450 unsigned Reg = MO.getReg();
451451 if (KillRegs)
470470 MachineOperand *DefOp = NULL;
471471 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
472472 MachineOperand &MO = DefMI->getOperand(i);
473 if (MO.isReg() && MO.isDef()) {
473 if (MO.isRegister() && MO.isDef()) {
474474 if (MO.getReg() == Reg)
475475 DefOp = &MO;
476476 else if (!MO.isDead())
487487 MachineInstr *NMI = I;
488488 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
489489 MachineOperand &MO = NMI->getOperand(j);
490 if (!MO.isReg() || MO.getReg() != Reg)
490 if (!MO.isRegister() || MO.getReg() != Reg)
491491 continue;
492492 if (MO.isUse())
493493 FoundUse = true;
510510 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
511511 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
512512 MachineOperand &MO = MI.getOperand(i);
513 if (!MO.isReg() || !MO.isUse())
513 if (!MO.isRegister() || !MO.isUse())
514514 continue;
515515 unsigned Reg = MO.getReg();
516516 if (Reg == 0)
534534
535535 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
536536 const MachineOperand &MO = MI.getOperand(i);
537 if (!MO.isReg() || !MO.isDef())
537 if (!MO.isRegister() || !MO.isDef())
538538 continue;
539539 unsigned Reg = MO.getReg();
540540 RegKills.reset(Reg);
825825 bool CanReuse = true;
826826 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
827827 if (ti != -1 &&
828 MI.getOperand(ti).isReg() &&
828 MI.getOperand(ti).isRegister() &&
829829 MI.getOperand(ti).getReg() == VirtReg) {
830830 // Okay, we have a two address operand. We can reuse this physreg as
831831 // long as we are allowed to clobber the value and there isn't an
6767 default: break;
6868 case ARM::LDR:
6969 if (MI->getOperand(1).isFrameIndex() &&
70 MI->getOperand(2).isReg() &&
70 MI->getOperand(2).isRegister() &&
7171 MI->getOperand(3).isImmediate() &&
7272 MI->getOperand(2).getReg() == 0 &&
7373 MI->getOperand(3).getImmedValue() == 0) {
101101 default: break;
102102 case ARM::STR:
103103 if (MI->getOperand(1).isFrameIndex() &&
104 MI->getOperand(2).isReg() &&
104 MI->getOperand(2).isRegister() &&
105105 MI->getOperand(3).isImmediate() &&
106106 MI->getOperand(2).getReg() == 0 &&
107107 MI->getOperand(3).getImmedValue() == 0) {
520520 bool Found = false;
521521 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
522522 const MachineOperand &MO = MI->getOperand(i);
523 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
523 if (MO.isRegister() && MO.getReg() == ARM::CPSR) {
524524 Pred.push_back(MO);
525525 Found = true;
526526 }
449449 case 'I':
450450 // Write 'i' if an integer constant, otherwise nothing. Used to print
451451 // addi vs add, etc.
452 if (MI->getOperand(OpNo).isImm())
452 if (MI->getOperand(OpNo).isImmediate())
453453 O << "i";
454454 return false;
455455 }
128128 unsigned MBBStartOffset = 0;
129129 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
130130 I != E; ++I) {
131 if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) {
131 if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImmediate()) {
132132 MBBStartOffset += getNumBytesForInstruction(I);
133133 continue;
134134 }
6767 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
6868 if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
6969 MachineOperand &MO = MI->getOperand(i);
70 if (MO.isReg()) {
70 if (MO.isRegister()) {
7171 MO.setReg(Pred[j].getReg());
7272 MadeChange = true;
73 } else if (MO.isImm()) {
73 } else if (MO.isImmediate()) {
7474 MO.setImm(Pred[j].getImmedValue());
7575 MadeChange = true;
76 } else if (MO.isMBB()) {
76 } else if (MO.isMachineBasicBlock()) {
7777 MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
7878 MadeChange = true;
7979 }
546546 case 'h': // Print QImode high register
547547 case 'w': // Print HImode register
548548 case 'k': // Print SImode register
549 if (MI->getOperand(OpNo).isReg())
549 if (MI->getOperand(OpNo).isRegister())
550550 return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
551551 printOperand(MI, OpNo);
552552 return false;
219219 SmallVector DeadRegs;
220220 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
221221 const MachineOperand &MO = MI->getOperand(i);
222 if (MO.isReg() && MO.isDead())
222 if (MO.isRegister() && MO.isDead())
223223 DeadRegs.push_back(MO.getReg());
224224 }
225225
290290
291291 static const MachineInstrBuilder &FuseInstrAddOperand(MachineInstrBuilder &MIB,
292292 MachineOperand &MO) {
293 if (MO.isReg())
293 if (MO.isRegister())
294294 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
295 else if (MO.isImm())
295 else if (MO.isImmediate())
296296 MIB = MIB.addImm(MO.getImm());
297297 else if (MO.isFrameIndex())
298298 MIB = MIB.addFrameIndex(MO.getFrameIndex());
339339 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
340340 MachineOperand &MO = MI->getOperand(i);
341341 if (i == OpNo) {
342 assert(MO.isReg() && "Expected to fold into reg operand!");
342 assert(MO.isRegister() && "Expected to fold into reg operand!");
343343 unsigned NumAddrOps = MOs.size();
344344 for (unsigned i = 0; i != NumAddrOps; ++i)
345345 MIB = FuseInstrAddOperand(MIB, MOs[i]);
439439 // instruction is different than folding it other places. It requires
440440 // replacing the *two* registers with the memory location.
441441 if (isTwoAddr && NumOps >= 2 && i < 2 &&
442 MI->getOperand(0).isReg() &&
443 MI->getOperand(1).isReg() &&
442 MI->getOperand(0).isRegister() &&
443 MI->getOperand(1).isRegister() &&
444444 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
445445 static const TableEntry OpcodeTable[] = {
446446 { X86::ADC32ri, X86::ADC32mi },
15271527 if (RetOpcode == X86::EH_RETURN) {
15281528 MBBI = prior(MBB.end());
15291529 MachineOperand &DestAddr = MBBI->getOperand(0);
1530 assert(DestAddr.isReg() && "Offset should be in register!");
1530 assert(DestAddr.isRegister() && "Offset should be in register!");
15311531 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
15321532 addReg(DestAddr.getReg());
15331533 }