llvm.org GIT mirror llvm / 928bfce
Merging r231259: ------------------------------------------------------------------------ r231259 | marek.olsak | 2015-03-04 12:33:45 -0500 (Wed, 04 Mar 2015) | 4 lines R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32 Required by OpenGL (ARB_gpu_shader5). ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@236263 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
4 changed file(s) with 35 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
6767 def int_AMDGPU_bfe_u32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
6868 def int_AMDGPU_bfm : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
6969 def int_AMDGPU_brev : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
70 def int_AMDGPU_flbit_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
7071 def int_AMDGPU_barrier_local : Intrinsic<[], [], []>;
7172 def int_AMDGPU_barrier_global : Intrinsic<[], [], []>;
7273 }
12941294 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
12951295 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
12961296 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1297 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
12971298 }
12981299 }
12991300
151151 [(set i32:$dst, (ctlz_zero_undef i32:$src0))]
152152 >;
153153
154 //defm S_FLBIT_I32_B64 : SOP1_32 , "s_flbit_i32_b64", []>;
155 defm S_FLBIT_I32 : SOP1_32 , "s_flbit_i32", []>;
156 //defm S_FLBIT_I32_I64 : SOP1_32 , "s_flbit_i32_i64", []>;
154 defm S_FLBIT_I32_B64 : SOP1_32_64 , "s_flbit_i32_b64", []>;
155 defm S_FLBIT_I32 : SOP1_32 , "s_flbit_i32",
156 [(set i32:$dst, (int_AMDGPU_flbit_i32 i32:$src0))]
157 >;
158 defm S_FLBIT_I32_I64 : SOP1_32_64 , "s_flbit_i32_i64", []>;
157159 defm S_SEXT_I32_I8 : SOP1_32 , "s_sext_i32_i8",
158160 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
159161 >;
0 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
1 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2
3 declare i32 @llvm.AMDGPU.flbit.i32(i32) nounwind readnone
4
5 ; FUNC-LABEL: {{^}}s_flbit:
6 ; SI: s_load_dword [[VAL:s[0-9]+]],
7 ; SI: s_flbit_i32 [[SRESULT:s[0-9]+]], [[VAL]]
8 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
9 ; SI: buffer_store_dword [[VRESULT]],
10 ; SI: s_endpgm
11 define void @s_flbit(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
12 %r = call i32 @llvm.AMDGPU.flbit.i32(i32 %val) nounwind readnone
13 store i32 %r, i32 addrspace(1)* %out, align 4
14 ret void
15 }
16
17 ; FUNC-LABEL: {{^}}v_flbit:
18 ; SI: buffer_load_dword [[VAL:v[0-9]+]],
19 ; SI: v_ffbh_i32_e32 [[RESULT:v[0-9]+]], [[VAL]]
20 ; SI: buffer_store_dword [[RESULT]],
21 ; SI: s_endpgm
22 define void @v_flbit(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
23 %val = load i32 addrspace(1)* %valptr, align 4
24 %r = call i32 @llvm.AMDGPU.flbit.i32(i32 %val) nounwind readnone
25 store i32 %r, i32 addrspace(1)* %out, align 4
26 ret void
27 }