llvm.org GIT mirror llvm / 928b930
AMDGPU: Use appropriate soffset for spilling This needs to be the frame offset register, and not the global scratch wave offset register. For kernels, these are the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303287 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 3 years ago
2 changed file(s) with 20 addition(s) and 20 deletion(s). Raw diff Collapse all Expand all
764764 .addFrameIndex(FrameIndex) // addr
765765 .addMemOperand(MMO)
766766 .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
767 .addReg(MFI->getScratchWaveOffsetReg(), RegState::Implicit);
767 .addReg(MFI->getFrameOffsetReg(), RegState::Implicit);
768768 // Add the scratch resource registers as implicit uses because we may end up
769769 // needing them, and need to ensure that the reserved registers are
770770 // correctly handled.
795795 .addReg(SrcReg, getKillRegState(isKill)) // data
796796 .addFrameIndex(FrameIndex) // addr
797797 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
798 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
798 .addReg(MFI->getFrameOffsetReg()) // scratch_offset
799799 .addImm(0) // offset
800800 .addMemOperand(MMO);
801801 }
868868 .addFrameIndex(FrameIndex) // addr
869869 .addMemOperand(MMO)
870870 .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
871 .addReg(MFI->getScratchWaveOffsetReg(), RegState::Implicit);
871 .addReg(MFI->getFrameOffsetReg(), RegState::Implicit);
872872
873873 if (ST.hasScalarStores()) {
874874 // m0 is used for offset to scalar stores if used to spill.
891891
892892 unsigned Opcode = getVGPRSpillRestoreOpcode(SpillSize);
893893 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
894 .addFrameIndex(FrameIndex) // vaddr
895 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
896 .addReg(MFI->getScratchWaveOffsetReg()) // scratch_offset
897 .addImm(0) // offset
894 .addFrameIndex(FrameIndex) // vaddr
895 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
896 .addReg(MFI->getFrameOffsetReg()) // scratch_offset
897 .addImm(0) // offset
898898 .addMemOperand(MMO);
899899 }
900900
653653 int64_t Offset = (ST.getWavefrontSize() * FrOffset) + (EltSize * i);
654654 if (Offset != 0) {
655655 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), OffsetReg)
656 .addReg(MFI->getScratchWaveOffsetReg())
656 .addReg(MFI->getFrameOffsetReg())
657657 .addImm(Offset);
658658 } else {
659659 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
660 .addReg(MFI->getScratchWaveOffsetReg());
660 .addReg(MFI->getFrameOffsetReg());
661661 }
662662
663663 BuildMI(*MBB, MI, DL, TII->get(ScalarStoreOp))
714714 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
715715 EltSize, MinAlign(Align, EltSize * i));
716716 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE))
717 .addReg(TmpReg, RegState::Kill) // src
718 .addFrameIndex(Index) // vaddr
719 .addReg(MFI->getScratchRSrcReg()) // srrsrc
720 .addReg(MFI->getScratchWaveOffsetReg()) // soffset
721 .addImm(i * 4) // offset
717 .addReg(TmpReg, RegState::Kill) // src
718 .addFrameIndex(Index) // vaddr
719 .addReg(MFI->getScratchRSrcReg()) // srrsrc
720 .addReg(MFI->getFrameOffsetReg()) // soffset
721 .addImm(i * 4) // offset
722722 .addMemOperand(MMO);
723723 }
724724 }
805805 int64_t Offset = (ST.getWavefrontSize() * FrOffset) + (EltSize * i);
806806 if (Offset != 0) {
807807 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), OffsetReg)
808 .addReg(MFI->getScratchWaveOffsetReg())
808 .addReg(MFI->getFrameOffsetReg())
809809 .addImm(Offset);
810810 } else {
811811 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
812 .addReg(MFI->getScratchWaveOffsetReg());
812 .addReg(MFI->getFrameOffsetReg());
813813 }
814814
815815 auto MIB =
852852 MinAlign(Align, EltSize * i));
853853
854854 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg)
855 .addFrameIndex(Index) // vaddr
856 .addReg(MFI->getScratchRSrcReg()) // srsrc
857 .addReg(MFI->getScratchWaveOffsetReg()) // soffset
858 .addImm(i * 4) // offset
855 .addFrameIndex(Index) // vaddr
856 .addReg(MFI->getScratchRSrcReg()) // srsrc
857 .addReg(MFI->getFrameOffsetReg()) // soffset
858 .addImm(i * 4) // offset
859859 .addMemOperand(MMO);
860860
861861 auto MIB =