llvm.org GIT mirror llvm / 923a400
AMDGPU: Assembler support for exp compr is not currently parsed (or printed) correctly, but that should probably be fixed along with intrinsic changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288698 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 3 years ago
5 changed file(s) with 403 addition(s) and 29 deletion(s). Raw diff Collapse all Expand all
134134 ImmTyDA,
135135 ImmTyR128,
136136 ImmTyLWE,
137 ImmTyExpTgt,
137138 ImmTyExpCompr,
138139 ImmTyExpVM,
139140 ImmTyHwreg,
141 ImmTyOff,
140142 ImmTySendMsg,
141143 };
142144
212214
213215 bool isRegOrImmWithFP64InputMods() const {
214216 return isRegOrImmWithInputMods(MVT::f64);
217 }
218
219 bool isVReg32OrOff() const {
220 return isOff() || isRegClass(AMDGPU::VGPR_32RegClassID);
215221 }
216222
217223 bool isImmTy(ImmTy ImmT) const {
229235 bool isDA() const { return isImmTy(ImmTyDA); }
230236 bool isR128() const { return isImmTy(ImmTyUNorm); }
231237 bool isLWE() const { return isImmTy(ImmTyLWE); }
238 bool isOff() const { return isImmTy(ImmTyOff); }
239 bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }
232240 bool isExpVM() const { return isImmTy(ImmTyExpVM); }
233241 bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }
234242 bool isOffen() const { return isImmTy(ImmTyOffen); }
459467 }
460468 }
461469
462 void printImmTy(raw_ostream& OS, ImmTy Type) const {
470 static void printImmTy(raw_ostream& OS, ImmTy Type) {
463471 switch (Type) {
464472 case ImmTyNone: OS << "None"; break;
465473 case ImmTyGDS: OS << "GDS"; break;
487495 case ImmTyDA: OS << "DA"; break;
488496 case ImmTyR128: OS << "R128"; break;
489497 case ImmTyLWE: OS << "LWE"; break;
498 case ImmTyOff: OS << "Off"; break;
499 case ImmTyExpTgt: OS << "ExpTgt"; break;
490500 case ImmTyExpCompr: OS << "ExpCompr"; break;
491501 case ImmTyExpVM: OS << "ExpVM"; break;
492502 case ImmTyHwreg: OS << "Hwreg"; break;
712722 OperandMatchResultTy parseRegOrImm(OperandVector &Operands);
713723 OperandMatchResultTy parseRegOrImmWithFPInputMods(OperandVector &Operands);
714724 OperandMatchResultTy parseRegOrImmWithIntInputMods(OperandVector &Operands);
725 OperandMatchResultTy parseVReg32OrOff(OperandVector &Operands);
715726
716727 void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
717728 void cvtDS(MCInst &Inst, const OperandVector &Operands);
729 void cvtExp(MCInst &Inst, const OperandVector &Operands);
718730
719731 bool parseCnt(int64_t &IntVal);
720732 OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
729741
730742 bool parseSendMsgConstruct(OperandInfoTy &Msg, OperandInfoTy &Operation, int64_t &StreamId);
731743 bool parseHwregConstruct(OperandInfoTy &HwReg, int64_t &Offset, int64_t &Width);
744
745 void errorExpTgt();
746 OperandMatchResultTy parseExpTgtImpl(StringRef Str, uint8_t &Val);
747
732748 public:
733749 OperandMatchResultTy parseOptionalOperand(OperandVector &Operands);
734750
751 OperandMatchResultTy parseExpTgt(OperandVector &Operands);
735752 OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
736753 OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
737754
750767 AMDGPUOperand::Ptr defaultSMRDOffset8() const;
751768 AMDGPUOperand::Ptr defaultSMRDOffset20() const;
752769 AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
770 AMDGPUOperand::Ptr defaultExpTgt() const;
753771 AMDGPUOperand::Ptr defaultExpCompr() const;
754772 AMDGPUOperand::Ptr defaultExpVM() const;
755773
13571375 AMDGPUOperand &Op = static_cast(*Operands.back());
13581376 Op.setModifiers(Mods);
13591377 }
1378
13601379 return MatchOperand_Success;
1380 }
1381
1382 OperandMatchResultTy AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {
1383 std::unique_ptr Reg = parseRegister();
1384 if (Reg) {
1385 Operands.push_back(std::move(Reg));
1386 return MatchOperand_Success;
1387 }
1388
1389 const AsmToken &Tok = Parser.getTok();
1390 if (Tok.getString() == "off") {
1391 Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Tok.getLoc(),
1392 AMDGPUOperand::ImmTyOff, false));
1393 Parser.Lex();
1394 return MatchOperand_Success;
1395 }
1396
1397 return MatchOperand_NoMatch;
13611398 }
13621399
13631400 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
19992036 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
20002037 }
20012038
2039 void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
2040 OptionalImmIndexMap OptionalIdx;
2041
2042 unsigned EnMask = 0;
2043 int SrcIdx = 0;
2044
2045 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
2046 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
2047
2048 // Add the register arguments
2049 if (Op.isReg()) {
2050 EnMask |= (1 << SrcIdx);
2051 Op.addRegOperands(Inst, 1);
2052 ++SrcIdx;
2053 continue;
2054 }
2055
2056 if (Op.isOff()) {
2057 ++SrcIdx;
2058 Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));
2059 continue;
2060 }
2061
2062 if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyExpTgt) {
2063 Op.addImmOperands(Inst, 1);
2064 continue;
2065 }
2066
2067 if (Op.isToken() && Op.getToken() == "done")
2068 continue;
2069
2070 // Handle optional arguments
2071 OptionalIdx[Op.getImmTy()] = i;
2072 }
2073
2074 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);
2075 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);
2076
2077 Inst.addOperand(MCOperand::createImm(EnMask));
2078 }
20022079
20032080 //===----------------------------------------------------------------------===//
20042081 // s_waitcnt
22712348 return true;
22722349 Parser.Lex();
22732350 return false;
2351 }
2352
2353 void AMDGPUAsmParser::errorExpTgt() {
2354 Error(Parser.getTok().getLoc(), "invalid exp target");
2355 }
2356
2357 OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str,
2358 uint8_t &Val) {
2359 if (Str == "null") {
2360 Val = 9;
2361 return MatchOperand_Success;
2362 }
2363
2364 if (Str.startswith("mrt")) {
2365 Str = Str.drop_front(3);
2366 if (Str == "z") { // == mrtz
2367 Val = 8;
2368 return MatchOperand_Success;
2369 }
2370
2371 if (Str.getAsInteger(10, Val))
2372 return MatchOperand_ParseFail;
2373
2374 if (Val > 7)
2375 errorExpTgt();
2376
2377 return MatchOperand_Success;
2378 }
2379
2380 if (Str.startswith("pos")) {
2381 Str = Str.drop_front(3);
2382 if (Str.getAsInteger(10, Val))
2383 return MatchOperand_ParseFail;
2384
2385 if (Val > 3)
2386 errorExpTgt();
2387
2388 Val += 12;
2389 return MatchOperand_Success;
2390 }
2391
2392 if (Str.startswith("param")) {
2393 Str = Str.drop_front(5);
2394 if (Str.getAsInteger(10, Val))
2395 return MatchOperand_ParseFail;
2396
2397 if (Val >= 32)
2398 errorExpTgt();
2399
2400 Val += 32;
2401 return MatchOperand_Success;
2402 }
2403
2404 if (Str.startswith("invalid_target_")) {
2405 Str = Str.drop_front(15);
2406 if (Str.getAsInteger(10, Val))
2407 return MatchOperand_ParseFail;
2408
2409 errorExpTgt();
2410 return MatchOperand_Success;
2411 }
2412
2413 return MatchOperand_NoMatch;
2414 }
2415
2416 OperandMatchResultTy AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {
2417 uint8_t Val;
2418 StringRef Str = Parser.getTok().getString();
2419
2420 auto Res = parseExpTgtImpl(Str, Val);
2421 if (Res != MatchOperand_Success)
2422 return Res;
2423
2424 SMLoc S = Parser.getTok().getLoc();
2425 Parser.Lex();
2426
2427 Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S,
2428 AMDGPUOperand::ImmTyExpTgt));
2429 return MatchOperand_Success;
22742430 }
22752431
22762432 OperandMatchResultTy
25382694 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyLWE);
25392695 }
25402696
2697 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultExpTgt() const {
2698 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyExpTgt);
2699 }
2700
25412701 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultExpCompr() const {
25422702 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyExpCompr);
25432703 }
26422802 {"src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel, false, nullptr},
26432803 {"src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel, false, nullptr},
26442804 {"dst_unused", AMDGPUOperand::ImmTySdwaDstUnused, false, nullptr},
2805 {"vm", AMDGPUOperand::ImmTyExpVM, true, nullptr},
26452806 };
26462807
26472808 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {
31243285 return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand;
31253286 case MCK_SoppBrTarget:
31263287 return Operand.isSoppBrTarget() ? Match_Success : Match_InvalidOperand;
3127 default: return Match_InvalidOperand;
3128 }
3129 }
3288 case MCK_VReg32OrOff:
3289 return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;
3290 default:
3291 return Match_InvalidOperand;
3292 }
3293 }
314314 let RenderMethod = "addImmOperands";
315315 }
316316
317 def ExpTgtMatchClass : AsmOperandClass {
318 let Name = "ExpTgt";
319 let PredicateMethod = "isExpTgt";
320 let ParserMethod = "parseExpTgt";
321 let RenderMethod = "printExpTgt";
322 }
323
317324 def SendMsgImm : Operand {
318325 let PrintMethod = "printSendMsg";
319326 let ParserMatchClass = SendMsgMatchClass;
325332 let ParserMethod = "parseSWaitCntOps";
326333 }
327334
335 def VReg32OrOffClass : AsmOperandClass {
336 let Name = "VReg32OrOff";
337 let ParserMethod = "parseVReg32OrOff";
338 }
339
328340 def WAIT_FLAG : Operand {
329341 let ParserMatchClass = SWaitMatchClass;
330342 let PrintMethod = "printWaitFlag";
332344
333345 include "SIInstrFormats.td"
334346 include "VIInstrFormats.td"
347
348 // ===----------------------------------------------------------------------===//
349 // ExpSrc* Special cases for exp src operands which are printed as
350 // "off" depending on en operand.
351 // ===----------------------------------------------------------------------===//
352
353 def ExpSrc0 : RegisterOperand {
354 let PrintMethod = "printExpSrc0";
355 let ParserMatchClass = VReg32OrOffClass;
356 }
357
358 def ExpSrc1 : RegisterOperand {
359 let PrintMethod = "printExpSrc1";
360 let ParserMatchClass = VReg32OrOffClass;
361 }
362
363 def ExpSrc2 : RegisterOperand {
364 let PrintMethod = "printExpSrc2";
365 let ParserMatchClass = VReg32OrOffClass;
366 }
367
368 def ExpSrc3 : RegisterOperand {
369 let PrintMethod = "printExpSrc3";
370 let ParserMatchClass = VReg32OrOffClass;
371 }
335372
336373 class NamedMatchClass : AsmOperandClass {
337374 let Name = "Imm"#CName;
401438
402439 def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
403440
404 def exp_tgt : Operand {
405 let PrintMethod = "printExpTgt";
441 def exp_tgt : NamedOperandU8<"ExpTgt", NamedMatchClass<"ExpTgt", 0>> {
442
406443 }
407444
408445 } // End OperandType = "OPERAND_IMMEDIATE"
530567 exp_vm:$vm, exp_compr:$compr, i8imm:$en),
531568 "exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")#"$compr$vm",
532569 [(node (i8 timm:$en), (i1 timm:$vm), (i8 timm:$tgt), (i1 timm:$compr),
533 f32:$src0, f32:$src1, f32:$src2, f32:$src3)]
534 >;
570 f32:$src0, f32:$src1, f32:$src2, f32:$src3)]> {
571 let AsmMatchConverter = "cvtExp";
572 }
535573
536574 // Split EXP instruction into EXP and EXP_DONE so we can set
537575 // mayLoad for done=1.
448448 //===----------------------------------------------------------------------===//
449449
450450 defm VCSrc : RegInlineOperand<"VS", "VCSrc">;
451
452 // ===----------------------------------------------------------------------===//
453 // ExpSrc* Special cases for exp src operands which are printed as
454 // "off" depending on en operand.
455 // ===----------------------------------------------------------------------===//
456
457 def ExpSrc0 : RegisterOperand {
458 let PrintMethod = "printExpSrc0";
459 }
460
461 def ExpSrc1 : RegisterOperand {
462 let PrintMethod = "printExpSrc1";
463 }
464
465 def ExpSrc2 : RegisterOperand {
466 let PrintMethod = "printExpSrc2";
467 }
468
469 def ExpSrc3 : RegisterOperand {
470 let PrintMethod = "printExpSrc3";
471 }
0 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
1 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
2
3 exp mrt8 v3, v2, v1, v0
4 // GCN: :5: error: invalid exp target
5
6 exp pos4 v3, v2, v1, v0
7 // GCN: :5: error: invalid exp target
8
9 exp param32 v3, v2, v1, v0
10 // GCN: :5: error: invalid exp target
11
12 exp invalid_target_10 v3, v2, v1, v0
13 // GCN: :5: error: invalid exp target
14
15 exp invalid_target_10 v3, v2, v1, v0 done
16 // GCN: :5: error: invalid exp target
17
18 exp invalid_target_11 v3, v2, v1, v0
19 // GCN: :5: error: invalid exp target
20
21 exp invalid_target_11 v3, v2, v1, v0 done
22 // GCN: :5: error: invalid exp target
23
24 exp mrt-1 v3, v2, v1, v0
25 // GCN: :5: error: failed parsing operand
26
27 exp mrtX v3, v2, v1, v0
28 // GCN: :5: error: failed parsing operand
29
30 exp pos-1 v3, v2, v1, v0
31 // GCN: :5: error: failed parsing operand
32
33 exp posX v3, v2, v1, v0
34 // GCN: :5: error: failed parsing operand
35
36 exp param-1 v3, v2, v1, v0
37 // GCN: :5: error: failed parsing operand
38
39 exp paramX v3, v2, v1, v0
40 // GCN: :5: error: failed parsing operand
41
42 exp invalid_target_-1 v3, v2, v1, v0
43 // GCN: :5: error: failed parsing operand
44
45 exp invalid_target_X v3, v2, v1, v0
46 // GCN: :5: error: failed parsing operand
47
48 exp mrt0 s0, v0, v0, v0
49 // GCN: 10: error: invalid operand for instruction
50
51 exp mrt0 v0, s0, v0, v0
52 // GCN: 14: error: invalid operand for instruction
53
54 exp mrt0 v0, v0, s0, v0
55 // GCN: 18: error: invalid operand for instruction
56
57 exp mrt0 v0, v0, v0, s0
58 // GCN: 22: error: invalid operand for instruction
59
60 exp mrt0 v[0:1], v0, v0, v0
61 // GCN: 10: error: invalid operand for instruction
62
63 exp mrt0 v0, v[0:1], v0, v0
64 // GCN: 14: error: invalid operand for instruction
65
66 exp mrt0 v0, v0, v[0:1], v0
67 // GCN: 18: error: invalid operand for instruction
68
69 exp mrt0 v0, v0, v0, v[0:1]
70 // GCN: 22: error: invalid operand for instruction
71
72 exp mrt0 1.0, v0, v0, v0
73 // GCN: 10: error: invalid operand for instruction
74
75 exp mrt0 v0, 1.0, v0, v0
76 // GCN: 14: error: invalid operand for instruction
77
78 exp mrt0 v0, v0, 1.0, v0
79 // GCN: 18: error: invalid operand for instruction
80
81 exp mrt0 v0, v0, v0, 1.0
82 // GCN: 22: error: invalid operand for instruction
83
84 exp mrt0 7, v0, v0, v0
85 // GCN: 10: error: invalid operand for instruction
86
87 exp mrt0 v0, 7, v0, v0
88 // GCN: 14: error: invalid operand for instruction
89
90 exp mrt0 v0, v0, 7, v0
91 // GCN: 18: error: invalid operand for instruction
92
93 exp mrt0 v0, v0, v0, 7
94 // GCN: 22: error: invalid operand for instruction
95
96 exp mrt0 0x12345678, v0, v0, v0
97 // GCN: 10: error: invalid operand for instruction
98
99 exp mrt0 v0, 0x12345678, v0, v0
100 // GCN: 14: error: invalid operand for instruction
101
102 exp mrt0 v0, v0, 0x12345678, v0
103 // GCN: 18: error: invalid operand for instruction
104
105 exp mrt0 v0, v0, v0, 0x12345678
106 // GCN: 22: error: invalid operand for instruction
0 // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
1 // RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2
3 exp mrt0 off, off, off, off
4 // GCN: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
5
6 exp mrt0 off, off, off, off done
7 // GCN: exp mrt0 off, off, off, off done ; encoding: [0x00,0x08,0x00,0xf8,0x00,0x00,0x00,0x00]
8
9 exp mrt0 v4, off, off, off done
10 // GCN: exp mrt0 v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xf8,0x04,0x00,0x00,0x00]
11
12 exp mrt0 off, v3, off, off done
13 // GCN: exp mrt0 off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xf8,0x00,0x03,0x00,0x00]
14
15 exp mrt0 off, off, v2, off done
16 // GCN: exp mrt0 off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xf8,0x00,0x00,0x02,0x00]
17
18 exp mrt0 off, off, off, v1 done
19 // GCN: exp mrt0 off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xf8,0x00,0x00,0x00,0x01]
20
21 exp mrt0 v4, v3, off, off done
22 // GCN: exp mrt0 v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xf8,0x04,0x03,0x00,0x00]
23
24 exp mrt0 v4, off, v2, off done
25 // GCN: exp mrt0 v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xf8,0x04,0x00,0x02,0x00]
26
27 exp mrt0 v4, off, off, v1
28 // GCN: exp mrt0 v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xf8,0x04,0x00,0x00,0x01]
29
30 exp mrt0 v4, off, off, v1 done
31 // GCN: exp mrt0 v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xf8,0x04,0x00,0x00,0x01]
32
33 exp mrt0 v4, v3, v2, v1
34 // GCN: exp mrt0 v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
35
36 exp mrt0 v4, v3, v2, v1 done
37 // GCN: exp mrt0 v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
38
39 exp mrt7 v1, v1, v1, v1
40 // GCN: exp mrt7 v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xf8,0x01,0x01,0x01,0x01]
41
42 exp mrt7 v1, v1, v1, v1 done
43 // GCN: exp mrt7 v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xf8,0x01,0x01,0x01,0x01]
44
45 exp mrtz v4, v3, v2, v1
46 // GCN: exp mrtz v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
47
48 exp mrtz v4, v3, v2, v1 done
49 // GCN: exp mrtz v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
50
51 exp null v4, v3, v2, v1
52 // GCN: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
53
54 exp null v4, v3, v2, v1 done
55 // GCN: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
56
57 exp pos0 v4, v3, v2, v1
58 // GCN: exp pos0 v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
59
60 exp pos0 v4, v3, v2, v1 done
61 // GCN: exp pos0 v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
62
63 exp pos3 v4, v3, v2, v1
64 // GCN: exp pos3 v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xf8,0x04,0x03,0x02,0x01]
65
66 exp pos3 v4, v3, v2, v1 done
67 // GCN: exp pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01]
68
69 exp param0 v4, v3, v2, v1
70 // GCN: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xf8,0x04,0x03,0x02,0x01]
71
72 exp param0 v4, v3, v2, v1 done
73 // GCN: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x04,0x03,0x02,0x01]
74
75 exp param31 v4, v3, v2, v1
76 // GCN: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xf8,0x04,0x03,0x02,0x01]
77
78 exp param31 v4, v3, v2, v1 done
79 // GCN: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xf8,0x04,0x03,0x02,0x01]
80
81 exp mrt0 v4, v3, v2, v1 vm
82 // GCN: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01]
83
84 exp mrt0 v4, v3, v2, v1 done vm
85 // GCN: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01]