llvm.org GIT mirror llvm / 922d314
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 7 years ago
53 changed file(s) with 1125 addition(s) and 595 deletion(s). Raw diff Collapse all Expand all
119119 // X86 processors supported.
120120 //===----------------------------------------------------------------------===//
121121
122 include "X86Schedule.td"
123
124 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
125 "Intel Atom processors">;
126
122127 class Proc Features>
123 : ProcessorNoItineraries, Features>;
128 : ProcessorGenericItineraries, Features>;
129
130 class AtomProc Features>
131 : Processor;
124132
125133 def : Proc<"generic", []>;
126134 def : Proc<"i386", []>;
145153 FeatureSlowBTMem]>;
146154 def : Proc<"penryn", [FeatureSSE41, FeatureCMPXCHG16B,
147155 FeatureSlowBTMem]>;
148 def : Proc<"atom", [FeatureSSE3, FeatureCMPXCHG16B, FeatureMOVBE,
149 FeatureSlowBTMem]>;
156 def : AtomProc<"atom", [ProcIntelAtom, FeatureSSE3, FeatureCMPXCHG16B,
157 FeatureMOVBE, FeatureSlowBTMem]>;
150158 // "Arrandale" along with corei3 and corei5
151159 def : Proc<"corei7", [FeatureSSE42, FeatureCMPXCHG16B,
152160 FeatureSlowBTMem, FeatureFastUAMem,
178178
179179 // For 64-bit since we have so many registers use the ILP scheduler, for
180180 // 32-bit code use the register pressure specific scheduling.
181 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
181182 if (Subtarget->is64Bit())
182183 setSchedulingPreference(Sched::ILP);
184 else if (Subtarget->isAtom())
185 setSchedulingPreference(Sched::Hybrid);
183186 else
184187 setSchedulingPreference(Sched::RegPressure);
185188 setStackPointerRegisterToSaveRestore(X86StackPtr);
1717 let neverHasSideEffects = 1 in
1818 def LEA16r : I<0x8D, MRMSrcMem,
1919 (outs GR16:$dst), (ins i32mem:$src),
20 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
20 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize;
2121 let isReMaterializable = 1 in
2222 def LEA32r : I<0x8D, MRMSrcMem,
2323 (outs GR32:$dst), (ins i32mem:$src),
2424 "lea{l}\t{$src|$dst}, {$dst|$src}",
25 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
25 [(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
26 Requires<[In32BitMode]>;
2627
2728 def LEA64_32r : I<0x8D, MRMSrcMem,
2829 (outs GR32:$dst), (ins lea64_32mem:$src),
2930 "lea{l}\t{$src|$dst}, {$dst|$src}",
30 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
31 [(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
32 Requires<[In64BitMode]>;
3133
3234 let isReMaterializable = 1 in
3335 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
3436 "lea{q}\t{$src|$dst}, {$dst|$src}",
35 [(set GR64:$dst, lea64addr:$src)]>;
37 [(set GR64:$dst, lea64addr:$src)], IIC_LEA>;
3638
3739
3840
5557 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
5658 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
5759 "mul{w}\t$src",
58 []>, OpSize; // AX,DX = AX*GR16
60 [], IIC_MUL16_REG>, OpSize; // AX,DX = AX*GR16
5961
6062 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
6163 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
6264 "mul{l}\t$src", // EAX,EDX = EAX*GR32
63 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/]>;
65 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
66 IIC_MUL32_REG>;
6467 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
6568 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
6669 "mul{q}\t$src", // RAX,RDX = RAX*GR64
67 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>;
70 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
71 IIC_MUL64>;
6872
6973 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
7074 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
7377 // This probably ought to be moved to a def : Pat<> if the
7478 // syntax can be accepted.
7579 [(set AL, (mul AL, (loadi8 addr:$src))),
76 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
80 (implicit EFLAGS)], IIC_MUL8>; // AL,AH = AL*[mem8]
7781
7882 let mayLoad = 1, neverHasSideEffects = 1 in {
7983 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
8084 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
8185 "mul{w}\t$src",
82 []>, OpSize; // AX,DX = AX*[mem16]
86 [], IIC_MUL16_MEM>, OpSize; // AX,DX = AX*[mem16]
8387
8488 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
8589 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
8690 "mul{l}\t$src",
87 []>; // EAX,EDX = EAX*[mem32]
91 [], IIC_MUL32_MEM>; // EAX,EDX = EAX*[mem32]
8892 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
8993 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
90 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
94 "mul{q}\t$src", [], IIC_MUL64>; // RAX,RDX = RAX*[mem64]
9195 }
9296
9397 let neverHasSideEffects = 1 in {
129133 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
130134 "imul{w}\t{$src2, $dst|$dst, $src2}",
131135 [(set GR16:$dst, EFLAGS,
132 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
136 (X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>,
137 TB, OpSize;
133138 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
134139 "imul{l}\t{$src2, $dst|$dst, $src2}",
135140 [(set GR32:$dst, EFLAGS,
136 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
141 (X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,
142 TB;
137143 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
138144 (ins GR64:$src1, GR64:$src2),
139145 "imul{q}\t{$src2, $dst|$dst, $src2}",
140146 [(set GR64:$dst, EFLAGS,
141 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
147 (X86smul_flag GR64:$src1, GR64:$src2))], IIC_IMUL64_RR>,
148 TB;
142149 }
143150
144151 // Register-Memory Signed Integer Multiply
146153 (ins GR16:$src1, i16mem:$src2),
147154 "imul{w}\t{$src2, $dst|$dst, $src2}",
148155 [(set GR16:$dst, EFLAGS,
149 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
156 (X86smul_flag GR16:$src1, (load addr:$src2)))],
157 IIC_IMUL16_RM>,
150158 TB, OpSize;
151159 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
152160 (ins GR32:$src1, i32mem:$src2),
153161 "imul{l}\t{$src2, $dst|$dst, $src2}",
154162 [(set GR32:$dst, EFLAGS,
155 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
163 (X86smul_flag GR32:$src1, (load addr:$src2)))],
164 IIC_IMUL32_RM>,
165 TB;
156166 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
157167 (ins GR64:$src1, i64mem:$src2),
158168 "imul{q}\t{$src2, $dst|$dst, $src2}",
159169 [(set GR64:$dst, EFLAGS,
160 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
170 (X86smul_flag GR64:$src1, (load addr:$src2)))],
171 IIC_IMUL64_RM>,
172 TB;
161173 } // Constraints = "$src1 = $dst"
162174
163175 } // Defs = [EFLAGS]
169181 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
170182 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
171183 [(set GR16:$dst, EFLAGS,
172 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
184 (X86smul_flag GR16:$src1, imm:$src2))],
185 IIC_IMUL16_RRI>, OpSize;
173186 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
174187 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
175188 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
176189 [(set GR16:$dst, EFLAGS,
177 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
190 (X86smul_flag GR16:$src1, i16immSExt8:$src2))],
191 IIC_IMUL16_RRI>,
178192 OpSize;
179193 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
180194 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
181195 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
182196 [(set GR32:$dst, EFLAGS,
183 (X86smul_flag GR32:$src1, imm:$src2))]>;
197 (X86smul_flag GR32:$src1, imm:$src2))],
198 IIC_IMUL32_RRI>;
184199 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
185200 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
186201 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
187202 [(set GR32:$dst, EFLAGS,
188 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
203 (X86smul_flag GR32:$src1, i32immSExt8:$src2))],
204 IIC_IMUL32_RRI>;
189205 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
190206 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
191207 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
192208 [(set GR64:$dst, EFLAGS,
193 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
209 (X86smul_flag GR64:$src1, i64immSExt32:$src2))],
210 IIC_IMUL64_RRI>;
194211 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
195212 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
196213 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
197214 [(set GR64:$dst, EFLAGS,
198 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
215 (X86smul_flag GR64:$src1, i64immSExt8:$src2))],
216 IIC_IMUL64_RRI>;
199217
200218
201219 // Memory-Integer Signed Integer Multiply
203221 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
204222 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
205223 [(set GR16:$dst, EFLAGS,
206 (X86smul_flag (load addr:$src1), imm:$src2))]>,
224 (X86smul_flag (load addr:$src1), imm:$src2))],
225 IIC_IMUL16_RMI>,
207226 OpSize;
208227 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
209228 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
210229 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
211230 [(set GR16:$dst, EFLAGS,
212231 (X86smul_flag (load addr:$src1),
213 i16immSExt8:$src2))]>, OpSize;
232 i16immSExt8:$src2))], IIC_IMUL16_RMI>,
233 OpSize;
214234 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
215235 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
216236 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217237 [(set GR32:$dst, EFLAGS,
218 (X86smul_flag (load addr:$src1), imm:$src2))]>;
238 (X86smul_flag (load addr:$src1), imm:$src2))],
239 IIC_IMUL32_RMI>;
219240 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
220241 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
221242 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
222243 [(set GR32:$dst, EFLAGS,
223244 (X86smul_flag (load addr:$src1),
224 i32immSExt8:$src2))]>;
245 i32immSExt8:$src2))],
246 IIC_IMUL32_RMI>;
225247 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
226248 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
227249 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228250 [(set GR64:$dst, EFLAGS,
229251 (X86smul_flag (load addr:$src1),
230 i64immSExt32:$src2))]>;
252 i64immSExt32:$src2))],
253 IIC_IMUL64_RMI>;
231254 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
232255 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
233256 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
234257 [(set GR64:$dst, EFLAGS,
235258 (X86smul_flag (load addr:$src1),
236 i64immSExt8:$src2))]>;
259 i64immSExt8:$src2))],
260 IIC_IMUL64_RMI>;
237261 } // Defs = [EFLAGS]
238262
239263
242266 // unsigned division/remainder
243267 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
244268 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
245 "div{b}\t$src", []>;
269 "div{b}\t$src", [], IIC_DIV8_REG>;
246270 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
247271 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
248 "div{w}\t$src", []>, OpSize;
272 "div{w}\t$src", [], IIC_DIV16>, OpSize;
249273 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
250274 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
251 "div{l}\t$src", []>;
275 "div{l}\t$src", [], IIC_DIV32>;
252276 // RDX:RAX/r64 = RAX,RDX
253277 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
254278 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
255 "div{q}\t$src", []>;
279 "div{q}\t$src", [], IIC_DIV64>;
256280
257281 let mayLoad = 1 in {
258282 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
259283 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
260 "div{b}\t$src", []>;
284 "div{b}\t$src", [], IIC_DIV8_MEM>;
261285 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
262286 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
263 "div{w}\t$src", []>, OpSize;
287 "div{w}\t$src", [], IIC_DIV16>, OpSize;
264288 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
265289 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
266 "div{l}\t$src", []>;
290 "div{l}\t$src", [], IIC_DIV32>;
267291 // RDX:RAX/[mem64] = RAX,RDX
268292 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
269293 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
270 "div{q}\t$src", []>;
294 "div{q}\t$src", [], IIC_DIV64>;
271295 }
272296
273297 // Signed division/remainder.
274298 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
275299 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
276 "idiv{b}\t$src", []>;
300 "idiv{b}\t$src", [], IIC_IDIV8>;
277301 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
278302 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
279 "idiv{w}\t$src", []>, OpSize;
303 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
280304 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
281305 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
282 "idiv{l}\t$src", []>;
306 "idiv{l}\t$src", [], IIC_IDIV32>;
283307 // RDX:RAX/r64 = RAX,RDX
284308 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
285309 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
286 "idiv{q}\t$src", []>;
310 "idiv{q}\t$src", [], IIC_IDIV64>;
287311
288312 let mayLoad = 1 in {
289313 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
290314 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
291 "idiv{b}\t$src", []>;
315 "idiv{b}\t$src", [], IIC_IDIV8>;
292316 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
293317 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
294 "idiv{w}\t$src", []>, OpSize;
318 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
295319 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
296320 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
297 "idiv{l}\t$src", []>;
321 "idiv{l}\t$src", [], IIC_IDIV32>;
298322 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
299323 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
300 "idiv{q}\t$src", []>;
324 "idiv{q}\t$src", [], IIC_IDIV64>;
301325 }
302326
303327 //===----------------------------------------------------------------------===//
311335 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
312336 "neg{b}\t$dst",
313337 [(set GR8:$dst, (ineg GR8:$src1)),
314 (implicit EFLAGS)]>;
338 (implicit EFLAGS)], IIC_UNARY_REG>;
315339 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
316340 "neg{w}\t$dst",
317341 [(set GR16:$dst, (ineg GR16:$src1)),
318 (implicit EFLAGS)]>, OpSize;
342 (implicit EFLAGS)], IIC_UNARY_REG>, OpSize;
319343 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
320344 "neg{l}\t$dst",
321345 [(set GR32:$dst, (ineg GR32:$src1)),
322 (implicit EFLAGS)]>;
346 (implicit EFLAGS)], IIC_UNARY_REG>;
323347 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
324348 [(set GR64:$dst, (ineg GR64:$src1)),
325 (implicit EFLAGS)]>;
349 (implicit EFLAGS)], IIC_UNARY_REG>;
326350 } // Constraints = "$src1 = $dst"
327351
328352 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
329353 "neg{b}\t$dst",
330354 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
331 (implicit EFLAGS)]>;
355 (implicit EFLAGS)], IIC_UNARY_MEM>;
332356 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
333357 "neg{w}\t$dst",
334358 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
335 (implicit EFLAGS)]>, OpSize;
359 (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize;
336360 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
337361 "neg{l}\t$dst",
338362 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
339 (implicit EFLAGS)]>;
363 (implicit EFLAGS)], IIC_UNARY_MEM>;
340364 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
341365 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
342 (implicit EFLAGS)]>;
366 (implicit EFLAGS)], IIC_UNARY_MEM>;
343367 } // Defs = [EFLAGS]
344368
345369
350374 let AddedComplexity = 15 in {
351375 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
352376 "not{b}\t$dst",
353 [(set GR8:$dst, (not GR8:$src1))]>;
377 [(set GR8:$dst, (not GR8:$src1))], IIC_UNARY_REG>;
354378 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
355379 "not{w}\t$dst",
356 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
380 [(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize;
357381 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
358382 "not{l}\t$dst",
359 [(set GR32:$dst, (not GR32:$src1))]>;
383 [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>;
360384 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
361 [(set GR64:$dst, (not GR64:$src1))]>;
385 [(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>;
362386 }
363387 } // Constraints = "$src1 = $dst"
364388
365389 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
366390 "not{b}\t$dst",
367 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
391 [(store (not (loadi8 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
368392 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
369393 "not{w}\t$dst",
370 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
394 [(store (not (loadi16 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
395 OpSize;
371396 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
372397 "not{l}\t$dst",
373 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
398 [(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
374399 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
375 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
400 [(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
376401 } // CodeSize
377402
378403 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
381406 let CodeSize = 2 in
382407 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
383408 "inc{b}\t$dst",
384 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
409 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))],
410 IIC_UNARY_REG>;
385411
386412 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
387413 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
388414 "inc{w}\t$dst",
389 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
415 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], IIC_UNARY_REG>,
390416 OpSize, Requires<[In32BitMode]>;
391417 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
392418 "inc{l}\t$dst",
393 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
419 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
420 IIC_UNARY_REG>,
394421 Requires<[In32BitMode]>;
395422 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
396 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>;
423 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
424 IIC_UNARY_REG>;
397425 } // isConvertibleToThreeAddress = 1, CodeSize = 1
398426
399427
402430 // Can transform into LEA.
403431 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
404432 "inc{w}\t$dst",
405 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
433 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))],
434 IIC_UNARY_REG>,
406435 OpSize, Requires<[In64BitMode]>;
407436 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
408437 "inc{l}\t$dst",
409 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
438 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
439 IIC_UNARY_REG>,
410440 Requires<[In64BitMode]>;
411441 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
412442 "dec{w}\t$dst",
413 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
443 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
444 IIC_UNARY_REG>,
414445 OpSize, Requires<[In64BitMode]>;
415446 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
416447 "dec{l}\t$dst",
417 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
448 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
449 IIC_UNARY_REG>,
418450 Requires<[In64BitMode]>;
419451 } // isConvertibleToThreeAddress = 1, CodeSize = 2
420452
423455 let CodeSize = 2 in {
424456 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
425457 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
426 (implicit EFLAGS)]>;
458 (implicit EFLAGS)], IIC_UNARY_MEM>;
427459 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
428460 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
429 (implicit EFLAGS)]>,
461 (implicit EFLAGS)], IIC_UNARY_MEM>,
430462 OpSize, Requires<[In32BitMode]>;
431463 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
432464 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
433 (implicit EFLAGS)]>,
465 (implicit EFLAGS)], IIC_UNARY_MEM>,
434466 Requires<[In32BitMode]>;
435467 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
436468 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
437 (implicit EFLAGS)]>;
469 (implicit EFLAGS)], IIC_UNARY_MEM>;
438470
439471 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
440472 // how to unfold them.
441473 // FIXME: What is this for??
442474 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
443475 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
444 (implicit EFLAGS)]>,
476 (implicit EFLAGS)], IIC_UNARY_MEM>,
445477 OpSize, Requires<[In64BitMode]>;
446478 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
447479 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
448 (implicit EFLAGS)]>,
480 (implicit EFLAGS)], IIC_UNARY_MEM>,
449481 Requires<[In64BitMode]>;
450482 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
451483 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
452 (implicit EFLAGS)]>,
484 (implicit EFLAGS)], IIC_UNARY_MEM>,
453485 OpSize, Requires<[In64BitMode]>;
454486 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
455487 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
456 (implicit EFLAGS)]>,
488 (implicit EFLAGS)], IIC_UNARY_MEM>,
457489 Requires<[In64BitMode]>;
458490 } // CodeSize = 2
459491
461493 let CodeSize = 2 in
462494 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
463495 "dec{b}\t$dst",
464 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
496 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))],
497 IIC_UNARY_REG>;
465498 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
466499 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
467500 "dec{w}\t$dst",
468 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
501 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
502 IIC_UNARY_REG>,
469503 OpSize, Requires<[In32BitMode]>;
470504 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
471505 "dec{l}\t$dst",
472 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
506 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
507 IIC_UNARY_REG>,
473508 Requires<[In32BitMode]>;
474509 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
475 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>;
510 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
511 IIC_UNARY_REG>;
476512 } // CodeSize = 2
477513 } // Constraints = "$src1 = $dst"
478514
480516 let CodeSize = 2 in {
481517 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
482518 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
483 (implicit EFLAGS)]>;
519 (implicit EFLAGS)], IIC_UNARY_MEM>;
484520 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
485521 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
486 (implicit EFLAGS)]>,
522 (implicit EFLAGS)], IIC_UNARY_MEM>,
487523 OpSize, Requires<[In32BitMode]>;
488524 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
489525 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
490 (implicit EFLAGS)]>,
526 (implicit EFLAGS)], IIC_UNARY_MEM>,
491527 Requires<[In32BitMode]>;
492528 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
493529 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
494 (implicit EFLAGS)]>;
530 (implicit EFLAGS)], IIC_UNARY_MEM>;
495531 } // CodeSize = 2
496532 } // Defs = [EFLAGS]
497533
587623 /// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
588624 /// or 1 (for i16,i32,i64 operations).
589625 class ITy opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
590 string mnemonic, string args, list pattern>
626 string mnemonic, string args, list pattern,
627 InstrItinClass itin = IIC_BIN_NONMEM>
591628 : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
592629 opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
593630 f, outs, ins,
594 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> {
631 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern,
632 itin> {
595633
596634 // Infer instruction prefixes from type info.
597635 let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
663701 dag outlist, list pattern>
664702 : ITy
665703 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
666 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>;
704 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_MEM>;
667705
668706 // BinOpRM_R - Instructions like "add reg, reg, [mem]".
669707 class BinOpRM_R opcode, string mnemonic, X86TypeInfo typeinfo,
775813 list pattern>
776814 : ITy
777815 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src),
778 mnemonic, "{$src, $dst|$dst, $src}", pattern>;
816 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM>;
779817
780818 // BinOpMR_RMW - Instructions like "add [mem], reg".
781819 class BinOpMR_RMW opcode, string mnemonic, X86TypeInfo typeinfo,
803841 Format f, list pattern, bits<8> opcode = 0x80>
804842 : ITy
805843 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src),
806 mnemonic, "{$src, $dst|$dst, $src}", pattern> {
844 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM> {
807845 let ImmT = typeinfo.ImmEncoding;
808846 }
809847
836874 Format f, list pattern>
837875 : ITy<0x82, f, typeinfo,
838876 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src),
839 mnemonic, "{$src, $dst|$dst, $src}", pattern> {
877 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM> {
840878 let ImmT = Imm8; // Always 8-bit immediate.
841879 }
842880
11491187 // register class is constrained to GR8_NOREX.
11501188 let isPseudo = 1 in
11511189 def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask),
1152 "", []>;
1190 "", [], IIC_BIN_NONMEM>;
11531191 }
11541192
11551193 //===----------------------------------------------------------------------===//
11591197 PatFrag ld_frag> {
11601198 def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
11611199 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1162 [(set RC:$dst, EFLAGS, (X86andn_flag RC:$src1, RC:$src2))]>;
1200 [(set RC:$dst, EFLAGS, (X86andn_flag RC:$src1, RC:$src2))],
1201 IIC_BIN_NONMEM>;
11631202 def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
11641203 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
11651204 [(set RC:$dst, EFLAGS,
1166 (X86andn_flag RC:$src1, (ld_frag addr:$src2)))]>;
1205 (X86andn_flag RC:$src1, (ld_frag addr:$src2)))], IIC_BIN_MEM>;
11671206 }
11681207
11691208 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2020 : I
2121 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
2222 [(set GR16:$dst,
23 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,TB,OpSize;
23 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
24 IIC_CMOV16_RR>,TB,OpSize;
2425 def #NAME#32rr
2526 : I
2627 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
2728 [(set GR32:$dst,
28 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>, TB;
29 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
30 IIC_CMOV32_RR>, TB;
2931 def #NAME#64rr
3032 :RI
3133 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
3234 [(set GR64:$dst,
33 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
35 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
36 IIC_CMOV32_RR>, TB;
3437 }
3538
3639 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" in {
3841 : I
3942 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
4043 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
41 CondNode, EFLAGS))]>, TB, OpSize;
44 CondNode, EFLAGS))], IIC_CMOV16_RM>,
45 TB, OpSize;
4246 def #NAME#32rm
4347 : I
4448 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
4549 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
46 CondNode, EFLAGS))]>, TB;
50 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
4751 def #NAME#64rm
4852 :RI
4953 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
5054 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
51 CondNode, EFLAGS))]>, TB;
55 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
5256 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
5357 } // end multiclass
5458
7781 let Uses = [EFLAGS] in {
7882 def r : I
7983 !strconcat(Mnemonic, "\t$dst"),
80 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))]>, TB;
84 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
85 IIC_SET_R>, TB;
8186 def m : I
8287 !strconcat(Mnemonic, "\t$dst"),
83 [(store (X86setcc OpNode, EFLAGS), addr:$dst)]>, TB;
88 [(store (X86setcc OpNode, EFLAGS), addr:$dst)],
89 IIC_SET_M>, TB;
8490 } // Uses = [EFLAGS]
8591 }
8692
1919 hasCtrlDep = 1, FPForm = SpecialFP in {
2020 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
2121 "ret",
22 [(X86retflag 0)]>;
22 [(X86retflag 0)], IIC_RET>;
2323 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
2424 "ret\t$amt",
25 [(X86retflag timm:$amt)]>;
25 [(X86retflag timm:$amt)], IIC_RET_IMM>;
2626 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
2727 "retw\t$amt",
28 []>, OpSize;
28 [], IIC_RET_IMM>, OpSize;
2929 def LRETL : I <0xCB, RawFrm, (outs), (ins),
30 "lretl", []>;
30 "lretl", [], IIC_RET>;
3131 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
32 "lretq", []>;
32 "lretq", [], IIC_RET>;
3333 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
34 "lret\t$amt", []>;
34 "lret\t$amt", [], IIC_RET>;
3535 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
36 "lretw\t$amt", []>, OpSize;
36 "lretw\t$amt", [], IIC_RET>, OpSize;
3737 }
3838
3939 // Unconditional branches.
4040 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
4141 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
42 "jmp\t$dst", [(br bb:$dst)]>;
42 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
4343 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
44 "jmp\t$dst", []>;
44 "jmp\t$dst", [], IIC_JMP_REL>;
4545 // FIXME : Intel syntax for JMP64pcrel32 such that it is not ambiguious
4646 // with JMP_1.
4747 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
48 "jmpq\t$dst", []>;
48 "jmpq\t$dst", [], IIC_JMP_REL>;
4949 }
5050
5151 // Conditional Branches.
5252 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
5353 multiclass ICBr opc1, bits<8> opc4, string asm, PatFrag Cond> {
54 def _1 : Ii8PCRel >;
54 def _1 : Ii8PCRel ,
55 IIC_Jcc>;
5556 def _4 : Ii32PCRel
56 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
57 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB;
5758 }
5859 }
5960
8182 // jecxz.
8283 let Uses = [CX] in
8384 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
84 "jcxz\t$dst", []>, AdSize, Requires<[In32BitMode]>;
85 "jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In32BitMode]>;
8586 let Uses = [ECX] in
8687 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
87 "jecxz\t$dst", []>, Requires<[In32BitMode]>;
88 "jecxz\t$dst", [], IIC_JCXZ>, Requires<[In32BitMode]>;
8889
8990 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
9091 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version
9192 // is jrcxz.
9293 let Uses = [ECX] in
9394 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
94 "jecxz\t$dst", []>, AdSize, Requires<[In64BitMode]>;
95 "jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>;
9596 let Uses = [RCX] in
9697 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
97 "jrcxz\t$dst", []>, Requires<[In64BitMode]>;
98 "jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>;
9899 }
99100
100101 // Indirect branches
101102 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
102103 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
103 [(brind GR32:$dst)]>, Requires<[In32BitMode]>;
104 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>;
104105 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
105 [(brind (loadi32 addr:$dst))]>, Requires<[In32BitMode]>;
106 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, Requires<[In32BitMode]>;
106107
107108 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
108 [(brind GR64:$dst)]>, Requires<[In64BitMode]>;
109 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>;
109110 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
110 [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>;
111 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, Requires<[In64BitMode]>;
111112
112113 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
113114 (ins i16imm:$off, i16imm:$seg),
114 "ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
115 "ljmp{w}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>, OpSize;
115116 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
116117 (ins i32imm:$off, i16imm:$seg),
117 "ljmp{l}\t{$seg, $off|$off, $seg}", []>;
118 "ljmp{l}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>;
118119 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
119 "ljmp{q}\t{*}$dst", []>;
120 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
120121
121122 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
122 "ljmp{w}\t{*}$dst", []>, OpSize;
123 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize;
123124 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
124 "ljmp{l}\t{*}$dst", []>;
125 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
125126 }
126127
127128
128129 // Loop instructions
129130
130 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
131 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
132 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
131 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
132 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
133 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
133134
134135 //===----------------------------------------------------------------------===//
135136 // Call Instructions...
146147 Uses = [ESP] in {
147148 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
148149 (outs), (ins i32imm_pcrel:$dst,variable_ops),
149 "call{l}\t$dst", []>, Requires<[In32BitMode]>;
150 "call{l}\t$dst", [], IIC_CALL_RI>, Requires<[In32BitMode]>;
150151 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
151 "call{l}\t{*}$dst", [(X86call GR32:$dst)]>,
152 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
152153 Requires<[In32BitMode]>;
153154 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
154 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>,
155 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], IIC_CALL_MEM>,
155156 Requires<[In32BitMode]>;
156157
157158 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
158159 (ins i16imm:$off, i16imm:$seg),
159 "lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
160 "lcall{w}\t{$seg, $off|$off, $seg}", [],
161 IIC_CALL_FAR_PTR>, OpSize;
160162 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
161163 (ins i32imm:$off, i16imm:$seg),
162 "lcall{l}\t{$seg, $off|$off, $seg}", []>;
164 "lcall{l}\t{$seg, $off|$off, $seg}", [],
165 IIC_CALL_FAR_PTR>;
163166
164167 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
165 "lcall{w}\t{*}$dst", []>, OpSize;
168 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize;
166169 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
167 "lcall{l}\t{*}$dst", []>;
170 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
168171
169172 // callw for 16 bit code for the assembler.
170173 let isAsmParserOnly = 1 in
195198 // mcinst.
196199 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
197200 (ins i32imm_pcrel:$dst, variable_ops),
198 "jmp\t$dst # TAILCALL",
199 []>;
201 "jmp\t$dst # TAILCALL",
202 [], IIC_JMP_REL>;
200203 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
201 "", []>; // FIXME: Remove encoding when JIT is dead.
204 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
202205 let mayLoad = 1 in
203206 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
204 "jmp{l}\t{*}$dst # TAILCALL", []>;
207 "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
205208 }
206209
207210
225228 // the 32-bit pcrel field that we have.
226229 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
227230 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
228 "call{q}\t$dst", []>,
231 "call{q}\t$dst", [], IIC_CALL_RI>,
229232 Requires<[In64BitMode, NotWin64]>;
230233 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
231 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
234 "call{q}\t{*}$dst", [(X86call GR64:$dst)],
235 IIC_CALL_RI>,
232236 Requires<[In64BitMode, NotWin64]>;
233237 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
234 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
238 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
239 IIC_CALL_MEM>,
235240 Requires<[In64BitMode, NotWin64]>;
236241
237242 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
238 "lcall{q}\t{*}$dst", []>;
243 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
239244 }
240245
241246 // FIXME: We need to teach codegen about single list of call-clobbered
252257 Uses = [RSP] in {
253258 def WINCALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
254259 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
255 "call{q}\t$dst", []>,
260 "call{q}\t$dst", [], IIC_CALL_RI>,
256261 Requires<[IsWin64]>;
257262 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
258263 "call{q}\t{*}$dst",
259 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
264 [(X86call GR64:$dst)], IIC_CALL_RI>,
265 Requires<[IsWin64]>;
260266 def WINCALL64m : I<0xFF, MRM2m, (outs),
261267 (ins i64mem:$dst,variable_ops),
262268 "call{q}\t{*}$dst",
263 [(X86call (loadi64 addr:$dst))]>,
269 [(X86call (loadi64 addr:$dst))], IIC_CALL_MEM>,
264270 Requires<[IsWin64]>;
265271 }
266272
271277 Uses = [RSP] in {
272278 def W64ALLOCA : Ii32PCRel<0xE8, RawFrm,
273279 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
274 "call{q}\t$dst", []>,
280 "call{q}\t$dst", [], IIC_CALL_RI>,
275281 Requires<[IsWin64]>;
276282 }
277283
295301
296302 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
297303 (ins i64i32imm_pcrel:$dst, variable_ops),
298 "jmp\t$dst # TAILCALL", []>;
304 "jmp\t$dst # TAILCALL", [], IIC_JMP_REL>;
299305 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst, variable_ops),
300 "jmp{q}\t{*}$dst # TAILCALL", []>;
306 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
301307
302308 let mayLoad = 1 in
303309 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
304 "jmp{q}\t{*}$dst # TAILCALL", []>;
305 }
310 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
311 }
122122 class MemOp4 { bit hasMemOp4Prefix = 1; }
123123 class XOP { bit hasXOP_Prefix = 1; }
124124 class X86Inst opcod, Format f, ImmType i, dag outs, dag ins,
125 string AsmStr, Domain d = GenericDomain>
125 string AsmStr,
126 InstrItinClass itin,
127 Domain d = GenericDomain>
126128 : Instruction {
127129 let Namespace = "X86";
128130
137139
138140 // If this is a pseudo instruction, mark it isCodeGenOnly.
139141 let isCodeGenOnly = !eq(!cast(f), "Pseudo");
142
143 let Itinerary = itin;
140144
141145 //
142146 // Attributes specific to X86 instructions...
188192 }
189193
190194 class PseudoI pattern>
191 : X86Inst<0, Pseudo, NoImm, oops, iops, ""> {
195 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
192196 let Pattern = pattern;
193197 }
194198
195199 class I o, Format f, dag outs, dag ins, string asm,
196 list pattern, Domain d = GenericDomain>
197 : X86Inst {
200 list pattern, InstrItinClass itin = IIC_DEFAULT,
201 Domain d = GenericDomain>
202 : X86Inst {
198203 let Pattern = pattern;
199204 let CodeSize = 3;
200205 }
201206 class Ii8 o, Format f, dag outs, dag ins, string asm,
202 list pattern, Domain d = GenericDomain>
203 : X86Inst {
207 list pattern, InstrItinClass itin = IIC_DEFAULT,
208 Domain d = GenericDomain>
209 : X86Inst {
204210 let Pattern = pattern;
205211 let CodeSize = 3;
206212 }
207213 class Ii8PCRel o, Format f, dag outs, dag ins, string asm,
208 list pattern>
209 : X86Inst {
214 list pattern, InstrItinClass itin = IIC_DEFAULT>
215 : X86Inst {
210216 let Pattern = pattern;
211217 let CodeSize = 3;
212218 }
213219 class Ii16 o, Format f, dag outs, dag ins, string asm,
214 list pattern>
215 : X86Inst {
220 list pattern, InstrItinClass itin = IIC_DEFAULT>
221 : X86Inst {
216222 let Pattern = pattern;
217223 let CodeSize = 3;
218224 }
219225 class Ii32 o, Format f, dag outs, dag ins, string asm,
220 list pattern>
221 : X86Inst {
226 list pattern, InstrItinClass itin = IIC_DEFAULT>
227 : X86Inst {
222228 let Pattern = pattern;
223229 let CodeSize = 3;
224230 }
225231
226232 class Ii16PCRel o, Format f, dag outs, dag ins, string asm,
227 list pattern>
228 : X86Inst {
233 list pattern, InstrItinClass itin = IIC_DEFAULT>
234 : X86Inst {
229235 let Pattern = pattern;
230236 let CodeSize = 3;
231237 }
232238
233239 class Ii32PCRel o, Format f, dag outs, dag ins, string asm,
234 list pattern>
235 : X86Inst {
240 list pattern, InstrItinClass itin = IIC_DEFAULT>
241 : X86Inst {
236242 let Pattern = pattern;
237243 let CodeSize = 3;
238244 }
243249 : I {}
244250
245251 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
246 class FpI_ pattern>
247 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
252 class FpI_ pattern,
253 InstrItinClass itin = IIC_DEFAULT>
254 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
248255 let FPForm = fp;
249256 let Pattern = pattern;
250257 }
256263 // Iseg32 - 16-bit segment selector, 32-bit offset
257264
258265 class Iseg16 o, Format f, dag outs, dag ins, string asm,
259 list pattern> : X86Inst {
266 list pattern, InstrItinClass itin = IIC_DEFAULT>
267 : X86Inst {
260268 let Pattern = pattern;
261269 let CodeSize = 3;
262270 }
263271
264272 class Iseg32 o, Format f, dag outs, dag ins, string asm,
265 list pattern> : X86Inst {
273 list pattern, InstrItinClass itin = IIC_DEFAULT>
274 : X86Inst {
266275 let Pattern = pattern;
267276 let CodeSize = 3;
268277 }
269278
270279 // SI - SSE 1 & 2 scalar instructions
271 class SI o, Format F, dag outs, dag ins, string asm, list pattern>
272 : I {
280 class SI o, Format F, dag outs, dag ins, string asm,
281 list pattern, InstrItinClass itin = IIC_DEFAULT>
282 : I {
273283 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
274284 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
275285
279289
280290 // SIi8 - SSE 1 & 2 scalar instructions
281291 class SIi8 o, Format F, dag outs, dag ins, string asm,
282 list pattern>
283 : Ii8 {
292 list pattern, InstrItinClass itin = IIC_DEFAULT>
293 : Ii8 {
284294 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
285295 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
286296
290300
291301 // PI - SSE 1 & 2 packed instructions
292302 class PI o, Format F, dag outs, dag ins, string asm, list pattern,
293 Domain d>
294 : I {
303 InstrItinClass itin, Domain d>
304 : I {
295305 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
296306 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
297307
301311
302312 // PIi8 - SSE 1 & 2 packed instructions with immediate
303313 class PIi8 o, Format F, dag outs, dag ins, string asm,
304 list pattern, Domain d>
305 : Ii8 {
314 list pattern, InstrItinClass itin, Domain d>
315 : Ii8 {
306316 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
307317 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
308318
318328 // VSSI - SSE1 instructions with XS prefix in AVX form.
319329 // VPSI - SSE1 instructions with TB prefix in AVX form.
320330
321 class SSI o, Format F, dag outs, dag ins, string asm, list pattern>
322 : I, XS, Requires<[HasSSE1]>;
331 class SSI o, Format F, dag outs, dag ins, string asm,
332 list pattern, InstrItinClass itin = IIC_DEFAULT>
333 : I, XS, Requires<[HasSSE1]>;
323334 class SSIi8 o, Format F, dag outs, dag ins, string asm,
324 list pattern>
325 : Ii8, XS, Requires<[HasSSE1]>;
326 class PSI o, Format F, dag outs, dag ins, string asm, list pattern>
327 : I, TB,
335 list pattern, InstrItinClass itin = IIC_DEFAULT>
336 : Ii8, XS, Requires<[HasSSE1]>;
337 class PSI o, Format F, dag outs, dag ins, string asm,
338 list pattern, InstrItinClass itin = IIC_DEFAULT>
339 : I, TB,
328340 Requires<[HasSSE1]>;
329341 class PSIi8 o, Format F, dag outs, dag ins, string asm,
330 list pattern>
331 : Ii8, TB,
342 list pattern, InstrItinClass itin = IIC_DEFAULT>
343 : Ii8, TB,
332344 Requires<[HasSSE1]>;
333345 class VSSI o, Format F, dag outs, dag ins, string asm,
334 list pattern>
335 : I, XS,
346 list pattern, InstrItinClass itin = IIC_DEFAULT>
347 : I, XS,
336348 Requires<[HasAVX]>;
337349 class VPSI o, Format F, dag outs, dag ins, string asm,
338 list pattern>
339 : I, TB,
350 list pattern, InstrItinClass itin = IIC_DEFAULT>
351 : I, TB,
340352 Requires<[HasAVX]>;
341353
342354 // SSE2 Instruction Templates:
349361 // VSDI - SSE2 instructions with XD prefix in AVX form.
350362 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
351363
352 class SDI o, Format F, dag outs, dag ins, string asm, list pattern>
353 : I, XD, Requires<[HasSSE2]>;
364 class SDI o, Format F, dag outs, dag ins, string asm,
365 list pattern, InstrItinClass itin = IIC_DEFAULT>
366 : I, XD, Requires<[HasSSE2]>;
354367 class SDIi8 o, Format F, dag outs, dag ins, string asm,
355 list pattern>
356 : Ii8, XD, Requires<[HasSSE2]>;
368 list pattern, InstrItinClass itin = IIC_DEFAULT>
369 : Ii8, XD, Requires<[HasSSE2]>;
357370 class SSDIi8 o, Format F, dag outs, dag ins, string asm,
358371 list pattern>
359372 : Ii8, XS, Requires<[HasSSE2]>;
360 class PDI o, Format F, dag outs, dag ins, string asm, list pattern>
361 : I, TB, OpSize,
373 class PDI o, Format F, dag outs, dag ins, string asm,
374 list pattern, InstrItinClass itin = IIC_DEFAULT>
375 : I, TB, OpSize,
362376 Requires<[HasSSE2]>;
363377 class PDIi8 o, Format F, dag outs, dag ins, string asm,
364 list pattern>
365 : Ii8, TB, OpSize,
378 list pattern, InstrItinClass itin = IIC_DEFAULT>
379 : Ii8, TB, OpSize,
366380 Requires<[HasSSE2]>;
367381 class VSDI o, Format F, dag outs, dag ins, string asm,
368 list pattern>
369 : I, XD,
382 list pattern, InstrItinClass itin = IIC_DEFAULT>
383 : I, XD,
370384 Requires<[HasAVX]>;
371385 class VPDI o, Format F, dag outs, dag ins, string asm,
372 list pattern>
373 : I, TB,
386 list pattern, InstrItinClass itin = IIC_DEFAULT>
387 : I, TB,
374388 OpSize, Requires<[HasAVX]>;
375389
376390 // SSE3 Instruction Templates:
380394 // S3DI - SSE3 instructions with XD prefix.
381395
382396 class S3SI o, Format F, dag outs, dag ins, string asm,
383 list pattern>
384 : I, XS,
397 list pattern, InstrItinClass itin = IIC_DEFAULT>
398 : I, XS,
385399 Requires<[HasSSE3]>;
386400 class S3DI o, Format F, dag outs, dag ins, string asm,
387 list pattern>
388 : I, XD,
401 list pattern, InstrItinClass itin = IIC_DEFAULT>
402 : I, XD,
389403 Requires<[HasSSE3]>;
390 class S3I o, Format F, dag outs, dag ins, string asm, list pattern>
391 : I, TB, OpSize,
404 class S3I o, Format F, dag outs, dag ins, string asm,
405 list pattern, InstrItinClass itin = IIC_DEFAULT>
406 : I, TB, OpSize,
392407 Requires<[HasSSE3]>;
393408
394409
402417 // classes. They need to be enabled even if AVX is enabled.
403418
404419 class SS38I o, Format F, dag outs, dag ins, string asm,
405 list pattern>
406 : I, T8,
420 list pattern, InstrItinClass itin = IIC_DEFAULT>
421 : I, T8,
407422 Requires<[HasSSSE3]>;
408423 class SS3AI o, Format F, dag outs, dag ins, string asm,
409 list pattern>
410 : Ii8, TA,
424 list pattern, InstrItinClass itin = IIC_DEFAULT>
425 : Ii8, TA,
411426 Requires<[HasSSSE3]>;
412427
413428 // SSE4.1 Instruction Templates:
416431 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
417432 //
418433 class SS48I o, Format F, dag outs, dag ins, string asm,
419 list pattern>
420 : I, T8,
434 list pattern, InstrItinClass itin = IIC_DEFAULT>
435 : I, T8,
421436 Requires<[HasSSE41]>;
422437 class SS4AIi8 o, Format F, dag outs, dag ins, string asm,
423 list pattern>
424 : Ii8, TA,
438 list pattern, InstrItinClass itin = IIC_DEFAULT>
439 : Ii8, TA,
425440 Requires<[HasSSE41]>;
426441
427442 // SSE4.2 Instruction Templates:
428443 //
429444 // SS428I - SSE 4.2 instructions with T8 prefix.
430445 class SS428I o, Format F, dag outs, dag ins, string asm,
431 list pattern>
432 : I, T8,
446 list pattern, InstrItinClass itin = IIC_DEFAULT>
447 : I, T8,
433448 Requires<[HasSSE42]>;
434449
435450 // SS42FI - SSE 4.2 instructions with T8XD prefix.
436451 class SS42FI o, Format F, dag outs, dag ins, string asm,
437 list pattern>
438 : I, T8XD, Requires<[HasSSE42]>;
452 list pattern, InstrItinClass itin = IIC_DEFAULT>
453 : I, T8XD, Requires<[HasSSE42]>;
439454
440455 // SS42AI = SSE 4.2 instructions with TA prefix
441456 class SS42AI o, Format F, dag outs, dag ins, string asm,
442 list pattern>
443 : Ii8, TA,
457 list pattern, InstrItinClass itin = IIC_DEFAULT>
458 : Ii8, TA,
444459 Requires<[HasSSE42]>;
445460
446461 // AVX Instruction Templates:
449464 // AVX8I - AVX instructions with T8 and OpSize prefix.
450465 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
451466 class AVX8I o, Format F, dag outs, dag ins, string asm,
452 list pattern>
453 : I, T8, OpSize,
467 list pattern, InstrItinClass itin = IIC_DEFAULT>
468 : I, T8, OpSize,
454469 Requires<[HasAVX]>;
455470 class AVXAIi8 o, Format F, dag outs, dag ins, string asm,
456 list pattern>
457 : Ii8, TA, OpSize,
471 list pattern, InstrItinClass itin = IIC_DEFAULT>
472 : Ii8, TA, OpSize,
458473 Requires<[HasAVX]>;
459474
460475 // AVX2 Instruction Templates:
463478 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
464479 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
465480 class AVX28I o, Format F, dag outs, dag ins, string asm,
466 list pattern>
467 : I, T8, OpSize,
481 list pattern, InstrItinClass itin = IIC_DEFAULT>
482 : I, T8, OpSize,
468483 Requires<[HasAVX2]>;
469484 class AVX2AIi8 o, Format F, dag outs, dag ins, string asm,
470 list pattern>
471 : Ii8, TA, OpSize,
485 list pattern, InstrItinClass itin = IIC_DEFAULT>
486 : Ii8, TA, OpSize,
472487 Requires<[HasAVX2]>;
473488
474489 // AES Instruction Templates:
476491 // AES8I
477492 // These use the same encoding as the SSE4.2 T8 and TA encodings.
478493 class AES8I o, Format F, dag outs, dag ins, string asm,
479 listpattern>
480 : I, T8,
494 listpattern, InstrItinClass itin = IIC_DEFAULT>
495 : I, T8,
481496 Requires<[HasSSE2, HasAES]>;
482497
483498 class AESAI o, Format F, dag outs, dag ins, string asm,
484 list pattern>
485 : Ii8, TA,
499 list pattern, InstrItinClass itin = IIC_DEFAULT>
500 : Ii8, TA,
486501 Requires<[HasSSE2, HasAES]>;
487502
488503 // CLMUL Instruction Templates
489504 class CLMULIi8 o, Format F, dag outs, dag ins, string asm,
490 listpattern>
491 : Ii8, TA,
505 listpattern, InstrItinClass itin = IIC_DEFAULT>
506 : Ii8, TA,
492507 OpSize, Requires<[HasSSE2, HasCLMUL]>;
493508
494509 class AVXCLMULIi8 o, Format F, dag outs, dag ins, string asm,
495 listpattern>
496 : Ii8, TA,
510 listpattern, InstrItinClass itin = IIC_DEFAULT>
511 : Ii8, TA,
497512 OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
498513
499514 // FMA3 Instruction Templates
500515 class FMA3 o, Format F, dag outs, dag ins, string asm,
501 listpattern>
502 : I, T8,
516 listpattern, InstrItinClass itin = IIC_DEFAULT>
517 : I, T8,
503518 OpSize, VEX_4V, Requires<[HasFMA3]>;
504519
505520 // FMA4 Instruction Templates
506521 class FMA4 o, Format F, dag outs, dag ins, string asm,
507 listpattern>
508 : Ii8, TA,
522 listpattern, InstrItinClass itin = IIC_DEFAULT>
523 : I, TA,
509524 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>;
510525
511526 // XOP 2, 3 and 4 Operand Instruction Template
512527 class IXOP o, Format F, dag outs, dag ins, string asm,
513 list pattern>
514 : I,
528 list pattern, InstrItinClass itin = IIC_DEFAULT>
529 : I,
515530 XOP, XOP9, Requires<[HasXOP]>;
516531
517532 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
518533 class IXOPi8 o, Format F, dag outs, dag ins, string asm,
519 list pattern>
520 : Ii8,
534 list pattern, InstrItinClass itin = IIC_DEFAULT>
535 : Ii8,
521536 XOP, XOP8, Requires<[HasXOP]>;
522537
523538 // XOP 5 operand instruction (VEX encoding!)
524539 class IXOP5 o, Format F, dag outs, dag ins, string asm,
525 listpattern>
526 : Ii8, TA,
540 listpattern, InstrItinClass itin = IIC_DEFAULT>
541 : Ii8, TA,
527542 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
528543
529544 // X86-64 Instruction templates...
530545 //
531546
532 class RI o, Format F, dag outs, dag ins, string asm, list pattern>
533 : I, REX_W;
547 class RI o, Format F, dag outs, dag ins, string asm,
548 list pattern, InstrItinClass itin = IIC_DEFAULT>
549 : I, REX_W;
534550 class RIi8 o, Format F, dag outs, dag ins, string asm,
535 list pattern>
536 : Ii8, REX_W;
551 list pattern, InstrItinClass itin = IIC_DEFAULT>
552 : Ii8, REX_W;
537553 class RIi32 o, Format F, dag outs, dag ins, string asm,
538 list pattern>
539 : Ii32, REX_W;
554 list pattern, InstrItinClass itin = IIC_DEFAULT>
555 : Ii32, REX_W;
540556
541557 class RIi64 o, Format f, dag outs, dag ins, string asm,
542 list pattern>
543 : X86Inst, REX_W {
558 list pattern, InstrItinClass itin = IIC_DEFAULT>
559 : X86Inst, REX_W {
544560 let Pattern = pattern;
545561 let CodeSize = 3;
546562 }
547563
548564 class RSSI o, Format F, dag outs, dag ins, string asm,
549 list pattern>
550 : SSI, REX_W;
565 list pattern, InstrItinClass itin = IIC_DEFAULT>
566 : SSI, REX_W;
551567 class RSDI o, Format F, dag outs, dag ins, string asm,
552 list pattern>
553 : SDI, REX_W;
568 list pattern, InstrItinClass itin = IIC_DEFAULT>
569 : SDI, REX_W;
554570 class RPDI o, Format F, dag outs, dag ins, string asm,
555 list pattern>
556 : PDI, REX_W;
571 list pattern, InstrItinClass itin = IIC_DEFAULT>
572 : PDI, REX_W;
557573 class VRPDI o, Format F, dag outs, dag ins, string asm,
558 list pattern>
559 : VPDI, VEX_W;
574 list pattern, InstrItinClass itin = IIC_DEFAULT>
575 : VPDI, VEX_W;
560576
561577 // MMX Instruction templates
562578 //
569585 // MMXID - MMX instructions with XD prefix.
570586 // MMXIS - MMX instructions with XS prefix.
571587 class MMXI o, Format F, dag outs, dag ins, string asm,
572 list pattern>
573 : I, TB, Requires<[HasMMX]>;
588 list pattern, InstrItinClass itin = IIC_DEFAULT>
589 : I, TB, Requires<[HasMMX]>;
574590 class MMXI64 o, Format F, dag outs, dag ins, string asm,
575 list pattern>
576 : I, TB, Requires<[HasMMX,In64BitMode]>;
591 list pattern, InstrItinClass itin = IIC_DEFAULT>
592 : I, TB, Requires<[HasMMX,In64BitMode]>;
577593 class MMXRI o, Format F, dag outs, dag ins, string asm,
578 list pattern>
579 : I, TB, REX_W, Requires<[HasMMX]>;
594 list pattern, InstrItinClass itin = IIC_DEFAULT>
595 : I, TB, REX_W, Requires<[HasMMX]>;
580596 class MMX2I o, Format F, dag outs, dag ins, string asm,
581 list pattern>
582 : I, TB, OpSize, Requires<[HasMMX]>;
597 list pattern, InstrItinClass itin = IIC_DEFAULT>
598 : I, TB, OpSize, Requires<[HasMMX]>;
583599 class MMXIi8 o, Format F, dag outs, dag ins, string asm,
584 list pattern>
585 : Ii8, TB, Requires<[HasMMX]>;
600 list pattern, InstrItinClass itin = IIC_DEFAULT>
601 : Ii8, TB, Requires<[HasMMX]>;
586602 class MMXID o, Format F, dag outs, dag ins, string asm,
587 list pattern>
588 : Ii8, XD, Requires<[HasMMX]>;
603 list pattern, InstrItinClass itin = IIC_DEFAULT>
604 : Ii8, XD, Requires<[HasMMX]>;
589605 class MMXIS o, Format F, dag outs, dag ins, string asm,
590 list pattern>
591 : Ii8, XS, Requires<[HasMMX]>;
606 list pattern, InstrItinClass itin = IIC_DEFAULT>
607 : Ii8, XS, Requires<[HasMMX]>;
104104 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
105105 string asm, Domain d> {
106106 def irr : PI
107 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
107 [(set DstRC:$dst, (Int SrcRC:$src))],
108 IIC_DEFAULT, d>;
108109 def irm : PI
109 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
110 [(set DstRC:$dst, (Int (ld_frag addr:$src)))],
111 IIC_DEFAULT, d>;
110112 }
111113
112114 multiclass sse12_cvt_pint_3addr opc, RegisterClass SrcRC,
113115 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
114116 PatFrag ld_frag, string asm, Domain d> {
115117 def irr : PI
116 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
118 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
119 IIC_DEFAULT, d>;
117120 def irm : PI
118121 (ins DstRC:$src1, x86memop:$src2), asm,
119 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
122 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
123 IIC_DEFAULT, d>;
120124 }
121125
122126 //===----------------------------------------------------------------------===//
6666 !if(Is2Addr,
6767 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6868 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
69 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
69 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_DEFAULT, d>;
7070 let mayLoad = 1 in
7171 def rm : PI
7272 !if(Is2Addr,
7373 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7474 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
75 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
75 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
76 IIC_DEFAULT, d>;
7677 }
7778
7879 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
8687 !if(Is2Addr,
8788 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
8889 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
89 pat_rr, d>;
90 pat_rr, IIC_DEFAULT, d>;
9091 def rm : PI
9192 !if(Is2Addr,
9293 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
9394 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
94 pat_rm, d>;
95 pat_rm, IIC_DEFAULT, d>;
9596 }
9697
9798 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
105106 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106107 [(set RC:$dst, (!cast(
107108 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
109110 def rm_Int : PI
110111 !if(Is2Addr,
111112 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112113 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113114 [(set RC:$dst, (!cast(
114115 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
116 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
116117 }
117118
118119 //===----------------------------------------------------------------------===//
736737 bit IsReMaterializable = 1> {
737738 let neverHasSideEffects = 1 in
738739 def rr : PI
739 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
740 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], IIC_DEFAULT, d>;
740741 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
741742 def rm : PI
742743 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
743 [(set RC:$dst, (ld_frag addr:$src))], d>;
744 [(set RC:$dst, (ld_frag addr:$src))], IIC_DEFAULT, d>;
744745 }
745746
746747 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
10021003 [(set RC:$dst,
10031004 (mov_frag RC:$src1,
10041005 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1005 SSEPackedSingle>, TB;
1006 IIC_DEFAULT, SSEPackedSingle>, TB;
10061007
10071008 def PDrm : PI
10081009 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
10091010 !strconcat(base_opc, "d", asm_opr),
10101011 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
10111012 (scalar_to_vector (loadf64 addr:$src2)))))],
1012 SSEPackedDouble>, TB, OpSize;
1013 IIC_DEFAULT, SSEPackedDouble>, TB, OpSize;
10131014 }
10141015
10151016 let AddedComplexity = 20 in {
14121413 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
14131414 string asm, Domain d> {
14141415 def rr : PI
1415 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1416 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1417 IIC_DEFAULT, d>;
14161418 def rm : PI
1417 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1419 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1420 IIC_DEFAULT, d>;
14181421 }
14191422
14201423 multiclass sse12_vcvt_avx opc, RegisterClass SrcRC, RegisterClass DstRC,
21232126 PatFrag ld_frag, string OpcodeStr, Domain d> {
21242127 def rr: PI
21252128 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2126 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2129 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2130 IIC_DEFAULT, d>;
21272131 def rm: PI
21282132 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
21292133 [(set EFLAGS, (OpNode (vt RC:$src1),
2130 (ld_frag addr:$src2)))], d>;
2134 (ld_frag addr:$src2)))],
2135 IIC_DEFAULT, d>;
21312136 }
21322137
21332138 let Defs = [EFLAGS] in {
21842189 let isAsmParserOnly = 1 in {
21852190 def rri : PIi8<0xC2, MRMSrcReg,
21862191 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2187 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], d>;
2192 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2193 IIC_DEFAULT, d>;
21882194 def rmi : PIi8<0xC2, MRMSrcMem,
21892195 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
2190 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], d>;
2196 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2197 IIC_DEFAULT, d>;
21912198 }
21922199
21932200 // Accept explicit immediate argument form instead of comparison code.
21942201 def rri_alt : PIi8<0xC2, MRMSrcReg,
21952202 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2196 asm_alt, [], d>;
2203 asm_alt, [], IIC_DEFAULT, d>;
21972204 def rmi_alt : PIi8<0xC2, MRMSrcMem,
21982205 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2199 asm_alt, [], d>;
2206 asm_alt, [], IIC_DEFAULT, d>;
22002207 }
22012208
22022209 defm VCMPPS : sse12_cmp_packed
22712278 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
22722279 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
22732280 [(set RC:$dst, (vt (shufp:$src3
2274 RC:$src1, (mem_frag addr:$src2))))], d>;
2281 RC:$src1, (mem_frag addr:$src2))))],
2282 IIC_DEFAULT, d>;
22752283 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
22762284 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
22772285 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
22782286 [(set RC:$dst,
2279 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2287 (vt (shufp:$src3 RC:$src1, RC:$src2)))],
2288 IIC_DEFAULT, d>;
22802289 }
22812290
22822291 defm VSHUFPS : sse12_shuffle
24472456 def rr : PI
24482457 (outs RC:$dst), (ins RC:$src1, RC:$src2),
24492458 asm, [(set RC:$dst,
2450 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2459 (vt (OpNode RC:$src1, RC:$src2)))],
2460 IIC_DEFAULT, d>;
24512461 def rm : PI
24522462 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
24532463 asm, [(set RC:$dst,
24542464 (vt (OpNode RC:$src1,
2455 (mem_frag addr:$src2))))], d>;
2465 (mem_frag addr:$src2))))],
2466 IIC_DEFAULT, d>;
24562467 }
24572468
24582469 let AddedComplexity = 10 in {
25882599 Domain d> {
25892600 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
25902601 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2591 [(set GR32:$dst, (Int RC:$src))], d>;
2602 [(set GR32:$dst, (Int RC:$src))], IIC_DEFAULT, d>;
25922603 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2593 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2604 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2605 IIC_DEFAULT, d>, REX_W;
25942606 }
25952607
25962608 let Predicates = [HasAVX] in {
26202632
26212633 // Assembler Only
26222634 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2623 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2635 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2636 SSEPackedSingle>, TB, VEX;
26242637 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2625 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2638 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2639 SSEPackedDouble>, TB,
26262640 OpSize, VEX;
26272641 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2628 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2642 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2643 SSEPackedSingle>, TB, VEX;
26292644 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2630 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2645 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2646 SSEPackedDouble>, TB,
26312647 OpSize, VEX;
26322648 }
26332649
63946410 !strconcat(OpcodeStr,
63956411 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
63966412 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6397 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6413 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
63986414
63996415 def rm : Ii8
64006416 (ins RC:$src1, x86memop:$src2, RC:$src3),
64036419 [(set RC:$dst,
64046420 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
64056421 RC:$src3))],
6406 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6422 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
64076423 }
64086424
64096425 let Predicates = [HasAVX] in {
1818 let Uses = [CL] in {
1919 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
2020 "shl{b}\t{%cl, $dst|$dst, CL}",
21 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
21 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
2222 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2323 "shl{w}\t{%cl, $dst|$dst, CL}",
24 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
24 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
2525 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2626 "shl{l}\t{%cl, $dst|$dst, CL}",
27 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
27 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>;
2828 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
2929 "shl{q}\t{%cl, $dst|$dst, CL}",
30 [(set GR64:$dst, (shl GR64:$src1, CL))]>;
30 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
3131 } // Uses = [CL]
3232
3333 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
3434 "shl{b}\t{$src2, $dst|$dst, $src2}",
35 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
35 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
3636
3737 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
3838 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
3939 "shl{w}\t{$src2, $dst|$dst, $src2}",
40 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
40 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
41 OpSize;
4142 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
4243 "shl{l}\t{$src2, $dst|$dst, $src2}",
43 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
44 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>;
4445 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
4546 (ins GR64:$src1, i8imm:$src2),
4647 "shl{q}\t{$src2, $dst|$dst, $src2}",
47 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
48 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
49 IIC_SR>;
4850
4951 // NOTE: We don't include patterns for shifts of a register by one, because
5052 // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
5153 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
52 "shl{b}\t$dst", []>;
54 "shl{b}\t$dst", [], IIC_SR>;
5355 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
54 "shl{w}\t$dst", []>, OpSize;
56 "shl{w}\t$dst", [], IIC_SR>, OpSize;
5557 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
56 "shl{l}\t$dst", []>;
58 "shl{l}\t$dst", [], IIC_SR>;
5759 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
58 "shl{q}\t$dst", []>;
60 "shl{q}\t$dst", [], IIC_SR>;
5961 } // isConvertibleToThreeAddress = 1
6062 } // Constraints = "$src = $dst"
6163
6567 let Uses = [CL] in {
6668 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
6769 "shl{b}\t{%cl, $dst|$dst, CL}",
68 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
70 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
6971 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
7072 "shl{w}\t{%cl, $dst|$dst, CL}",
71 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
73 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
74 OpSize;
7275 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
7376 "shl{l}\t{%cl, $dst|$dst, CL}",
74 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
77 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
7578 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
7679 "shl{q}\t{%cl, $dst|$dst, CL}",
77 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
80 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
7881 }
7982 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
8083 "shl{b}\t{$src, $dst|$dst, $src}",
81 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
84 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
85 IIC_SR>;
8286 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
8387 "shl{w}\t{$src, $dst|$dst, $src}",
84 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
88 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
89 IIC_SR>,
8590 OpSize;
8691 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
8792 "shl{l}\t{$src, $dst|$dst, $src}",
88 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
93 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
94 IIC_SR>;
8995 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
9096 "shl{q}\t{$src, $dst|$dst, $src}",
91 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
97 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
98 IIC_SR>;
9299
93100 // Shift by 1
94101 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
95102 "shl{b}\t$dst",
96 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
103 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
104 IIC_SR>;
97105 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
98106 "shl{w}\t$dst",
99 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
107 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
108 IIC_SR>,
100109 OpSize;
101110 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
102111 "shl{l}\t$dst",
103 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
112 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
113 IIC_SR>;
104114 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
105115 "shl{q}\t$dst",
106 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
116 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
117 IIC_SR>;
107118
108119 let Constraints = "$src1 = $dst" in {
109120 let Uses = [CL] in {
110121 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
111122 "shr{b}\t{%cl, $dst|$dst, CL}",
112 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
123 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
113124 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
114125 "shr{w}\t{%cl, $dst|$dst, CL}",
115 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
126 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
116127 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
117128 "shr{l}\t{%cl, $dst|$dst, CL}",
118 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
129 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>;
119130 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
120131 "shr{q}\t{%cl, $dst|$dst, CL}",
121 [(set GR64:$dst, (srl GR64:$src1, CL))]>;
132 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
122133 }
123134
124135 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
125136 "shr{b}\t{$src2, $dst|$dst, $src2}",
126 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
137 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
127138 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
128139 "shr{w}\t{$src2, $dst|$dst, $src2}",
129 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
140 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
141 IIC_SR>, OpSize;
130142 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
131143 "shr{l}\t{$src2, $dst|$dst, $src2}",
132 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
144 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
145 IIC_SR>;
133146 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
134147 "shr{q}\t{$src2, $dst|$dst, $src2}",
135 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
148 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
136149
137150 // Shift right by 1
138151 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
139152 "shr{b}\t$dst",
140 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
153 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
141154 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
142155 "shr{w}\t$dst",
143 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
156 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
144157 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
145158 "shr{l}\t$dst",
146 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
159 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>;
147160 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
148161 "shr{q}\t$dst",
149 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
162 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
150163 } // Constraints = "$src = $dst"
151164
152165
153166 let Uses = [CL] in {
154167 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
155168 "shr{b}\t{%cl, $dst|$dst, CL}",
156 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
169 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
157170 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
158171 "shr{w}\t{%cl, $dst|$dst, CL}",
159 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
172 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
160173 OpSize;
161174 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
162175 "shr{l}\t{%cl, $dst|$dst, CL}",
163 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
176 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
164177 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
165178 "shr{q}\t{%cl, $dst|$dst, CL}",
166 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
179 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
167180 }
168181 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
169182 "shr{b}\t{$src, $dst|$dst, $src}",
170 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
183 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
184 IIC_SR>;
171185 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
172186 "shr{w}\t{$src, $dst|$dst, $src}",
173 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
187 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
188 IIC_SR>,
174189 OpSize;
175190 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
176191 "shr{l}\t{$src, $dst|$dst, $src}",
177 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
192 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
193 IIC_SR>;
178194 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
179195 "shr{q}\t{$src, $dst|$dst, $src}",
180 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
196 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
197 IIC_SR>;
181198
182199 // Shift by 1
183200 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
184201 "shr{b}\t$dst",
185 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
202 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
203 IIC_SR>;
186204 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
187205 "shr{w}\t$dst",
188 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
206 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
207 IIC_SR>,OpSize;
189208 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
190209 "shr{l}\t$dst",
191 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
210 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
211 IIC_SR>;
192212 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
193213 "shr{q}\t$dst",
194 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
214 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
215 IIC_SR>;
195216
196217 let Constraints = "$src1 = $dst" in {
197218 let Uses = [CL] in {
198219 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
199220 "sar{b}\t{%cl, $dst|$dst, CL}",
200 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
221 [(set GR8:$dst, (sra GR8:$src1, CL))],
222 IIC_SR>;
201223 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
202224 "sar{w}\t{%cl, $dst|$dst, CL}",
203 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
225 [(set GR16:$dst, (sra GR16:$src1, CL))],
226 IIC_SR>, OpSize;
204227 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
205228 "sar{l}\t{%cl, $dst|$dst, CL}",
206 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
229 [(set GR32:$dst, (sra GR32:$src1, CL))],
230 IIC_SR>;
207231 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
208232 "sar{q}\t{%cl, $dst|$dst, CL}",
209 [(set GR64:$dst, (sra GR64:$src1, CL))]>;
233 [(set GR64:$dst, (sra GR64:$src1, CL))],
234 IIC_SR>;
210235 }
211236
212237 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
213238 "sar{b}\t{$src2, $dst|$dst, $src2}",
214 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
239 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
240 IIC_SR>;
215241 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
216242 "sar{w}\t{$src2, $dst|$dst, $src2}",
217 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
243 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
244 IIC_SR>,
218245 OpSize;
219246 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
220247 "sar{l}\t{$src2, $dst|$dst, $src2}",
221 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
248 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
249 IIC_SR>;
222250 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
223251 (ins GR64:$src1, i8imm:$src2),
224252 "sar{q}\t{$src2, $dst|$dst, $src2}",
225 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
253 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
254 IIC_SR>;
226255
227256 // Shift by 1
228257 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
229258 "sar{b}\t$dst",
230 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
259 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
260 IIC_SR>;
231261 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
232262 "sar{w}\t$dst",
233 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
263 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
264 IIC_SR>, OpSize;
234265 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
235266 "sar{l}\t$dst",
236 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
267 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
268 IIC_SR>;
237269 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
238270 "sar{q}\t$dst",
239 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
271 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
272 IIC_SR>;
240273 } // Constraints = "$src = $dst"
241274
242275
243276 let Uses = [CL] in {
244277 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
245278 "sar{b}\t{%cl, $dst|$dst, CL}",
246 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
279 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
280 IIC_SR>;
247281 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
248282 "sar{w}\t{%cl, $dst|$dst, CL}",
249 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
283 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
284 IIC_SR>, OpSize;
250285 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
251286 "sar{l}\t{%cl, $dst|$dst, CL}",
252 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
287 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
288 IIC_SR>;
253289 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
254290 "sar{q}\t{%cl, $dst|$dst, CL}",
255 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
291 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
292 IIC_SR>;
256293 }
257294 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
258295 "sar{b}\t{$src, $dst|$dst, $src}",
259 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
296 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
297 IIC_SR>;
260298 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
261299 "sar{w}\t{$src, $dst|$dst, $src}",
262 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
300 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
301 IIC_SR>,
263302 OpSize;
264303 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
265304 "sar{l}\t{$src, $dst|$dst, $src}",
266 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
305 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
306 IIC_SR>;
267307 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
268308 "sar{q}\t{$src, $dst|$dst, $src}",
269 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
309 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
310 IIC_SR>;
270311
271312 // Shift by 1
272313 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
273314 "sar{b}\t$dst",
274 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
315 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)],
316 IIC_SR>;
275317 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
276318 "sar{w}\t$dst",
277 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
319 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
320 IIC_SR>,
278321 OpSize;
279322 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
280323 "sar{l}\t$dst",
281 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
324 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
325 IIC_SR>;
282326 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
283327 "sar{q}\t$dst",
284 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
328 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
329 IIC_SR>;
285330
286331 //===----------------------------------------------------------------------===//
287332 // Rotate instructions
289334
290335 let Constraints = "$src1 = $dst" in {
291336 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
292 "rcl{b}\t$dst", []>;
337 "rcl{b}\t$dst", [], IIC_SR>;
293338 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
294 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
339 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
295340 let Uses = [CL] in
296341 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
297 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
342 "rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
298343
299344 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
300 "rcl{w}\t$dst", []>, OpSize;
345 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
301346 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
302 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
347 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
303348 let Uses = [CL] in
304349 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
305 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
350 "rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
306351
307352 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
308 "rcl{l}\t$dst", []>;
353 "rcl{l}\t$dst", [], IIC_SR>;
309354 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
310 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
355 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
311356 let Uses = [CL] in
312357 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
313 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
358 "rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
314359
315360
316361 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
317 "rcl{q}\t$dst", []>;
362 "rcl{q}\t$dst", [], IIC_SR>;
318363 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
319 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
364 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
320365 let Uses = [CL] in
321366 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
322 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
367 "rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
323368
324369
325370 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
326 "rcr{b}\t$dst", []>;
371 "rcr{b}\t$dst", [], IIC_SR>;
327372 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
328 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
373 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
329374 let Uses = [CL] in
330375 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
331 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
376 "rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
332377
333378 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
334 "rcr{w}\t$dst", []>, OpSize;
379 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
335380 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
336 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
381 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
337382 let Uses = [CL] in
338383 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
339 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
384 "rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
340385
341386 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
342 "rcr{l}\t$dst", []>;
387 "rcr{l}\t$dst", [], IIC_SR>;
343388 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
344 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
389 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
345390 let Uses = [CL] in
346391 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
347 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
392 "rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
348393
349394 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
350 "rcr{q}\t$dst", []>;
395 "rcr{q}\t$dst", [], IIC_SR>;
351396 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
352 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
397 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
353398 let Uses = [CL] in
354399 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
355 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
400 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
356401
357402 } // Constraints = "$src = $dst"
358403
359404 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
360 "rcl{b}\t$dst", []>;
405 "rcl{b}\t$dst", [], IIC_SR>;
361406 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
362 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
407 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
363408 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
364 "rcl{w}\t$dst", []>, OpSize;
409 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
365410 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
366 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
411 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
367412 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
368 "rcl{l}\t$dst", []>;
413 "rcl{l}\t$dst", [], IIC_SR>;
369414 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
370 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
415 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
371416 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
372 "rcl{q}\t$dst", []>;
417 "rcl{q}\t$dst", [], IIC_SR>;
373418 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
374 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
419 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
375420
376421 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
377 "rcr{b}\t$dst", []>;
422 "rcr{b}\t$dst", [], IIC_SR>;
378423 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
379 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
424 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
380425 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
381 "rcr{w}\t$dst", []>, OpSize;
426 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
382427 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
383 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
428 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
384429 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
385 "rcr{l}\t$dst", []>;
430 "rcr{l}\t$dst", [], IIC_SR>;
386431 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
387 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
432 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
388433 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
389 "rcr{q}\t$dst", []>;
434 "rcr{q}\t$dst", [], IIC_SR>;
390435 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
391 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
436 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
392437
393438 let Uses = [CL] in {
394439 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
395 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
440 "rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
396441 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
397 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
442 "rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
398443 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
399 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
444 "rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
400445 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
401 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
446 "rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
402447
403448 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
404 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
449 "rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
405450 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
406 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
451 "rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
407452 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
408 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
453 "rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
409454 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
410 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
455 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
411456 }
412457
413458 let Constraints = "$src1 = $dst" in {
415460 let Uses = [CL] in {
416461 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
417462 "rol{b}\t{%cl, $dst|$dst, CL}",
418 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
463 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
419464 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
420465 "rol{w}\t{%cl, $dst|$dst, CL}",
421 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
466 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize;
422467 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
423468 "rol{l}\t{%cl, $dst|$dst, CL}",
424 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
469 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>;
425470 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
426471 "rol{q}\t{%cl, $dst|$dst, CL}",
427 [(set GR64:$dst, (rotl GR64:$src1, CL))]>;
472 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
428473 }
429474
430475 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
431476 "rol{b}\t{$src2, $dst|$dst, $src2}",
432 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
477 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
433478 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
434479 "rol{w}\t{$src2, $dst|$dst, $src2}",
435 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
480 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
481 IIC_SR>,
436482 OpSize;
437483 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
438484 "rol{l}\t{$src2, $dst|$dst, $src2}",
439 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
485 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
486 IIC_SR>;
440487 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
441488 (ins GR64:$src1, i8imm:$src2),
442489 "rol{q}\t{$src2, $dst|$dst, $src2}",
443 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
490 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
491 IIC_SR>;
444492
445493 // Rotate by 1
446494 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
447495 "rol{b}\t$dst",
448 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
496 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
497 IIC_SR>;
449498 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
450499 "rol{w}\t$dst",
451 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
500 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
501 IIC_SR>, OpSize;
452502 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
453503 "rol{l}\t$dst",
454 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
504 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
505 IIC_SR>;
455506 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
456507 "rol{q}\t$dst",
457 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
508 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
509 IIC_SR>;
458510 } // Constraints = "$src = $dst"
459511
460512 let Uses = [CL] in {
461513 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
462514 "rol{b}\t{%cl, $dst|$dst, CL}",
463 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
515 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
516 IIC_SR>;
464517 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
465518 "rol{w}\t{%cl, $dst|$dst, CL}",
466 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
519 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
520 IIC_SR>, OpSize;
467521 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
468522 "rol{l}\t{%cl, $dst|$dst, CL}",
469 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
523 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
524 IIC_SR>;
470525 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
471526 "rol{q}\t{%cl, $dst|$dst, %cl}",
472 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
527 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
528 IIC_SR>;
473529 }
474530 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1),
475531 "rol{b}\t{$src1, $dst|$dst, $src1}",
476 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
532 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)],
533 IIC_SR>;
477534 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),
478535 "rol{w}\t{$src1, $dst|$dst, $src1}",
479 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)]>,
536 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
537 IIC_SR>,
480538 OpSize;
481539 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
482540 "rol{l}\t{$src1, $dst|$dst, $src1}",
483 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
541 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
542 IIC_SR>;
484543 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
485544 "rol{q}\t{$src1, $dst|$dst, $src1}",
486 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
545 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
546 IIC_SR>;
487547
488548 // Rotate by 1
489549 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
490550 "rol{b}\t$dst",
491 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
551 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
552 IIC_SR>;
492553 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
493554 "rol{w}\t$dst",
494 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
555 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
556 IIC_SR>,
495557 OpSize;
496558 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
497559 "rol{l}\t$dst",
498 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
560 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
561 IIC_SR>;
499562 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
500563 "rol{q}\t$dst",
501 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
564 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
565 IIC_SR>;
502566
503567 let Constraints = "$src1 = $dst" in {
504568 let Uses = [CL] in {
505569 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
506570 "ror{b}\t{%cl, $dst|$dst, CL}",
507 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
571 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
508572 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
509573 "ror{w}\t{%cl, $dst|$dst, CL}",
510 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
574 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize;
511575 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
512576 "ror{l}\t{%cl, $dst|$dst, CL}",
513 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
577 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>;
514578 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
515579 "ror{q}\t{%cl, $dst|$dst, CL}",
516 [(set GR64:$dst, (rotr GR64:$src1, CL))]>;
580 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
517581 }
518582
519583 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
520584 "ror{b}\t{$src2, $dst|$dst, $src2}",
521 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
585 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
522586 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
523587 "ror{w}\t{$src2, $dst|$dst, $src2}",
524 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
588 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
589 IIC_SR>,
525590 OpSize;
526591 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
527592 "ror{l}\t{$src2, $dst|$dst, $src2}",
528 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
593 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
594 IIC_SR>;
529595 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
530596 (ins GR64:$src1, i8imm:$src2),
531597 "ror{q}\t{$src2, $dst|$dst, $src2}",
532 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
598 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))],
599 IIC_SR>;
533600
534601 // Rotate by 1
535602 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
536603 "ror{b}\t$dst",
537 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
604 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))],
605 IIC_SR>;
538606 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
539607 "ror{w}\t$dst",
540 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
608 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))],
609 IIC_SR>, OpSize;
541610 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
542611 "ror{l}\t$dst",
543 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
612 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
613 IIC_SR>;
544614 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
545615 "ror{q}\t$dst",
546 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
616 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
617 IIC_SR>;
547618 } // Constraints = "$src = $dst"
548619
549620 let Uses = [CL] in {
550621 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
551622 "ror{b}\t{%cl, $dst|$dst, CL}",
552 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
623 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
624 IIC_SR>;
553625 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
554626 "ror{w}\t{%cl, $dst|$dst, CL}",
555 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
627 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
628 IIC_SR>, OpSize;
556629 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
557630 "ror{l}\t{%cl, $dst|$dst, CL}",
558 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
631 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
632 IIC_SR>;
559633 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
560634 "ror{q}\t{%cl, $dst|$dst, CL}",
561 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
635 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
636 IIC_SR>;
562637 }
563638 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
564639 "ror{b}\t{$src, $dst|$dst, $src}",
565 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
640 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
641 IIC_SR>;
566642 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
567643 "ror{w}\t{$src, $dst|$dst, $src}",
568 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
644 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
645 IIC_SR>,
569646 OpSize;
570647 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
571648 "ror{l}\t{$src, $dst|$dst, $src}",
572 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
649 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
650 IIC_SR>;
573651 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
574652 "ror{q}\t{$src, $dst|$dst, $src}",
575 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
653 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
654 IIC_SR>;
576655
577656 // Rotate by 1
578657 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
579658 "ror{b}\t$dst",
580 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
659 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)],
660 IIC_SR>;
581661 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
582662 "ror{w}\t$dst",
583 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
663 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
664 IIC_SR>,
584665 OpSize;
585666 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
586667 "ror{l}\t$dst",
587 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
668 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
669 IIC_SR>;
588670 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
589671 "ror{q}\t$dst",
590 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
672 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
673 IIC_SR>;
591674
592675
593676 //===----------------------------------------------------------------------===//
600683 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
601684 (ins GR16:$src1, GR16:$src2),
602685 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
603 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
686 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
687 IIC_SHD16_REG_CL>,
604688 TB, OpSize;
605689 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
606690 (ins GR16:$src1, GR16:$src2),
607691 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
608 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
692 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
693 IIC_SHD16_REG_CL>,
609694 TB, OpSize;
610695 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
611696 (ins GR32:$src1, GR32:$src2),
612697 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
613 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
698 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
699 IIC_SHD32_REG_CL>, TB;
614700 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
615701 (ins GR32:$src1, GR32:$src2),
616702 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
617 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
703 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
704 IIC_SHD32_REG_CL>, TB;
618705 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
619706 (ins GR64:$src1, GR64:$src2),
620707 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
621 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
708 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
709 IIC_SHD64_REG_CL>,
622710 TB;
623711 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
624712 (ins GR64:$src1, GR64:$src2),
625713 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
626 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
714 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
715 IIC_SHD64_REG_CL>,
627716 TB;
628717 }
629718
633722 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
634723 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
635724 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
636 (i8 imm:$src3)))]>,
725 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
637726 TB, OpSize;
638727 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
639728 (outs GR16:$dst),
640729 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
641730 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
642731 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
643 (i8 imm:$src3)))]>,
732 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
644733 TB, OpSize;
645734 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
646735 (outs GR32:$dst),
647736 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
648737 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
649738 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
650 (i8 imm:$src3)))]>,
739 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
651740 TB;
652741 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
653742 (outs GR32:$dst),
654743 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
655744 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
656745 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
657 (i8 imm:$src3)))]>,
746 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
658747 TB;
659748 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
660749 (outs GR64:$dst),
661750 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
662751 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
663752 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
664 (i8 imm:$src3)))]>,
753 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
665754 TB;
666755 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
667756 (outs GR64:$dst),
668757 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
669758 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
670759 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
671 (i8 imm:$src3)))]>,
760 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
672761 TB;
673762 }
674763 } // Constraints = "$src = $dst"
677766 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
678767 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
679768 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
680 addr:$dst)]>, TB, OpSize;
769 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
681770 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
682771 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
683772 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
684 addr:$dst)]>, TB, OpSize;
773 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
685774
686775 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
687776 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
688777 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
689 addr:$dst)]>, TB;
778 addr:$dst)], IIC_SHD32_MEM_CL>, TB;
690779 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
691780 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
692781 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
693 addr:$dst)]>, TB;
782 addr:$dst)], IIC_SHD32_MEM_CL>, TB;
694783
695784 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
696785 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
697786 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
698 addr:$dst)]>, TB;
787 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
699788 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
700789 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
701790 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
702 addr:$dst)]>, TB;
791 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
703792 }
704793
705794 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
706795 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
707796 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
708797 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
709 (i8 imm:$src3)), addr:$dst)]>,
798 (i8 imm:$src3)), addr:$dst)],
799 IIC_SHD16_MEM_IM>,
710800 TB, OpSize;
711801 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
712802 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
713803 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
714804 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
715 (i8 imm:$src3)), addr:$dst)]>,
805 (i8 imm:$src3)), addr:$dst)],
806 IIC_SHD16_MEM_IM>,
716807 TB, OpSize;
717808
718809 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
719810 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
720811 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
721812 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
722 (i8 imm:$src3)), addr:$dst)]>,
813 (i8 imm:$src3)), addr:$dst)],
814 IIC_SHD32_MEM_IM>,
723815 TB;
724816 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
725817 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
726818 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
727819 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
728 (i8 imm:$src3)), addr:$dst)]>,
820 (i8 imm:$src3)), addr:$dst)],
821 IIC_SHD32_MEM_IM>,
729822 TB;
730823
731824 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
732825 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
733826 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
734827 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
735 (i8 imm:$src3)), addr:$dst)]>,
828 (i8 imm:$src3)), addr:$dst)],
829 IIC_SHD64_MEM_IM>,
736830 TB;
737831 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
738832 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
739833 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
740834 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
741 (i8 imm:$src3)), addr:$dst)]>,
835 (i8 imm:$src3)), addr:$dst)],
836 IIC_SHD64_MEM_IM>,
742837 TB;
743838
744839 } // Defs = [EFLAGS]
0 //===- X86Schedule.td - X86 Scheduling Definitions ---------*- tablegen -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 //===----------------------------------------------------------------------===//
10 // Instruction Itinerary classes used for X86
11 def IIC_DEFAULT : InstrItinClass;
12 def IIC_ALU_MEM : InstrItinClass;
13 def IIC_ALU_NONMEM : InstrItinClass;
14 def IIC_LEA : InstrItinClass;
15 def IIC_LEA_16 : InstrItinClass;
16 def IIC_MUL8 : InstrItinClass;
17 def IIC_MUL16_MEM : InstrItinClass;
18 def IIC_MUL16_REG : InstrItinClass;
19 def IIC_MUL32_MEM : InstrItinClass;
20 def IIC_MUL32_REG : InstrItinClass;
21 def IIC_MUL64 : InstrItinClass;
22 // imul by al, ax, eax, tax
23 def IIC_IMUL8 : InstrItinClass;
24 def IIC_IMUL16_MEM : InstrItinClass;
25 def IIC_IMUL16_REG : InstrItinClass;
26 def IIC_IMUL32_MEM : InstrItinClass;
27 def IIC_IMUL32_REG : InstrItinClass;
28 def IIC_IMUL64 : InstrItinClass;
29 // imul reg by reg|mem
30 def IIC_IMUL16_RM : InstrItinClass;
31 def IIC_IMUL16_RR : InstrItinClass;
32 def IIC_IMUL32_RM : InstrItinClass;
33 def IIC_IMUL32_RR : InstrItinClass;
34 def IIC_IMUL64_RM : InstrItinClass;
35 def IIC_IMUL64_RR : InstrItinClass;
36 // imul reg = reg/mem * imm
37 def IIC_IMUL16_RMI : InstrItinClass;
38 def IIC_IMUL16_RRI : InstrItinClass;
39 def IIC_IMUL32_RMI : InstrItinClass;
40 def IIC_IMUL32_RRI : InstrItinClass;
41 def IIC_IMUL64_RMI : InstrItinClass;
42 def IIC_IMUL64_RRI : InstrItinClass;
43 // div
44 def IIC_DIV8_MEM : InstrItinClass;
45 def IIC_DIV8_REG : InstrItinClass;
46 def IIC_DIV16 : InstrItinClass;
47 def IIC_DIV32 : InstrItinClass;
48 def IIC_DIV64 : InstrItinClass;
49 // idiv
50 def IIC_IDIV8 : InstrItinClass;
51 def IIC_IDIV16 : InstrItinClass;
52 def IIC_IDIV32 : InstrItinClass;
53 def IIC_IDIV64 : InstrItinClass;
54 // neg/not/inc/dec
55 def IIC_UNARY_REG : InstrItinClass;
56 def IIC_UNARY_MEM : InstrItinClass;
57 // add/sub/and/or/xor/adc/sbc/cmp/test
58 def IIC_BIN_MEM : InstrItinClass;
59 def IIC_BIN_NONMEM : InstrItinClass;
60 // shift/rotate
61 def IIC_SR : InstrItinClass;
62 // shift double
63 def IIC_SHD16_REG_IM : InstrItinClass;
64 def IIC_SHD16_REG_CL : InstrItinClass;
65 def IIC_SHD16_MEM_IM : InstrItinClass;
66 def IIC_SHD16_MEM_CL : InstrItinClass;
67 def IIC_SHD32_REG_IM : InstrItinClass;
68 def IIC_SHD32_REG_CL : InstrItinClass;
69 def IIC_SHD32_MEM_IM : InstrItinClass;
70 def IIC_SHD32_MEM_CL : InstrItinClass;
71 def IIC_SHD64_REG_IM : InstrItinClass;
72 def IIC_SHD64_REG_CL : InstrItinClass;
73 def IIC_SHD64_MEM_IM : InstrItinClass;
74 def IIC_SHD64_MEM_CL : InstrItinClass;
75 // cmov
76 def IIC_CMOV16_RM : InstrItinClass;
77 def IIC_CMOV16_RR : InstrItinClass;
78 def IIC_CMOV32_RM : InstrItinClass;
79 def IIC_CMOV32_RR : InstrItinClass;
80 def IIC_CMOV64_RM : InstrItinClass;
81 def IIC_CMOV64_RR : InstrItinClass;
82 // set
83 def IIC_SET_R : InstrItinClass;
84 def IIC_SET_M : InstrItinClass;
85 // jmp/jcc/jcxz
86 def IIC_Jcc : InstrItinClass;
87 def IIC_JCXZ : InstrItinClass;
88 def IIC_JMP_REL : InstrItinClass;
89 def IIC_JMP_REG : InstrItinClass;
90 def IIC_JMP_MEM : InstrItinClass;
91 def IIC_JMP_FAR_MEM : InstrItinClass;
92 def IIC_JMP_FAR_PTR : InstrItinClass;
93 // loop
94 def IIC_LOOP : InstrItinClass;
95 def IIC_LOOPE : InstrItinClass;
96 def IIC_LOOPNE : InstrItinClass;
97 // call
98 def IIC_CALL_RI : InstrItinClass;
99 def IIC_CALL_MEM : InstrItinClass;
100 def IIC_CALL_FAR_MEM : InstrItinClass;
101 def IIC_CALL_FAR_PTR : InstrItinClass;
102 // ret
103 def IIC_RET : InstrItinClass;
104 def IIC_RET_IMM : InstrItinClass;
105
106 //===----------------------------------------------------------------------===//
107 // Processor instruction itineraries.
108
109 def GenericItineraries : ProcessorItineraries<[], [], []>;
110
111 include "X86ScheduleAtom.td"
112
113
114
0 //=- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the itinerary class data for the Intel Atom (Bonnell)
10 // processors.
11 //
12 //===----------------------------------------------------------------------===//
13
14 //
15 // Scheduling information derived from the "Intel 64 and IA32 Architectures
16 // Optimization Reference Manual", Chapter 13, Section 4.
17 // Functional Units
18 // Port 0
19 def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store
20 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
21 def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
22 // SIMD/FP: SIMD ALU, FP Adder
23
24 def AtomItineraries : ProcessorItineraries<
25 [ Port0, Port1 ],
26 [], [
27 // P0 only
28 // InstrItinData] >,
29 // P0 or P1
30 // InstrItinData] >,
31 // P0 and P1
32 // InstrItinData, InstrStage] >,
33 //
34 // Default is 1 cycle, port0 or port1
35 InstrItinData] >,
36 InstrItinData] >,
37 InstrItinData] >,
38 InstrItinData] >,
39 InstrItinData] >,
40 // mul
41 InstrItinData] >,
42 InstrItinData] >,
43 InstrItinData] >,
44 InstrItinData] >,
45 InstrItinData] >,
46 InstrItinData] >,
47 // imul by al, ax, eax, rax
48 InstrItinData] >,
49 InstrItinData] >,
50 InstrItinData] >,
51 InstrItinData] >,
52 InstrItinData] >,
53 InstrItinData] >,
54 // imul reg by reg|mem
55 InstrItinData] >,
56 InstrItinData] >,
57 InstrItinData] >,
58 InstrItinData] >,
59 InstrItinData] >,
60 InstrItinData] >,
61 // imul reg = reg/mem * imm
62 InstrItinData] >,
63 InstrItinData] >,
64 InstrItinData] >,
65 InstrItinData] >,
66 InstrItinData] >,
67 InstrItinData] >,
68 // idiv
69 InstrItinData] >,
70 InstrItinData] >,
71 InstrItinData] >,
72 InstrItinData] >,
73 // div
74 InstrItinData] >,
75 InstrItinData] >,
76 InstrItinData] >,
77 InstrItinData] >,
78 InstrItinData] >,
79 // neg/not/inc/dec
80 InstrItinData] >,
81 InstrItinData] >,
82 // add/sub/and/or/xor/adc/sbc/cmp/test
83 InstrItinData] >,
84 InstrItinData] >,
85 // shift/rotate
86 InstrItinData] >,
87 // shift double
88 InstrItinData] >,
89 InstrItinData] >,
90 InstrItinData] >,
91 InstrItinData] >,
92 InstrItinData] >,
93 InstrItinData] >,
94 InstrItinData] >,
95 InstrItinData] >,
96 InstrItinData] >,
97 InstrItinData] >,
98 InstrItinData] >,
99 InstrItinData] >,
100 // cmov
101 InstrItinData] >,
102 InstrItinData] >,
103 InstrItinData] >,
104 InstrItinData] >,
105 InstrItinData] >,
106 InstrItinData] >,
107 // set
108 InstrItinData] >,
109 InstrItinData] >,
110 // jcc
111 InstrItinData] >,
112 // jcxz/jecxz/jrcxz
113 InstrItinData] >,
114 // jmp rel
115 InstrItinData] >,
116 // jmp indirect
117 InstrItinData] >,
118 InstrItinData] >,
119 // jmp far
120 InstrItinData] >,
121 InstrItinData] >,
122 // loop/loope/loopne
123 InstrItinData] >,
124 InstrItinData] >,
125 InstrItinData] >,
126 // call - all but reg/imm
127 InstrItinData, InstrStage<1, [Port1]>] >,
128 InstrItinData] >,
129 InstrItinData] >,
130 InstrItinData] >,
131 //ret
132 InstrItinData] >,
133 InstrItinData, InstrStage<1, [Port1]>] >
134 ]>;
135
245245 IsBTMemSlow = true;
246246 ToggleFeature(X86::FeatureSlowBTMem);
247247 }
248
248249 // If it's Nehalem, unaligned memory access is fast.
249250 // FIXME: Nehalem is family 6. Also include Westmere and later processors?
250251 if (Family == 15 && Model == 26) {
251252 IsUAMemFast = true;
252253 ToggleFeature(X86::FeatureFastUAMem);
254 }
255
256 // Set processor type. Currently only Atom is detected.
257 if (Family == 6 && Model == 28) {
258 X86ProcFamily = IntelAtom;
253259 }
254260
255261 unsigned MaxExtLevel;
309315 const std::string &FS,
310316 unsigned StackAlignOverride, bool is64Bit)
311317 : X86GenSubtargetInfo(TT, CPU, FS)
318 , X86ProcFamily(Others)
312319 , PICStyle(PICStyles::None)
313320 , X86SSELevel(NoMMXSSE)
314321 , X863DNowLevel(NoThreeDNow)
332339 , IsUAMemFast(false)
333340 , HasVectorUAMem(false)
334341 , HasCmpxchg16b(false)
342 , PostRAScheduler(false)
335343 , stackAlignment(4)
336344 // FIXME: this is a known good value for Yonah. How about others?
337345 , MaxInlineSizeThreshold(128)
338346 , TargetTriple(TT)
339347 , In64BitMode(is64Bit) {
340348 // Determine default and user specified characteristics
349 std::string CPUName = CPU;
341350 if (!FS.empty() || !CPU.empty()) {
342 std::string CPUName = CPU;
343351 if (CPUName.empty()) {
344352 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
345353 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
362370 // If feature string is not empty, parse features string.
363371 ParseSubtargetFeatures(CPUName, FullFS);
364372 } else {
373 if (CPUName.empty()) {
374 #if defined (__x86_64__) || defined(__i386__)
375 CPUName = sys::getHostCPUName();
376 #else
377 CPUName = "generic";
378 #endif
379 }
365380 // Otherwise, use CPUID to auto-detect feature set.
366381 AutoDetectSubtargetFeatures();
367382
376391 ToggleFeature(X86::FeatureSSE2);
377392 }
378393 }
394 }
395
396 if (X86ProcFamily == IntelAtom) {
397 PostRAScheduler = true;
398 InstrItins = getInstrItineraryForCPU(CPUName);
379399 }
380400
381401 // It's important to keep the MCSubtargetInfo feature bits in sync with
397417 isTargetSolaris() || In64BitMode)
398418 stackAlignment = 16;
399419 }
420
421 bool X86Subtarget::enablePostRAScheduler(
422 CodeGenOpt::Level OptLevel,
423 TargetSubtargetInfo::AntiDepBreakMode& Mode,
424 RegClassVector& CriticalPathRCs) const {
425 Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
426 CriticalPathRCs.clear();
427 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
428 }
4848 NoThreeDNow, ThreeDNow, ThreeDNowA
4949 };
5050