llvm.org GIT mirror llvm / 91abace
add a gross hack to work around a problem that Argiris reported on llvmdev: SRoA is introducing MMX datatypes like <1 x i64>, which then cause random problems because the X86 backend is producing mmx stuff without inserting proper emms calls. In the short term, force off MMX datatypes. In the long term, the X86 backend should not select generic vector types to MMX registers. This is being worked on, but won't be done in time for 2.8. rdar://8380055 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112696 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 9 years ago
2 changed file(s) with 40 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
192192 };
193193 } // end anonymous namespace.
194194
195
196 /// IsVerbotenVectorType - Return true if this is a vector type ScalarRepl isn't
197 /// allowed to form. We do this to avoid MMX types, which is a complete hack,
198 /// but is required until the backend is fixed.
199 static bool IsVerbotenVectorType(const VectorType *VTy) {
200 // Reject all the MMX vector types.
201 switch (VTy->getNumElements()) {
202 default: return false;
203 case 1: return VTy->getElementType()->isIntegerTy(64);
204 case 2: return VTy->getElementType()->isIntegerTy(32);
205 case 4: return VTy->getElementType()->isIntegerTy(16);
206 case 8: return VTy->getElementType()->isIntegerTy(8);
207 }
208 }
209
210
195211 /// TryConvert - Analyze the specified alloca, and if it is safe to do so,
196212 /// rewrite it to be a new alloca which is mem2reg'able. This returns the new
197213 /// alloca if possible or null if not.
208224 // we just get a lot of insert/extracts. If at least one vector is
209225 // involved, then we probably really do have a union of vector/array.
210226 const Type *NewTy;
211 if (VectorTy && VectorTy->isVectorTy() && HadAVector) {
227 if (VectorTy && VectorTy->isVectorTy() && HadAVector &&
228 !IsVerbotenVectorType(cast(VectorTy))) {
212229 DEBUG(dbgs() << "CONVERT TO VECTOR: " << *AI << "\n TYPE = "
213230 << *VectorTy << '\n');
214231 NewTy = VectorTy; // Use the vector type.
16611678 /// HasPadding - Return true if the specified type has any structure or
16621679 /// alignment padding, false otherwise.
16631680 static bool HasPadding(const Type *Ty, const TargetData &TD) {
1681 if (const ArrayType *ATy = dyn_cast(Ty))
1682 return HasPadding(ATy->getElementType(), TD);
1683
1684 if (const VectorType *VTy = dyn_cast(Ty))
1685 return HasPadding(VTy->getElementType(), TD);
1686
16641687 if (const StructType *STy = dyn_cast(Ty)) {
16651688 const StructLayout *SL = TD.getStructLayout(STy);
16661689 unsigned PrevFieldBitOffset = 0;
16901713 if (PrevFieldEnd < SL->getSizeInBits())
16911714 return true;
16921715 }
1693
1694 } else if (const ArrayType *ATy = dyn_cast(Ty)) {
1695 return HasPadding(ATy->getElementType(), TD);
1696 } else if (const VectorType *VTy = dyn_cast(Ty)) {
1697 return HasPadding(VTy->getElementType(), TD);
1698 }
1716 }
1717
16991718 return TD.getTypeSizeInBits(Ty) != TD.getTypeAllocSizeInBits(Ty);
17001719 }
17011720
8484 ; CHECK-NEXT: ret i32
8585 }
8686
87
88 ;; should not turn into <1 x i64> - It is a banned MMX datatype.
89 ;; rdar://8380055
90 define i64 @test6(<2 x float> %X) {
91 %X_addr = alloca <2 x float>
92 store <2 x float> %X, <2 x float>* %X_addr
93 %P = bitcast <2 x float>* %X_addr to i64*
94 %tmp = load i64* %P
95 ret i64 %tmp
96 ; CHECK: @test6
97 ; CHECK-NEXT: bitcast <2 x float> %X to i64
98 ; CHECK-NEXT: ret i64
99 }
100