llvm.org GIT mirror llvm / 913134b
Merging r226711: ------------------------------------------------------------------------ r226711 | jroelofs | 2015-01-21 14:39:43 -0800 (Wed, 21 Jan 2015) | 8 lines Fix load-store optimizer on thumbv4t Thumbv4t does not have lo->lo copies other than MOVS, and that can't be predicated. So emit MOVS when needed and bail if there's a predicate. http://reviews.llvm.org/D6592 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@226918 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 4 years ago
2 changed file(s) with 69 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
566566 // MOV NewBase, Base
567567 // ADDS NewBase, #imm8.
568568 if (Base != NewBase && Offset >= 8) {
569 const ARMSubtarget &Subtarget = MBB.getParent()->getTarget()
570 .getSubtarget();
569571 // Need to insert a MOV to the new base first.
570 BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVr), NewBase)
571 .addReg(Base, getKillRegState(BaseKill))
572 .addImm(Pred).addReg(PredReg);
572 if (isARMLowRegister(NewBase) && isARMLowRegister(Base) &&
573 !Subtarget.hasV6Ops()) {
574 // thumbv4t doesn't have lo->lo copies, and we can't predicate tMOVSr
575 if (Pred != ARMCC::AL)
576 return false;
577 BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVSr), NewBase)
578 .addReg(Base, getKillRegState(BaseKill));
579 } else
580 BuildMI(MBB, MBBI, dl, TII->get(ARM::tMOVr), NewBase)
581 .addReg(Base, getKillRegState(BaseKill))
582 .addImm(Pred).addReg(PredReg);
583
573584 // Set up BaseKill and Base correctly to insert the ADDS/SUBS below.
574585 Base = NewBase;
575586 BaseKill = false;
0 ; RUN: llc -mtriple=thumbv4t-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V4T
1 ; RUN: llc -mtriple=thumbv6m-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V6M
2
3 ; CHECK-LABEL: foo
4 define i32 @foo(i32 %z, ...) #0 {
5 entry:
6 %a = alloca i32, align 4
7 %b = alloca i32, align 4
8 %c = alloca i32, align 4
9 %d = alloca i32, align 4
10 %e = alloca i32, align 4
11 %f = alloca i32, align 4
12 %g = alloca i32, align 4
13 %h = alloca i32, align 4
14
15 store i32 1, i32* %a, align 4
16 store i32 2, i32* %b, align 4
17 store i32 3, i32* %c, align 4
18 store i32 4, i32* %d, align 4
19 store i32 5, i32* %e, align 4
20 store i32 6, i32* %f, align 4
21 store i32 7, i32* %g, align 4
22 store i32 8, i32* %h, align 4
23
24 %0 = load i32* %a, align 4
25 %1 = load i32* %b, align 4
26 %2 = load i32* %c, align 4
27 %3 = load i32* %d, align 4
28 %4 = load i32* %e, align 4
29 %5 = load i32* %f, align 4
30 %6 = load i32* %g, align 4
31 %7 = load i32* %h, align 4
32
33 %add = add nsw i32 %0, %1
34 %add4 = add nsw i32 %add, %2
35 %add5 = add nsw i32 %add4, %3
36 %add6 = add nsw i32 %add5, %4
37 %add7 = add nsw i32 %add6, %5
38 %add8 = add nsw i32 %add7, %6
39 %add9 = add nsw i32 %add8, %7
40
41 %addz = add nsw i32 %add9, %z
42 call void @llvm.va_start(i8* null)
43 ret i32 %addz
44
45 ; CHECK: sub sp, #40
46 ; CHECK-NEXT: add [[BASE:r[0-9]]], sp, #8
47
48 ; CHECK-V4T: movs [[NEWBASE:r[0-9]]], [[BASE]]
49 ; CHECK-V6M: mov [[NEWBASE:r[0-9]]], [[BASE]]
50 ; CHECK-NEXT: adds [[NEWBASE]], #8
51 ; CHECK-NEXT: ldm [[NEWBASE]],
52 }
53
54 declare void @llvm.va_start(i8*) nounwind