llvm.org GIT mirror llvm / 9122396
[PowerPC] Remove need for adjustFixupOffst hack Now that applyFixup understands differently-sized fixups, we can define fixup_ppc_lo16/fixup_ppc_lo16_ds/fixup_ppc_ha16 to properly be 2-byte fixups, applied at an offset of 2 relative to the start of the instruction text. This has the benefit that if we actually need to generate a real relocation record, its address will come out correctly automatically, without having to fiddle with the offset in adjustFixupOffset. Tested on both 64-bit and 32-bit PowerPC, using external and integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181894 91177308-0d34-0410-b5e6-96231b3b80d8 Ulrich Weigand 7 years ago
4 changed file(s) with 52 addition(s) and 66 deletion(s). Raw diff Collapse all Expand all
5656 case FK_Data_1:
5757 return 1;
5858 case FK_Data_2:
59 case PPC::fixup_ppc_ha16:
60 case PPC::fixup_ppc_lo16:
61 case PPC::fixup_ppc_lo16_ds:
5962 return 2;
6063 case FK_Data_4:
6164 case PPC::fixup_ppc_brcond14:
6265 case PPC::fixup_ppc_br24:
63 case PPC::fixup_ppc_ha16:
64 case PPC::fixup_ppc_lo16:
65 case PPC::fixup_ppc_lo16_ds:
6666 return 4;
6767 case FK_Data_8:
6868 return 8;
9999 // name offset bits flags
100100 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
101101 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
102 { "fixup_ppc_lo16", 16, 16, 0 },
103 { "fixup_ppc_ha16", 16, 16, 0 },
104 { "fixup_ppc_lo16_ds", 16, 14, 0 },
102 { "fixup_ppc_lo16", 0, 16, 0 },
103 { "fixup_ppc_ha16", 0, 16, 0 },
104 { "fixup_ppc_lo16_ds", 0, 14, 0 },
105105 { "fixup_ppc_tlsreg", 0, 0, 0 },
106106 { "fixup_ppc_nofixup", 0, 0, 0 }
107107 };
3232 virtual const MCSymbol *undefinedExplicitRelSym(const MCValue &Target,
3333 const MCFixup &Fixup,
3434 bool IsPCRel) const;
35 virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset);
3635
3736 virtual void sortRelocs(const MCAssembler &Asm,
3837 std::vector &Relocs);
239238 return NULL;
240239 }
241240
242 void PPCELFObjectWriter::
243 adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) {
244 switch ((unsigned)Fixup.getKind()) {
245 case PPC::fixup_ppc_ha16:
246 case PPC::fixup_ppc_lo16:
247 case PPC::fixup_ppc_lo16_ds:
248 RelocOffset += 2;
249 break;
250 default:
251 break;
252 }
253 }
254
255241 // The standard sorter only sorts on the r_offset field, but PowerPC can
256242 // have multiple relocations at the same offset. Sort secondarily on the
257243 // relocation type to avoid nondeterminism.
141141 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
142142
143143 // Add a fixup for the branch target.
144 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
144 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
145145 (MCFixupKind)PPC::fixup_ppc_ha16));
146146 return 0;
147147 }
152152 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
153153
154154 // Add a fixup for the branch target.
155 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
155 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
156156 (MCFixupKind)PPC::fixup_ppc_lo16));
157157 return 0;
158158 }
169169 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
170170
171171 // Add a fixup for the displacement field.
172 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
172 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
173173 (MCFixupKind)PPC::fixup_ppc_lo16));
174174 return RegBits;
175175 }
187187 return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits;
188188
189189 // Add a fixup for the displacement field.
190 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
190 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
191191 (MCFixupKind)PPC::fixup_ppc_lo16_ds));
192192 return RegBits;
193193 }
77 # FIXME: .TOC.@tocbase
88
99 # CHECK: li 3, target@l # encoding: [0x38,0x60,A,A]
10 # CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16
11 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
10 # CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
11 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
1212 li 3, target@l
1313
1414 # CHECK: addis 3, 3, target@ha # encoding: [0x3c,0x63,A,A]
15 # CHECK-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_ha16
16 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_HA target 0x0
15 # CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16
16 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
1717 addis 3, 3, target@ha
1818
1919 # CHECK: lis 3, target@ha # encoding: [0x3c,0x60,A,A]
20 # CHECK-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_ha16
21 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_HA target 0x0
20 # CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_ha16
21 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
2222 lis 3, target@ha
2323
2424 # CHECK: addi 4, 3, target@l # encoding: [0x38,0x83,A,A]
25 # CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16
26 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
25 # CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
26 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
2727 addi 4, 3, target@l
2828
2929 # CHECK: lwz 1, target@l(3) # encoding: [0x80,0x23,A,A]
30 # CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16
31 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO target 0x0
30 # CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16
31 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
3232 lwz 1, target@l(3)
3333
3434 # CHECK: ld 1, target@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
35 # CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16_ds
36 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_ADDR16_LO_DS target 0x0
35 # CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_lo16_ds
36 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0
3737 ld 1, target@l(3)
3838
3939 # CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00]
40 # CHECK-NEXT: # fixup A - offset: 0, value: target@toc, kind: fixup_ppc_lo16_ds
41 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS target 0x0
40 # CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_lo16_ds
41 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0
4242 ld 1, target@toc(2)
4343
4444 # CHECK: addis 3, 2, target@toc@ha # encoding: [0x3c,0x62,A,A]
45 # CHECK-NEXT: # fixup A - offset: 0, value: target@toc@ha, kind: fixup_ppc_ha16
46 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA target 0x0
45 # CHECK-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_ha16
46 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0
4747 addis 3, 2, target@toc@ha
4848
4949 # CHECK: addi 4, 3, target@toc@l # encoding: [0x38,0x83,A,A]
50 # CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16
51 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO target 0x0
50 # CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16
51 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
5252 addi 4, 3, target@toc@l
5353
5454 # CHECK: lwz 1, target@toc@l(3) # encoding: [0x80,0x23,A,A]
55 # CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16
56 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO target 0x0
55 # CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16
56 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
5757 lwz 1, target@toc@l(3)
5858
5959 # CHECK: ld 1, target@toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
60 # CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16_ds
61 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS target 0x0
60 # CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_lo16_ds
61 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0
6262 ld 1, target@toc@l(3)
6363
6464 # FIXME: @tls
6565
6666
6767 # CHECK: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A]
68 # CHECK-NEXT: # fixup A - offset: 0, value: target@tprel@ha, kind: fixup_ppc_ha16
69 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA target 0x0
68 # CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_ha16
69 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0
7070 addis 3, 2, target@tprel@ha
7171
7272 # CHECK: addi 3, 3, target@tprel@l # encoding: [0x38,0x63,A,A]
73 # CHECK-NEXT: # fixup A - offset: 0, value: target@tprel@l, kind: fixup_ppc_lo16
74 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO target 0x0
73 # CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_lo16
74 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0
7575 addi 3, 3, target@tprel@l
7676
7777 # CHECK: addis 3, 2, target@dtprel@ha # encoding: [0x3c,0x62,A,A]
78 # CHECK-NEXT: # fixup A - offset: 0, value: target@dtprel@ha, kind: fixup_ppc_ha16
79 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_HA target 0x0
78 # CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_ha16
79 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0
8080 addis 3, 2, target@dtprel@ha
8181
8282 # CHECK: addi 3, 3, target@dtprel@l # encoding: [0x38,0x63,A,A]
83 # CHECK-NEXT: # fixup A - offset: 0, value: target@dtprel@l, kind: fixup_ppc_lo16
84 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_LO target 0x0
83 # CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_lo16
84 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0
8585 addi 3, 3, target@dtprel@l
8686
8787
8888 # CHECK: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A]
89 # CHECK-NEXT: # fixup A - offset: 0, value: target@got@tprel@ha, kind: fixup_ppc_ha16
90 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA target 0x0
89 # CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_ha16
90 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0
9191 addis 3, 2, target@got@tprel@ha
9292
9393 # CHECK: ld 1, target@got@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
94 # CHECK-NEXT: # fixup A - offset: 0, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds
95 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
94 # CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds
95 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
9696 ld 1, target@got@tprel@l(3)
9797
9898
9999 # CHECK: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A]
100 # CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16
101 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA target 0x0
100 # CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16
101 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0
102102 addis 3, 2, target@got@tlsgd@ha
103103
104104 # CHECK: addi 3, 3, target@got@tlsgd@l # encoding: [0x38,0x63,A,A]
105 # CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@l, kind: fixup_ppc_lo16
106 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO target 0x0
105 # CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_lo16
106 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0
107107 addi 3, 3, target@got@tlsgd@l
108108
109109
110110 # CHECK: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A]
111 # CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsld@ha, kind: fixup_ppc_ha16
112 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA target 0x0
111 # CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_ha16
112 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0
113113 addis 3, 2, target@got@tlsld@ha
114114
115115 # CHECK: addi 3, 3, target@got@tlsld@l # encoding: [0x38,0x63,A,A]
116 # CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsld@l, kind: fixup_ppc_lo16
117 # CHECK-REL: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO target 0x0
116 # CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_lo16
117 # CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0
118118 addi 3, 3, target@got@tlsld@l
119119