llvm.org GIT mirror llvm / 9101685
[AMDGPU] Refactor VOP3 instruction TD definitions Differential revision: https://reviews.llvm.org/D24664 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281965 91177308-0d34-0410-b5e6-96231b3b80d8 Valery Pykhtin 4 years ago
6 changed file(s) with 448 addition(s) and 373 deletion(s). Raw diff Collapse all Expand all
4343 >;
4444 } // End SchedRW = [WriteQuarterRate32]
4545
46 //===----------------------------------------------------------------------===//
47 // VOP3 Instructions
48 //===----------------------------------------------------------------------===//
49
50 defm V_MQSAD_U16_U8 : VOP3Inst , "v_mqsad_u16_u8",
51 VOP_I32_I32_I32
52 >;
53
54 defm V_QSAD_PK_U16_U8 : VOP3Inst , "v_qsad_pk_u16_u8",
55 VOP_I64_I64_I32_I64, int_amdgcn_qsad_pk_u16_u8>;
56
57 defm V_MQSAD_U32_U8 : VOP3Inst , "v_mqsad_u32_u8",
58 VOP_V4I32_I64_I32_V4I32, int_amdgcn_mqsad_u32_u8>;
59
60 let isCommutable = 1 in {
61 defm V_MAD_U64_U32 : VOP3Inst , "v_mad_u64_u32",
62 VOP_I64_I32_I32_I64
63 >;
64
65 // XXX - Does this set VCC?
66 defm V_MAD_I64_I32 : VOP3Inst , "v_mad_i64_i32",
67 VOP_I64_I32_I32_I64
68 >;
69 } // End isCommutable = 1
70
7146 } // End SubtargetPredicate = isCIVI
10711071 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
10721072 }
10731073
1074 class VOP3b_Profile : VOPProfile<[vt, vt, vt, vt]> {
1075 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
1076 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod";
1077 }
1078
1079 def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile {
1080 // FIXME: Hack to stop printing _e64
1081 let DstRC = RegisterOperand;
1082 }
1083
1084 def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile {
1085 // FIXME: Hack to stop printing _e64
1086 let DstRC = RegisterOperand;
1087 }
1088
10891074 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
10901075 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
10911076 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
13991384 let DisableDecoder = DisableVIDecoder;
14001385 }
14011386
1402 multiclass VOP3_m pattern,
1403 string opName, int NumSrcArgs, bit HasMods = 1, bit VOP3Only = 0> {
1404
1405 def "" : VOP3_Pseudo ;
1406
1407 def _si : VOP3_Real_si ,
1408 VOP3DisableFields
1409 !if(!eq(NumSrcArgs, 2), 0, 1),
1410 HasMods>;
1411 def _vi : VOP3_Real_vi ,
1412 VOP3DisableFields
1413 !if(!eq(NumSrcArgs, 2), 0, 1),
1414 HasMods>;
1415 }
1416
14171387 multiclass VOP3_1_m
14181388 list pattern, string opName, bit HasMods = 1> {
14191389
16961666 } // End isCodeGenOnly = 0
16971667 }
16981668
1699 multiclass VOP3_Helper
1700 list pat, int NumSrcArgs, bit HasMods,
1701 bit VOP3Only = 0> : VOP3_m <
1702 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods, VOP3Only
1703 >;
1704
1705 multiclass VOP3Inst
1706 SDPatternOperator node = null_frag, bit VOP3Only = 0> :
1707 VOP3_Helper <
1708 op, opName, (outs P.DstRC.RegClass:$vdst), P.Ins64, P.Asm64,
1709 !if(!eq(P.NumSrcArgs, 3),
1710 !if(P.HasModifiers,
1711 [(set P.DstVT:$vdst,
1712 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1713 i1:$clamp, i32:$omod)),
1714 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1715 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1716 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1717 P.Src2VT:$src2))]),
1718 !if(!eq(P.NumSrcArgs, 2),
1719 !if(P.HasModifiers,
1720 [(set P.DstVT:$vdst,
1721 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1722 i1:$clamp, i32:$omod)),
1723 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1724 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1725 /* P.NumSrcArgs == 1 */,
1726 !if(P.HasModifiers,
1727 [(set P.DstVT:$vdst,
1728 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1729 i1:$clamp, i32:$omod))))],
1730 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]))),
1731 P.NumSrcArgs, P.HasModifiers, VOP3Only
1732 >;
1733
1734 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1735 // only VOP instruction that implicitly reads VCC.
1736 multiclass VOP3_VCC_Inst
1737 VOPProfile P,
1738 SDPatternOperator node = null_frag> : VOP3_Helper <
1739 op, opName,
1740 (outs P.DstRC.RegClass:$vdst),
1741 P.Ins64,
1742 "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1743 [(set P.DstVT:$vdst,
1744 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1745 i1:$clamp, i32:$omod)),
1746 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1747 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1748 (i1 VCC)))],
1749 3, 1
1750 >;
1751
1752 multiclass VOP3bInst pattern = [], bit VOP3Only = 0> :
1753 VOP3b_2_3_m <
1754 op, P.Outs64, P.Ins64,
1755 opName#" "#P.Asm64, pattern,
1756 opName, "", 1, 1, VOP3Only
1757 >;
1758
17591669 class Vop3ModPat : Pat<
17601670 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
17611671 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
506506 defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst , "v_cvt_pk_i16_i32",
507507 VOP_I32_I32_I32
508508 >;
509
510 //===----------------------------------------------------------------------===//
511 // VOP3 Instructions
512 //===----------------------------------------------------------------------===//
513
514 let isCommutable = 1 in {
515 defm V_MAD_LEGACY_F32 : VOP3Inst , "v_mad_legacy_f32",
516 VOP_F32_F32_F32_F32
517 >;
518
519 defm V_MAD_F32 : VOP3Inst , "v_mad_f32",
520 VOP_F32_F32_F32_F32, fmad
521 >;
522
523 defm V_MAD_I32_I24 : VOP3Inst , "v_mad_i32_i24",
524 VOP_I32_I32_I32_I32, AMDGPUmad_i24
525 >;
526 defm V_MAD_U32_U24 : VOP3Inst , "v_mad_u32_u24",
527 VOP_I32_I32_I32_I32, AMDGPUmad_u24
528 >;
529 } // End isCommutable = 1
530
531 defm V_CUBEID_F32 : VOP3Inst , "v_cubeid_f32",
532 VOP_F32_F32_F32_F32, int_amdgcn_cubeid
533 >;
534 defm V_CUBESC_F32 : VOP3Inst , "v_cubesc_f32",
535 VOP_F32_F32_F32_F32, int_amdgcn_cubesc
536 >;
537 defm V_CUBETC_F32 : VOP3Inst , "v_cubetc_f32",
538 VOP_F32_F32_F32_F32, int_amdgcn_cubetc
539 >;
540 defm V_CUBEMA_F32 : VOP3Inst , "v_cubema_f32",
541 VOP_F32_F32_F32_F32, int_amdgcn_cubema
542 >;
543
544 defm V_BFE_U32 : VOP3Inst , "v_bfe_u32",
545 VOP_I32_I32_I32_I32, AMDGPUbfe_u32
546 >;
547 defm V_BFE_I32 : VOP3Inst , "v_bfe_i32",
548 VOP_I32_I32_I32_I32, AMDGPUbfe_i32
549 >;
550
551 defm V_BFI_B32 : VOP3Inst , "v_bfi_b32",
552 VOP_I32_I32_I32_I32, AMDGPUbfi
553 >;
554
555 let isCommutable = 1 in {
556 defm V_FMA_F32 : VOP3Inst , "v_fma_f32",
557 VOP_F32_F32_F32_F32, fma
558 >;
559 defm V_FMA_F64 : VOP3Inst , "v_fma_f64",
560 VOP_F64_F64_F64_F64, fma
561 >;
562
563 defm V_LERP_U8 : VOP3Inst , "v_lerp_u8",
564 VOP_I32_I32_I32_I32, int_amdgcn_lerp
565 >;
566 } // End isCommutable = 1
567
568 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>;
569 defm V_ALIGNBIT_B32 : VOP3Inst , "v_alignbit_b32",
570 VOP_I32_I32_I32_I32
571 >;
572 defm V_ALIGNBYTE_B32 : VOP3Inst , "v_alignbyte_b32",
573 VOP_I32_I32_I32_I32
574 >;
575
576 defm V_MIN3_F32 : VOP3Inst , "v_min3_f32",
577 VOP_F32_F32_F32_F32, AMDGPUfmin3>;
578
579 defm V_MIN3_I32 : VOP3Inst , "v_min3_i32",
580 VOP_I32_I32_I32_I32, AMDGPUsmin3
581 >;
582 defm V_MIN3_U32 : VOP3Inst , "v_min3_u32",
583 VOP_I32_I32_I32_I32, AMDGPUumin3
584 >;
585 defm V_MAX3_F32 : VOP3Inst , "v_max3_f32",
586 VOP_F32_F32_F32_F32, AMDGPUfmax3
587 >;
588 defm V_MAX3_I32 : VOP3Inst , "v_max3_i32",
589 VOP_I32_I32_I32_I32, AMDGPUsmax3
590 >;
591 defm V_MAX3_U32 : VOP3Inst , "v_max3_u32",
592 VOP_I32_I32_I32_I32, AMDGPUumax3
593 >;
594 defm V_MED3_F32 : VOP3Inst , "v_med3_f32",
595 VOP_F32_F32_F32_F32, AMDGPUfmed3
596 >;
597 defm V_MED3_I32 : VOP3Inst , "v_med3_i32",
598 VOP_I32_I32_I32_I32, AMDGPUsmed3
599 >;
600 defm V_MED3_U32 : VOP3Inst , "v_med3_u32",
601 VOP_I32_I32_I32_I32, AMDGPUumed3
602 >;
603
604 defm V_SAD_U8 : VOP3Inst , "v_sad_u8",
605 VOP_I32_I32_I32_I32, int_amdgcn_sad_u8>;
606
607 defm V_SAD_HI_U8 : VOP3Inst , "v_sad_hi_u8",
608 VOP_I32_I32_I32_I32, int_amdgcn_sad_hi_u8>;
609
610 defm V_SAD_U16 : VOP3Inst , "v_sad_u16",
611 VOP_I32_I32_I32_I32, int_amdgcn_sad_u16>;
612
613 defm V_SAD_U32 : VOP3Inst , "v_sad_u32",
614 VOP_I32_I32_I32_I32
615 >;
616
617 defm V_CVT_PK_U8_F32 : VOP3Inst, "v_cvt_pk_u8_f32",
618 VOP_I32_F32_I32_I32, int_amdgcn_cvt_pk_u8_f32
619 >;
620
621 //def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>;
622 defm V_DIV_FIXUP_F32 : VOP3Inst <
623 vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
624 >;
625
626 let SchedRW = [WriteDoubleAdd] in {
627
628 defm V_DIV_FIXUP_F64 : VOP3Inst <
629 vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
630 >;
631
632 } // End SchedRW = [WriteDouble]
633
634 let SchedRW = [WriteDoubleAdd] in {
635 let isCommutable = 1 in {
636
637 defm V_ADD_F64 : VOP3Inst , "v_add_f64",
638 VOP_F64_F64_F64, fadd, 1
639 >;
640 defm V_MUL_F64 : VOP3Inst , "v_mul_f64",
641 VOP_F64_F64_F64, fmul, 1
642 >;
643
644 defm V_MIN_F64 : VOP3Inst , "v_min_f64",
645 VOP_F64_F64_F64, fminnum, 1
646 >;
647 defm V_MAX_F64 : VOP3Inst , "v_max_f64",
648 VOP_F64_F64_F64, fmaxnum, 1
649 >;
650
651 } // End isCommutable = 1
652
653 defm V_LDEXP_F64 : VOP3Inst , "v_ldexp_f64",
654 VOP_F64_F64_I32, AMDGPUldexp, 1
655 >;
656
657 } // End let SchedRW = [WriteDoubleAdd]
658
659 let isCommutable = 1, SchedRW = [WriteQuarterRate32] in {
660
661 defm V_MUL_LO_U32 : VOP3Inst , "v_mul_lo_u32",
662 VOP_I32_I32_I32
663 >;
664 defm V_MUL_HI_U32 : VOP3Inst , "v_mul_hi_u32",
665 VOP_I32_I32_I32, mulhu
666 >;
667
668 let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32
669 defm V_MUL_LO_I32 : VOP3Inst , "v_mul_lo_i32",
670 VOP_I32_I32_I32
671 >;
672 }
673
674 defm V_MUL_HI_I32 : VOP3Inst , "v_mul_hi_i32",
675 VOP_I32_I32_I32, mulhs
676 >;
677
678 } // End isCommutable = 1, SchedRW = [WriteQuarterRate32]
679
680 let SchedRW = [WriteFloatFMA, WriteSALU] in {
681 defm V_DIV_SCALE_F32 : VOP3bInst , "v_div_scale_f32",
682 VOP3b_F32_I1_F32_F32_F32, [], 1
683 >;
684 }
685
686 let SchedRW = [WriteDouble, WriteSALU] in {
687 // Double precision division pre-scale.
688 defm V_DIV_SCALE_F64 : VOP3bInst , "v_div_scale_f64",
689 VOP3b_F64_I1_F64_F64_F64, [], 1
690 >;
691 } // End SchedRW = [WriteDouble]
692
693 let isCommutable = 1, Uses = [VCC, EXEC] in {
694
695 let SchedRW = [WriteFloatFMA] in {
696 // v_div_fmas_f32:
697 // result = src0 * src1 + src2
698 // if (vcc)
699 // result *= 2^32
700 //
701 defm V_DIV_FMAS_F32 : VOP3_VCC_Inst , "v_div_fmas_f32",
702 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
703 >;
704 }
705
706 let SchedRW = [WriteDouble] in {
707 // v_div_fmas_f64:
708 // result = src0 * src1 + src2
709 // if (vcc)
710 // result *= 2^64
711 //
712 defm V_DIV_FMAS_F64 : VOP3_VCC_Inst , "v_div_fmas_f64",
713 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
714 >;
715
716 } // End SchedRW = [WriteDouble]
717 } // End isCommutable = 1, Uses = [VCC, EXEC]
718
719 defm V_MSAD_U8 : VOP3Inst , "v_msad_u8",
720 VOP_I32_I32_I32_I32, int_amdgcn_msad_u8>;
721
722 defm V_MQSAD_PK_U16_U8 : VOP3Inst , "v_mqsad_pk_u16_u8",
723 VOP_I64_I64_I32_I64, int_amdgcn_mqsad_pk_u16_u8>;
724
725 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>;
726
727 let SchedRW = [WriteDouble] in {
728 defm V_TRIG_PREOP_F64 : VOP3Inst <
729 vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop
730 >;
731
732 } // End SchedRW = [WriteDouble]
733
734 // These instructions only exist on SI and CI
735 let SubtargetPredicate = isSICI in {
736
737 defm V_LSHL_B64 : VOP3Inst , "v_lshl_b64", VOP_I64_I64_I32>;
738 defm V_LSHR_B64 : VOP3Inst , "v_lshr_b64", VOP_I64_I64_I32>;
739 defm V_ASHR_I64 : VOP3Inst , "v_ashr_i64", VOP_I64_I64_I32>;
740
741 defm V_MULLIT_F32 : VOP3Inst , "v_mullit_f32",
742 VOP_F32_F32_F32_F32>;
743
744 } // End SubtargetPredicate = isSICI
745
746 let SubtargetPredicate = isVI, DisableSIDecoder = 1 in {
747
748 defm V_LSHLREV_B64 : VOP3Inst , "v_lshlrev_b64",
749 VOP_I64_I32_I64
750 >;
751 defm V_LSHRREV_B64 : VOP3Inst , "v_lshrrev_b64",
752 VOP_I64_I32_I64
753 >;
754 defm V_ASHRREV_I64 : VOP3Inst , "v_ashrrev_i64",
755 VOP_I64_I32_I64
756 >;
757
758 } // End SubtargetPredicate = isVI
759509
760510 //===----------------------------------------------------------------------===//
761511 // Pseudo Instructions
7474 } // End isCommutable = 1
7575 defm V_LDEXP_F16 : VOP2Inst , "v_ldexp_f16", VOP_F16_F16_I16>;
7676
77 //===----------------------------------------------------------------------===//
78 // VOP3 Instructions
79 //===----------------------------------------------------------------------===//
80 let isCommutable = 1 in {
81 defm V_MAD_F16 : VOP3Inst , "v_mad_f16", VOP_F16_F16_F16_F16>;
82 defm V_MAD_U16 : VOP3Inst , "v_mad_u16", VOP_I16_I16_I16_I16>;
83 defm V_MAD_I16 : VOP3Inst , "v_mad_i16", VOP_I16_I16_I16_I16>;
84 }
8577 } // let DisableSIDecoder = 1
8678
8779 // Aliases to simplify matching of floating-point instructions that
0 //===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 //===----------------------------------------------------------------------===//
10 // VOP3 Classes
11 //===----------------------------------------------------------------------===//
12
13 class getVOP3ModPat {
14 list ret3 = [(set P.DstVT:$vdst,
15 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
16 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
17 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))];
18
19 list ret2 = [(set P.DstVT:$vdst,
20 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
21 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];
22
23 list ret1 = [(set P.DstVT:$vdst,
24 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))];
25
26 list ret = !if(!eq(P.NumSrcArgs, 3), ret3,
27 !if(!eq(P.NumSrcArgs, 2), ret2,
28 ret1));
29 }
30
31 class getVOP3Pat {
32 list ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
33 list ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
34 list ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0))];
35 list ret = !if(!eq(P.NumSrcArgs, 3), ret3,
36 !if(!eq(P.NumSrcArgs, 2), ret2,
37 ret1));
38 }
39
40 class VOP3Inst :
41 VOP3_PseudoNew
42 !if(P.HasModifiers, getVOP3ModPat.ret, getVOP3Pat.ret),
43 VOP3Only>;
44
45 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
46 // only VOP instruction that implicitly reads VCC.
47 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
48 def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> {
49 let Outs64 = (outs DstRC.RegClass:$vdst);
50 }
51 def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> {
52 let Outs64 = (outs DstRC.RegClass:$vdst);
53 }
54 }
55
56 class getVOP3VCC {
57 list ret =
58 [(set P.DstVT:$vdst,
59 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
60 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
61 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
62 (i1 VCC)))];
63 }
64
65 class VOP3_Profile : VOPProfile {
66 // FIXME: Hack to stop printing _e64
67 let Outs64 = (outs DstRC.RegClass:$vdst);
68 let Asm64 = " " # P.Asm64;
69 }
70
71 class VOP3b_Profile : VOPProfile<[vt, vt, vt, vt]> {
72 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
73 let Asm64 = " $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod";
74 }
75
76 def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile {
77 // FIXME: Hack to stop printing _e64
78 let DstRC = RegisterOperand;
79 }
80
81 def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile {
82 // FIXME: Hack to stop printing _e64
83 let DstRC = RegisterOperand;
84 }
85
86 //===----------------------------------------------------------------------===//
87 // VOP3 Instructions
88 //===----------------------------------------------------------------------===//
89
90 let isCommutable = 1 in {
91
92 def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile>;
93 def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile, fmad>;
94 def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile, AMDGPUmad_i24>;
95 def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile, AMDGPUmad_u24>;
96 def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile, fma>;
97 def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile, fma>;
98 def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile, int_amdgcn_lerp>;
99
100 let SchedRW = [WriteDoubleAdd] in {
101 def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile, fadd, 1>;
102 def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile, fmul, 1>;
103 def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile, fminnum, 1>;
104 def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile, fmaxnum, 1>;
105 } // End SchedRW = [WriteDoubleAdd]
106
107 let SchedRW = [WriteQuarterRate32] in {
108 def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile>;
109 def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile, mulhu>;
110 def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile>;
111 def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile, mulhs>;
112 } // End SchedRW = [WriteQuarterRate32]
113
114 let Uses = [VCC, EXEC] in {
115 // v_div_fmas_f32:
116 // result = src0 * src1 + src2
117 // if (vcc)
118 // result *= 2^32
119 //
120 def V_DIV_FMAS_F32 : VOP3_PseudoNew <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC,
121 getVOP3VCC.ret> {
122 let SchedRW = [WriteFloatFMA];
123 }
124 // v_div_fmas_f64:
125 // result = src0 * src1 + src2
126 // if (vcc)
127 // result *= 2^64
128 //
129 def V_DIV_FMAS_F64 : VOP3_PseudoNew <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC,
130 getVOP3VCC.ret> {
131 let SchedRW = [WriteDouble];
132 }
133 } // End Uses = [VCC, EXEC]
134
135 } // End isCommutable = 1
136
137 def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile, int_amdgcn_cubeid>;
138 def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile, int_amdgcn_cubesc>;
139 def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile, int_amdgcn_cubetc>;
140 def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile, int_amdgcn_cubema>;
141 def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile, AMDGPUbfe_u32>;
142 def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile, AMDGPUbfe_i32>;
143 def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile, AMDGPUbfi>;
144 def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile>;
145 def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile>;
146 def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile, AMDGPUfmin3>;
147 def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile, AMDGPUsmin3>;
148 def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile, AMDGPUumin3>;
149 def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile, AMDGPUfmax3>;
150 def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile, AMDGPUsmax3>;
151 def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile, AMDGPUumax3>;
152 def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile, AMDGPUfmed3>;
153 def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile, AMDGPUsmed3>;
154 def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile, AMDGPUumed3>;
155 def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile, int_amdgcn_sad_u8>;
156 def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile, int_amdgcn_sad_hi_u8>;
157 def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile, int_amdgcn_sad_u16>;
158 def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile>;
159 def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile, int_amdgcn_cvt_pk_u8_f32>;
160 def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile, AMDGPUdiv_fixup>;
161
162 let SchedRW = [WriteDoubleAdd] in {
163 def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile, AMDGPUdiv_fixup>;
164 def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile, AMDGPUldexp, 1>;
165 } // End SchedRW = [WriteDoubleAdd]
166
167 def V_DIV_SCALE_F32 : VOP3_PseudoNew <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
168 let SchedRW = [WriteFloatFMA, WriteSALU];
169 }
170
171 // Double precision division pre-scale.
172 def V_DIV_SCALE_F64 : VOP3_PseudoNew <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
173 let SchedRW = [WriteDouble, WriteSALU];
174 }
175
176 def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile, int_amdgcn_msad_u8>;
177 def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile, int_amdgcn_mqsad_pk_u16_u8>;
178
179 def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile, AMDGPUtrig_preop> {
180 let SchedRW = [WriteDouble];
181 }
182
183 // These instructions only exist on SI and CI
184 let SubtargetPredicate = isSICI in {
185 def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile>;
186 def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile>;
187 def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile>;
188 def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile>;
189 } // End SubtargetPredicate = isSICI
190
191 let SubtargetPredicate = isVI in {
192 def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile>;
193 def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile>;
194 def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile>;
195 } // End SubtargetPredicate = isVI
196
197
198 let SubtargetPredicate = isCIVI in {
199
200 def V_MQSAD_U16_U8 : VOP3Inst <"v_mqsad_u16_u8", VOP3_Profile>;
201 def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile, int_amdgcn_qsad_pk_u16_u8>;
202 def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile, int_amdgcn_mqsad_u32_u8>;
203
204 let isCommutable = 1 in {
205 def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3_Profile>;
206
207 // XXX - Does this set VCC?
208 def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3_Profile>;
209 } // End isCommutable = 1
210
211 } // End SubtargetPredicate = isCIVI
212
213
214 let SubtargetPredicate = isVI in {
215
216 let isCommutable = 1 in {
217 def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile>;
218 def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile>;
219 def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile>;
220 }
221
222 } // End SubtargetPredicate = isVI
223
224
225 //===----------------------------------------------------------------------===//
226 // Target
227 //===----------------------------------------------------------------------===//
228
229 //===----------------------------------------------------------------------===//
230 // SI
231 //===----------------------------------------------------------------------===//
232
233 let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
234
235 multiclass VOP3_Real_si op> {
236 def _si : VOP3_Real(NAME), SIEncodingFamily.SI>,
237 VOP3e_siNew (NAME).Pfl>;
238 }
239
240 multiclass VOP3be_Real_si op> {
241 def _si : VOP3_Real(NAME), SIEncodingFamily.SI>,
242 VOP3be_siNew (NAME).Pfl>;
243 }
244
245 } // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
246
247 defm V_MAD_LEGACY_F32 : VOP3_Real_si <0x140>;
248 defm V_MAD_F32 : VOP3_Real_si <0x141>;
249 defm V_MAD_I32_I24 : VOP3_Real_si <0x142>;
250 defm V_MAD_U32_U24 : VOP3_Real_si <0x143>;
251 defm V_CUBEID_F32 : VOP3_Real_si <0x144>;
252 defm V_CUBESC_F32 : VOP3_Real_si <0x145>;
253 defm V_CUBETC_F32 : VOP3_Real_si <0x146>;
254 defm V_CUBEMA_F32 : VOP3_Real_si <0x147>;
255 defm V_BFE_U32 : VOP3_Real_si <0x148>;
256 defm V_BFE_I32 : VOP3_Real_si <0x149>;
257 defm V_BFI_B32 : VOP3_Real_si <0x14a>;
258 defm V_FMA_F32 : VOP3_Real_si <0x14b>;
259 defm V_FMA_F64 : VOP3_Real_si <0x14c>;
260 defm V_LERP_U8 : VOP3_Real_si <0x14d>;
261 defm V_ALIGNBIT_B32 : VOP3_Real_si <0x14e>;
262 defm V_ALIGNBYTE_B32 : VOP3_Real_si <0x14f>;
263 defm V_MULLIT_F32 : VOP3_Real_si <0x150>;
264 defm V_MIN3_F32 : VOP3_Real_si <0x151>;
265 defm V_MIN3_I32 : VOP3_Real_si <0x152>;
266 defm V_MIN3_U32 : VOP3_Real_si <0x153>;
267 defm V_MAX3_F32 : VOP3_Real_si <0x154>;
268 defm V_MAX3_I32 : VOP3_Real_si <0x155>;
269 defm V_MAX3_U32 : VOP3_Real_si <0x156>;
270 defm V_MED3_F32 : VOP3_Real_si <0x157>;
271 defm V_MED3_I32 : VOP3_Real_si <0x158>;
272 defm V_MED3_U32 : VOP3_Real_si <0x159>;
273 defm V_SAD_U8 : VOP3_Real_si <0x15a>;
274 defm V_SAD_HI_U8 : VOP3_Real_si <0x15b>;
275 defm V_SAD_U16 : VOP3_Real_si <0x15c>;
276 defm V_SAD_U32 : VOP3_Real_si <0x15d>;
277 defm V_CVT_PK_U8_F32 : VOP3_Real_si <0x15e>;
278 defm V_DIV_FIXUP_F32 : VOP3_Real_si <0x15f>;
279 defm V_DIV_FIXUP_F64 : VOP3_Real_si <0x160>;
280 defm V_LSHL_B64 : VOP3_Real_si <0x161>;
281 defm V_LSHR_B64 : VOP3_Real_si <0x162>;
282 defm V_ASHR_I64 : VOP3_Real_si <0x163>;
283 defm V_ADD_F64 : VOP3_Real_si <0x164>;
284 defm V_MUL_F64 : VOP3_Real_si <0x165>;
285 defm V_MIN_F64 : VOP3_Real_si <0x166>;
286 defm V_MAX_F64 : VOP3_Real_si <0x167>;
287 defm V_LDEXP_F64 : VOP3_Real_si <0x168>;
288 defm V_MUL_LO_U32 : VOP3_Real_si <0x169>;
289 defm V_MUL_HI_U32 : VOP3_Real_si <0x16a>;
290 defm V_MUL_LO_I32 : VOP3_Real_si <0x16b>;
291 defm V_MUL_HI_I32 : VOP3_Real_si <0x16c>;
292 defm V_DIV_SCALE_F32 : VOP3be_Real_si <0x16d>;
293 defm V_DIV_SCALE_F64 : VOP3be_Real_si <0x16e>;
294 defm V_DIV_FMAS_F32 : VOP3_Real_si <0x16f>;
295 defm V_DIV_FMAS_F64 : VOP3_Real_si <0x170>;
296 defm V_MSAD_U8 : VOP3_Real_si <0x171>;
297 defm V_MQSAD_PK_U16_U8 : VOP3_Real_si <0x173>;
298 defm V_TRIG_PREOP_F64 : VOP3_Real_si <0x174>;
299
300 //===----------------------------------------------------------------------===//
301 // CI
302 //===----------------------------------------------------------------------===//
303
304 multiclass VOP3_Real_ci op> {
305 def _ci : VOP3_Real(NAME), SIEncodingFamily.SI>,
306 VOP3e_siNew (NAME).Pfl> {
307 let AssemblerPredicates = [isCIOnly];
308 let DecoderNamespace = "CI";
309 }
310 }
311
312 defm V_MQSAD_U16_U8 : VOP3_Real_ci <0x172>;
313 defm V_QSAD_PK_U16_U8 : VOP3_Real_ci <0x172>;
314 defm V_MQSAD_U32_U8 : VOP3_Real_ci <0x174>;
315 defm V_MAD_U64_U32 : VOP3_Real_ci <0x176>;
316 defm V_MAD_I64_I32 : VOP3_Real_ci <0x177>;
317
318 //===----------------------------------------------------------------------===//
319 // VI
320 //===----------------------------------------------------------------------===//
321
322 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
323
324 multiclass VOP3_Real_vi op> {
325 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
326 VOP3e_viNew (NAME).Pfl>;
327 }
328
329 multiclass VOP3be_Real_vi op> {
330 def _vi : VOP3_Real(NAME), SIEncodingFamily.VI>,
331 VOP3be_viNew (NAME).Pfl>;
332 }
333
334 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
335
336 defm V_MQSAD_U16_U8 : VOP3_Real_vi <0x172>;
337 defm V_MAD_U64_U32 : VOP3_Real_vi <0x176>;
338 defm V_MAD_I64_I32 : VOP3_Real_vi <0x177>;
339
340 defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>;
341 defm V_MAD_F32 : VOP3_Real_vi <0x1c1>;
342 defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>;
343 defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>;
344 defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>;
345 defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>;
346 defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>;
347 defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>;
348 defm V_BFE_U32 : VOP3_Real_vi <0x1c8>;
349 defm V_BFE_I32 : VOP3_Real_vi <0x1c9>;
350 defm V_BFI_B32 : VOP3_Real_vi <0x1ca>;
351 defm V_FMA_F32 : VOP3_Real_vi <0x1cb>;
352 defm V_FMA_F64 : VOP3_Real_vi <0x1cc>;
353 defm V_LERP_U8 : VOP3_Real_vi <0x1cd>;
354 defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>;
355 defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>;
356 defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>;
357 defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>;
358 defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>;
359 defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>;
360 defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>;
361 defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>;
362 defm V_MED3_F32 : VOP3_Real_vi <0x1d6>;
363 defm V_MED3_I32 : VOP3_Real_vi <0x1d7>;
364 defm V_MED3_U32 : VOP3_Real_vi <0x1d8>;
365 defm V_SAD_U8 : VOP3_Real_vi <0x1d9>;
366 defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>;
367 defm V_SAD_U16 : VOP3_Real_vi <0x1db>;
368 defm V_SAD_U32 : VOP3_Real_vi <0x1dc>;
369 defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>;
370 defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>;
371 defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>;
372 defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>;
373 defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>;
374 defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>;
375 defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>;
376 defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>;
377 defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>;
378 defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>;
379 defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>;
380
381 defm V_MAD_F16 : VOP3_Real_vi <0x1ea>;
382 defm V_MAD_U16 : VOP3_Real_vi <0x1eb>;
383 defm V_MAD_I16 : VOP3_Real_vi <0x1ec>;
384
385 defm V_ADD_F64 : VOP3_Real_vi <0x280>;
386 defm V_MUL_F64 : VOP3_Real_vi <0x281>;
387 defm V_MIN_F64 : VOP3_Real_vi <0x282>;
388 defm V_MAX_F64 : VOP3_Real_vi <0x283>;
389 defm V_LDEXP_F64 : VOP3_Real_vi <0x284>;
390 defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>;
391
392 // removed from VI as identical to V_MUL_LO_U32
393 let isAsmParserOnly = 1 in {
394 defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>;
395 }
396
397 defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>;
398 defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>;
399
400 defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>;
401 defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>;
402 defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>;
403 defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>;
9999 let Inst{15} = !if(P.HasClamp, clamp, 0);
100100 }
101101
102 class VOP3e_siNew op, VOPProfile P> : VOP3a_siNew {
103 bits<8> vdst;
104 let Inst{7-0} = vdst;
105 }
106
107 class VOP3e_viNew op, VOPProfile P> : VOP3a_viNew {
108 bits<8> vdst;
109 let Inst{7-0} = vdst;
110 }
111
112 class VOP3beNew : Enc64 {
113 bits<8> vdst;
114 bits<2> src0_modifiers;
115 bits<9> src0;
116 bits<2> src1_modifiers;
117 bits<9> src1;
118 bits<2> src2_modifiers;
119 bits<9> src2;
120 bits<7> sdst;
121 bits<2> omod;
122
123 let Inst{7-0} = vdst;
124 let Inst{14-8} = sdst;
125 let Inst{31-26} = 0x34; //encoding
126 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
127 let Inst{49-41} = !if(P.HasSrc1, src1, 0);
128 let Inst{58-50} = !if(P.HasSrc2, src2, 0);
129 let Inst{60-59} = !if(P.HasOMod, omod, 0);
130 let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
131 let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
132 let Inst{63} = !if(P.HasSrc2Mods, src2_modifiers{0}, 0);
133 }
134
135 class VOP3be_siNew op, VOPProfile P> : VOP3beNew

{

136 let Inst{25-17} = op;
137 }
138
139 class VOP3be_viNew op, VOPProfile P> : VOP3beNew

{

140 bits<1> clamp;
141 let Inst{25-16} = op;
142 let Inst{15} = !if(P.HasClamp, clamp, 0);
143 }
144
102145 class VOP_SDWAeNew : Enc64 {
103146 bits<8> src0;
104147 bits<3> src0_sel;
127170 }
128171
129172 include "VOPCInstructions.td"
173 include "VOP3Instructions.td"