llvm.org GIT mirror llvm / 90f24bb
Merging r369084: ------------------------------------------------------------------------ r369084 | ctopper | 2019-08-16 06:47:44 +0200 (Fri, 16 Aug 2019) | 5 lines [X86] Manually reimplement getTargetInsertSubreg in X86DAGToDAGISel::matchBitExtract so we can call insertDAGNode on the target constant. This is needed to maintain the topological sort order. Fixes PR42992. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_90@369357 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 1 year, 3 months ago
2 changed file(s) with 23 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
33323332 SDValue ImplDef = SDValue(
33333333 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i32), 0);
33343334 insertDAGNode(*CurDAG, SDValue(Node, 0), ImplDef);
3335 NBits = CurDAG->getTargetInsertSubreg(X86::sub_8bit, DL, MVT::i32, ImplDef,
3336 NBits);
3335
3336 SDValue SRIdxVal = CurDAG->getTargetConstant(X86::sub_8bit, DL, MVT::i32);
3337 insertDAGNode(*CurDAG, SDValue(Node, 0), SRIdxVal);
3338 NBits = SDValue(
3339 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::i32, ImplDef,
3340 NBits, SRIdxVal), 0);
33373341 insertDAGNode(*CurDAG, SDValue(Node, 0), NBits);
33383342
33393343 if (Subtarget->hasBMI2()) {
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=bmi2 | FileCheck %s
2
3 define i32 @hoge(i32 %a) {
4 ; CHECK-LABEL: hoge:
5 ; CHECK: # %bb.0: # %bb
6 ; CHECK-NEXT: movl $15, %eax
7 ; CHECK-NEXT: bzhil %edi, %eax, %eax
8 ; CHECK-NEXT: shll $8, %eax
9 ; CHECK-NEXT: retq
10 bb:
11 %tmp3 = shl nsw i32 -1, %a
12 %tmp4 = xor i32 %tmp3, -1
13 %tmp5 = shl i32 %tmp4, 8
14 %tmp6 = and i32 %tmp5, 3840
15 ret i32 %tmp6
16 }