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Merging r293417: ------------------------------------------------------------------------ r293417 | jhibbits | 2017-01-28 20:55:57 -0800 (Sat, 28 Jan 2017) | 16 lines Add some Book-E instructions to the asm parser and printer. Summary: Adds the following instructions: * mfpmr * mtpmr * icblc * icblq * icbtls Fix the scheduling for mtspr on e5500, which uses CFX0, instead of SFX0/SFX1 as on e500mc. Addresses PR 31538. Differential Revision: https://reviews.llvm.org/D29002 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@293651 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 2 years ago
6 changed file(s) with 52 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
15071507 PPC970_DGroup_Single;
15081508 } // hasSideEffects = 0
15091509
1510 def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src),
1511 "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>;
1512 def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src),
1513 "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
15101514 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
15111515 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1516 def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src),
1517 "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
15121518
15131519 def : Pat<(int_ppc_dcbt xoaddr:$dst),
15141520 (DCBT 0, xoaddr:$dst)>;
23802386 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
23812387 "mftb $RT, $SPR", IIC_SprMFTB>;
23822388
2389 def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR),
2390 "mfpmr $RT, $SPR", IIC_SprMFPMR>;
2391
2392 def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT),
2393 "mtpmr $SPR, $RT", IIC_SprMTPMR>;
2394
2395
23832396 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
23842397 // on a 32-bit target.
23852398 let hasSideEffects = 1, usesCustomInserter = 1 in
117117 def IIC_SprABORT : InstrItinClass;
118118 def IIC_SprMSGSYNC : InstrItinClass;
119119 def IIC_SprSTOP : InstrItinClass;
120 def IIC_SprMFPMR : InstrItinClass;
121 def IIC_SprMTPMR : InstrItinClass;
120122
121123 //===----------------------------------------------------------------------===//
122124 // Processor instruction itineraries.
248248 InstrStage<5, [E500_SFX0]>],
249249 [8, 1],
250250 [E500_GPR_Bypass, E500_CR_Bypass]>,
251 InstrItinData,
252 InstrStage<4, [E500_SFX0]>],
253 [7, 1], // Latency = 4, Repeat rate = 4
254 [E500_GPR_Bypass, E500_GPR_Bypass]>,
251255 InstrItinData,
252256 InstrStage<4, [E500_SFX0]>],
253257 [7, 1], // Latency = 4, Repeat rate = 4
256260 InstrStage<1, [E500_SFX0, E500_SFX1]>],
257261 [4, 1], // Latency = 1, Repeat rate = 1
258262 [E500_GPR_Bypass, E500_CR_Bypass]>,
263 InstrItinData,
264 InstrStage<1, [E500_SFX0]>],
265 [4, 1], // Latency = 1, Repeat rate = 1
266 [E500_CR_Bypass, E500_GPR_Bypass]>,
259267 InstrItinData,
260268 InstrStage<4, [E500_SFX0]>],
261269 [7, 1], // Latency = 4, Repeat rate = 4
312312 InstrStage<5, [E5500_CFX_0]>],
313313 [9, 2], // Latency = 5, Repeat rate = 5
314314 [E5500_GPR_Bypass, E5500_CR_Bypass]>,
315 InstrItinData,
316 InstrStage<4, [E5500_SFX0]>],
315 InstrItinData,
316 InstrStage<4, [E5500_CFX_0]>],
317317 [8, 2], // Latency = 4, Repeat rate = 4
318318 [E5500_GPR_Bypass, E5500_GPR_Bypass]>,
319319 InstrItinData,
320 InstrStage<1, [E5500_CFX_0]>],
321 [5], // Latency = 1, Repeat rate = 1
322 [E5500_GPR_Bypass]>,
323 InstrItinData,
320324 InstrStage<1, [E5500_CFX_0]>],
321325 [5], // Latency = 1, Repeat rate = 1
322326 [E5500_GPR_Bypass]>,
325329 [8, 2], // Latency = 4, Repeat rate = 4
326330 [NoBypass, E5500_GPR_Bypass]>,
327331 InstrItinData,
328 InstrStage<1, [E5500_SFX0, E5500_SFX1]>],
332 InstrStage<1, [E5500_CFX_0]>],
329333 [5], // Latency = 1, Repeat rate = 1
330334 [E5500_GPR_Bypass]>,
331335 InstrItinData,
133133 0x7c 0x0b 0x66 0x24
134134 # CHECK: tlbsx 11, 12
135135 0x7c 0x0b 0x67 0x24
136
137 # CHECK: mfpmr 5, 400
138 0x7c 0xb0 0x62 0x9c
139 # CHECK: mtpmr 400, 6
140 0x7c 0xd0 0x63 0x9c
141 # CHECK: icblc 0, 0, 8
142 0x7c 0x00 0x41 0xcc
143 # CHECK: icbtls 0, 0, 9
144 0x7c 0x00 0x4b 0xcc
196196 # CHECK-BE: tlbsx 11, 12 # encoding: [0x7c,0x0b,0x67,0x24]
197197 # CHECK-LE: tlbsx 11, 12 # encoding: [0x24,0x67,0x0b,0x7c]
198198 tlbsx %r11, %r12
199
200 # CHECK-BE: mfpmr 5, 400 # encoding: [0x7c,0xb0,0x62,0x9c]
201 # CHECK-LE: mfpmr 5, 400 # encoding: [0x9c,0x62,0xb0,0x7c]
202 mfpmr 5, 400
203 # CHECK-BE: mtpmr 400, 6 # encoding: [0x7c,0xd0,0x63,0x9c]
204 # CHECK-LE: mtpmr 400, 6 # encoding: [0x9c,0x63,0xd0,0x7c]
205 mtpmr 400, 6
206 # CHECK-BE: icblc 0, 0, 8 # encoding: [0x7c,0x00,0x41,0xcc]
207 # CHECK-LE: icblc 0, 0, 8 # encoding: [0xcc,0x41,0x00,0x7c]
208 icblc 0, 0, 8
209 # CHECK-BE: icbtls 0, 0, 9 # encoding: [0x7c,0x00,0x4b,0xcc]
210 # CHECK-LE: icbtls 0, 0, 9 # encoding: [0xcc,0x4b,0x00,0x7c]
211 icbtls 0, 0, 9