llvm.org GIT mirror llvm / 905e335
[x86] Make the 'x86-64' cpu, what I see as and many use as the generic default architecture for reasonable modern x86 processors, actually be modern. This processor model should essentially be "tuned" for modern x86 chips as much as possible without undue penalties on any specific architecture. Previously we weren't even using the nice scheduling models. There are a few other tweaks needed here, but this change at least I have benchmarked across a decent swatch of chips (intel's clovertown, westmere, and sandybridge; amd's istanbul) and seen no significant regressions. If anyone has suggested ways to test this, just let me know. Somewhat alarmingly, no existing tests failed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208230 91177308-0d34-0410-b5e6-96231b3b80d8 Chandler Carruth 6 years ago
1 changed file(s) with 15 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
194194 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
195195 def : Proc<"pentium4", [FeatureSSE2]>;
196196 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
197 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
198 FeatureFastUAMem]>;
199198 // Intel Core Duo.
200199 def : ProcessorModel<"yonah", SandyBridgeModel,
201200 [FeatureSSE3, FeatureSlowBTMem]>;
342341 def : Proc<"c3", [Feature3DNow]>;
343342 def : Proc<"c3-2", [FeatureSSE1]>;
344 // We also provide a generic 64-bit specific x86 processor model which tries to
345 // be good for modern chips without enabling instruction set encodings past the
346 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
347 // modern 64-bit x86 chip, and enables features that are generally beneficial.
348 //
349 // We currently use the Sandy Bridge model as the default scheduling model as
350 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
351 // covers a huge swath of x86 processors. If there are specific scheduling
352 // knobs which need to be tuned differently for AMD chips, we might consider
353 // forming a common base for them.
354 def : ProcessorModel<"x86-64", SandyBridgeModel,
355 [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
356 FeatureFastUAMem]>;
345358 //===----------------------------------------------------------------------===//
346359 // Register File Description
347360 //===----------------------------------------------------------------------===//