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[X86] Automatically generate various tests. NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369909 91177308-0d34-0410-b5e6-96231b3b80d8 Amaury Sechet 5 months ago
25 changed file(s) with 1033 addition(s) and 235 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s | FileCheck %s
1 ; RUN: llc -relocation-model=pic < %s | FileCheck %s
2 ; RUN: llc -relocation-model=pic < %s | FileCheck %s --check-prefix=PIC
23
34 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
45 target triple = "x86_64-unknown-linux-gnu"
67 @foo = external global i8, align 1, !absolute_symbol !0
78
89 define void @bar(i8* %x) {
10 ; CHECK-LABEL: bar:
11 ; CHECK: # %bb.0: # %entry
12 ; CHECK-NEXT: testb $foo, (%rdi)
13 ; CHECK-NEXT: je .LBB0_1
14 ; CHECK-NEXT: # %bb.2: # %if.then
15 ; CHECK-NEXT: xorl %eax, %eax
16 ; CHECK-NEXT: jmp xf # TAILCALL
17 ; CHECK-NEXT: .LBB0_1: # %if.end
18 ; CHECK-NEXT: retq
19 ;
20 ; PIC-LABEL: bar:
21 ; PIC: # %bb.0: # %entry
22 ; PIC-NEXT: testb $foo, (%rdi)
23 ; PIC-NEXT: je .LBB0_1
24 ; PIC-NEXT: # %bb.2: # %if.then
25 ; PIC-NEXT: xorl %eax, %eax
26 ; PIC-NEXT: jmp xf@PLT # TAILCALL
27 ; PIC-NEXT: .LBB0_1: # %if.end
28 ; PIC-NEXT: retq
929 entry:
1030 %0 = load i8, i8* %x, align 1
1131 %conv = sext i8 %0 to i32
12 ; CHECK: testb $foo, (%rdi)
1332 %and = and i32 %conv, sext (i8 ptrtoint (i8* @foo to i8) to i32)
1433 %tobool = icmp eq i32 %and, 0
1534 br i1 %tobool, label %if.end, label %if.then
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
12
23 define i64 @bitcasti64tof64() {
34 ; CHECK-LABEL: bitcasti64tof64:
45 ; CHECK: # %bb.0:
5 ; CHECK: vmovsd {{.*#+}} xmm0 = mem[0],zero
6 ; CHECK-NEXT: # implicit-def: $rax
7 ; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
68 ; CHECK-NEXT: vmovq %xmm0, %rax
79 ; CHECK-NEXT: retq
810 %a = load double, double* undef
351351 }
352352
353353 define <4 x float> @shuffle_v4f32_1133(<4 x float> %a, <4 x float> %b) {
354 ; vmovshdup 128 test
354 ; vmovshdup 128 test
355355 %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32>
356356 ret <4 x float> %shuffle
357357 }
None ; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck %s
12
2 ; UNSAFE-LABEL: maxpd:
3 ; UNSAFE: vmaxpd {{.+}}, %xmm
43 define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
4 ; CHECK-LABEL: maxpd:
5 ; CHECK: # %bb.0:
6 ; CHECK-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
7 ; CHECK-NEXT: retq
58 %max_is_x = fcmp oge <2 x double> %x, %y
69 %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
710 ret <2 x double> %max
811 }
912
10 ; UNSAFE-LABEL: minpd:
11 ; UNSAFE: vminpd {{.+}}, %xmm
1213 define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
14 ; CHECK-LABEL: minpd:
15 ; CHECK: # %bb.0:
16 ; CHECK-NEXT: vminpd %xmm1, %xmm0, %xmm0
17 ; CHECK-NEXT: retq
1318 %min_is_x = fcmp ole <2 x double> %x, %y
1419 %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
1520 ret <2 x double> %min
1621 }
1722
18 ; UNSAFE-LABEL: maxps:
19 ; UNSAFE: vmaxps {{.+}}, %xmm
2023 define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
24 ; CHECK-LABEL: maxps:
25 ; CHECK: # %bb.0:
26 ; CHECK-NEXT: vmaxps %xmm1, %xmm0, %xmm0
27 ; CHECK-NEXT: retq
2128 %max_is_x = fcmp oge <4 x float> %x, %y
2229 %max = select <4 x i1> %max_is_x, <4 x float> %x, <4 x float> %y
2330 ret <4 x float> %max
2431 }
2532
26 ; UNSAFE-LABEL: minps:
27 ; UNSAFE: vminps {{.+}}, %xmm
2833 define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
34 ; CHECK-LABEL: minps:
35 ; CHECK: # %bb.0:
36 ; CHECK-NEXT: vminps %xmm1, %xmm0, %xmm0
37 ; CHECK-NEXT: retq
2938 %min_is_x = fcmp ole <4 x float> %x, %y
3039 %min = select <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y
3140 ret <4 x float> %min
3241 }
3342
34 ; UNSAFE-LABEL: vmaxpd:
35 ; UNSAFE: vmaxpd {{.+}}, %ymm
3643 define <4 x double> @vmaxpd(<4 x double> %x, <4 x double> %y) {
44 ; CHECK-LABEL: vmaxpd:
45 ; CHECK: # %bb.0:
46 ; CHECK-NEXT: vmaxpd %ymm1, %ymm0, %ymm0
47 ; CHECK-NEXT: retq
3748 %max_is_x = fcmp oge <4 x double> %x, %y
3849 %max = select <4 x i1> %max_is_x, <4 x double> %x, <4 x double> %y
3950 ret <4 x double> %max
4051 }
4152
42 ; UNSAFE-LABEL: vminpd:
43 ; UNSAFE: vminpd {{.+}}, %ymm
4453 define <4 x double> @vminpd(<4 x double> %x, <4 x double> %y) {
54 ; CHECK-LABEL: vminpd:
55 ; CHECK: # %bb.0:
56 ; CHECK-NEXT: vminpd %ymm1, %ymm0, %ymm0
57 ; CHECK-NEXT: retq
4558 %min_is_x = fcmp ole <4 x double> %x, %y
4659 %min = select <4 x i1> %min_is_x, <4 x double> %x, <4 x double> %y
4760 ret <4 x double> %min
4861 }
4962
50 ; UNSAFE-LABEL: vmaxps:
51 ; UNSAFE: vmaxps {{.+}}, %ymm
5263 define <8 x float> @vmaxps(<8 x float> %x, <8 x float> %y) {
64 ; CHECK-LABEL: vmaxps:
65 ; CHECK: # %bb.0:
66 ; CHECK-NEXT: vmaxps %ymm1, %ymm0, %ymm0
67 ; CHECK-NEXT: retq
5368 %max_is_x = fcmp oge <8 x float> %x, %y
5469 %max = select <8 x i1> %max_is_x, <8 x float> %x, <8 x float> %y
5570 ret <8 x float> %max
5671 }
5772
58 ; UNSAFE-LABEL: vminps:
59 ; UNSAFE: vminps {{.+}}, %ymm
6073 define <8 x float> @vminps(<8 x float> %x, <8 x float> %y) {
74 ; CHECK-LABEL: vminps:
75 ; CHECK: # %bb.0:
76 ; CHECK-NEXT: vminps %ymm1, %ymm0, %ymm0
77 ; CHECK-NEXT: retq
6178 %min_is_x = fcmp ole <8 x float> %x, %y
6279 %min = select <8 x i1> %min_is_x, <8 x float> %x, <8 x float> %y
6380 ret <8 x float> %min
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx,vpclmulqdq -show-mc-encoding | FileCheck %s --check-prefix=AVX_VPCLMULQDQ
12
23 ; Check for vpclmulqdq
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
12 ;
23
34 define i32 @x(i32 %t) nounwind readnone ssp {
5 ; CHECK-LABEL: x:
6 ; CHECK: # %bb.0: # %entry
7 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
8 ; CHECK-NEXT: shll $23, %eax
9 ; CHECK-NEXT: sarl $31, %eax
10 ; CHECK-NEXT: andl $-26, %eax
11 ; CHECK-NEXT: retl
412 entry:
5 ; CHECK: shll $23, %eax
6 ; CHECK: sarl $31, %eax
7 ; CHECK: andl $-26, %eax
813 %and = and i32 %t, 256
914 %tobool = icmp eq i32 %and, 0
1015 %retval.0 = select i1 %tobool, i32 0, i32 -26
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
12 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
23
4344 ;
4445 ; AVX-LABEL: combine_fabs_fabs:
4546 ; AVX: # %bb.0:
46 ; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
47 ; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
4748 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
4849 ; AVX-NEXT: retq
4950 %1 = call float @llvm.fabs.f32(float %a)
5960 ;
6061 ; AVX-LABEL: combine_vec_fabs_fabs:
6162 ; AVX: # %bb.0:
62 ; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
63 ; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
6364 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
6465 ; AVX-NEXT: retq
6566 %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
7677 ;
7778 ; AVX-LABEL: combine_fabs_fneg:
7879 ; AVX: # %bb.0:
79 ; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
80 ; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
8081 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
8182 ; AVX-NEXT: retq
8283 %1 = fsub float -0.0, %a
9293 ;
9394 ; AVX-LABEL: combine_vec_fabs_fneg:
9495 ; AVX: # %bb.0:
95 ; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
96 ; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
9697 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
9798 ; AVX-NEXT: retq
9899 %1 = fsub <4 x float> , %a
109110 ;
110111 ; AVX-LABEL: combine_fabs_fcopysign:
111112 ; AVX: # %bb.0:
112 ; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
113 ; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
113114 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
114115 ; AVX-NEXT: retq
115116 %1 = call float @llvm.copysign.f32(float %a, float %b)
125126 ;
126127 ; AVX-LABEL: combine_vec_fabs_fcopysign:
127128 ; AVX: # %bb.0:
128 ; AVX-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
129 ; AVX-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
129130 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
130131 ; AVX-NEXT: retq
131132 %1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b)
None ; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | grep fldl | count 1
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s
12
23 define double @doload64(i64 %x) nounwind {
4 ; CHECK-LABEL: doload64:
5 ; CHECK: # %bb.0:
6 ; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
7 ; CHECK-NEXT: retl
38 %tmp717 = bitcast i64 %x to double
49 ret double %tmp717
510 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=i686-- < %s | FileCheck %s
12
2 ; CHECK-LABEL: @bar
3 ; CHECK-DAG: movl $1074339512,
4 ; CHECK-DAG: movl $1374389535,
5 ; CHECK-DAG: movl $1078523331,
63 define void @bar() unnamed_addr {
4 ; CHECK-LABEL: bar:
5 ; CHECK: # %bb.0: # %entry-block
6 ; CHECK-NEXT: pushl %ebp
7 ; CHECK-NEXT: .cfi_def_cfa_offset 8
8 ; CHECK-NEXT: .cfi_offset %ebp, -8
9 ; CHECK-NEXT: movl %esp, %ebp
10 ; CHECK-NEXT: .cfi_def_cfa_register %ebp
11 ; CHECK-NEXT: andl $-8, %esp
12 ; CHECK-NEXT: subl $16, %esp
13 ; CHECK-NEXT: movl $1074339512, {{[0-9]+}}(%esp) # imm = 0x40091EB8
14 ; CHECK-NEXT: movl $1374389535, (%esp) # imm = 0x51EB851F
15 ; CHECK-NEXT: movl $1078523331, {{[0-9]+}}(%esp) # imm = 0x4048F5C3
16 ; CHECK-NEXT: movl %ebp, %esp
17 ; CHECK-NEXT: popl %ebp
18 ; CHECK-NEXT: .cfi_def_cfa %esp, 4
19 ; CHECK-NEXT: retl
720 entry-block:
821 %a = alloca double
922 %b = alloca float
None ; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -o %t
1 ; RUN: not grep unpcklps %t
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 | FileCheck %s --implicit-check-not unpcklps
22
33 define i32 @foo() nounwind {
4 ; CHECK-LABEL: foo:
5 ; CHECK: # %bb.0: # %entry
6 ; CHECK-NEXT: xorps %xmm0, %xmm0
7 ; CHECK-NEXT: movaps %xmm0, 0
48 entry:
59 %tmp74.i25762 = shufflevector <16 x float> zeroinitializer, <16 x float> zeroinitializer, <16 x i32> ; <<16 x float>> [#uses=1]
610 %tmp518 = shufflevector <16 x float> %tmp74.i25762, <16 x float> undef, <4 x i32> ; <<4 x float>> [#uses=1]
None ; RUN: llc < %s -mtriple=i686-- >/dev/null
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
12 ; PR4699
23
34 ; Handle this extractvalue-of-extractvalue case without getting in
910 %pp = type { %cc }
1011
1112 define fastcc void @foo(%pp* nocapture byval %p_arg) {
13 ; CHECK-LABEL: foo:
14 ; CHECK: # %bb.0: # %entry
15 ; CHECK-NEXT: retl
1216 entry:
1317 %tmp2 = getelementptr %pp, %pp* %p_arg, i64 0, i32 0 ; <%cc*> [#uses=
1418 %tmp3 = load %cc, %cc* %tmp2 ; <%cc> [#uses=1]
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
12
23 ; Use an h register, but don't omit the explicit shift for
45
56 define i32 @foo(i8* %x, i32 %y) nounwind {
67 ; CHECK-LABEL: foo:
7 ; CHECK-NOT: ret
8 ; CHECK: movzbl %{{[abcd]h}},
9 ; CHECK-NOT: ret
10 ; CHECK: shll $3,
11 ; CHECK: ret
8 ; CHECK: # %bb.0:
9 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
10 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
11 ; CHECK-NEXT: movzbl %ah, %eax
12 ; CHECK-NEXT: movb $77, (%ecx,%eax,8)
13 ; CHECK-NEXT: shll $3, %eax
14 ; CHECK-NEXT: retl
1215
1316 %t0 = lshr i32 %y, 8 ; [#uses=1]
1417 %t1 = and i32 %t0, 255 ; [#uses=2]
None ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
1 ; CHECK-NOT: IMPLICIT_DEF
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --implicit-check-not IMPLICIT_DEF
22
33 define void @foo(<2 x float>* %p) {
4 ; CHECK-LABEL: foo:
5 ; CHECK: # %bb.0:
6 ; CHECK-NEXT: xorps %xmm0, %xmm0
7 ; CHECK-NEXT: movlps %xmm0, (%rdi)
8 ; CHECK-NEXT: retq
49 %t = insertelement <2 x float> undef, float 0.0, i32 0
510 %v = insertelement <2 x float> %t, float 0.0, i32 1
611 br label %bb8
None ; RUN: llc < %s -mtriple=i686--
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
12
23 ; Test to check that we properly legalize an insert vector element
34 define void @test(<2 x i64> %val, <2 x i64>* %dst, i64 %x) nounwind {
5 ; CHECK-LABEL: test:
6 ; CHECK: # %bb.0: # %entry
7 ; CHECK-NEXT: pushl %edi
8 ; CHECK-NEXT: pushl %esi
9 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
10 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
11 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
12 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
13 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
14 ; CHECK-NEXT: addl {{[0-9]+}}(%esp), %esi
15 ; CHECK-NEXT: adcl {{[0-9]+}}(%esp), %edi
16 ; CHECK-NEXT: addl %ecx, %ecx
17 ; CHECK-NEXT: adcl %edx, %edx
18 ; CHECK-NEXT: movl %ecx, 8(%eax)
19 ; CHECK-NEXT: movl %esi, (%eax)
20 ; CHECK-NEXT: movl %edx, 12(%eax)
21 ; CHECK-NEXT: movl %edi, 4(%eax)
22 ; CHECK-NEXT: popl %esi
23 ; CHECK-NEXT: popl %edi
24 ; CHECK-NEXT: retl
425 entry:
526 %tmp4 = insertelement <2 x i64> %val, i64 %x, i32 0 ; <<2 x i64>> [#uses=1]
627 %add = add <2 x i64> %tmp4, %val ; <<2 x i64>> [#uses=1]
None ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-- | FileCheck %s
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-- | FileCheck %s --implicit-check-not '{{and|movz|sar|shl}}'
12
23 ; Optimize away zext-inreg and sext-inreg on the loop induction
34 ; variable using trip-count information.
45
5 ; CHECK-LABEL: count_up
6 ; CHECK-NOT: {{and|movz|sar|shl}}
7 ; CHECK: addq $8
8 ; CHECK-NOT: {{and|movz|sar|shl}}
9 ; CHECK: jne
106 define void @count_up(double* %d, i64 %n) nounwind {
7 ; CHECK-LABEL: count_up:
8 ; CHECK: # %bb.0: # %entry
9 ; CHECK-NEXT: movq $-80, %rax
10 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
11 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
12 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
13 ; CHECK-NEXT: .p2align 4, 0x90
14 ; CHECK-NEXT: .LBB0_1: # %loop
15 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
16 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
17 ; CHECK-NEXT: mulsd %xmm0, %xmm3
18 ; CHECK-NEXT: mulsd %xmm1, %xmm3
19 ; CHECK-NEXT: mulsd %xmm2, %xmm3
20 ; CHECK-NEXT: movsd %xmm3, 80(%rdi,%rax)
21 ; CHECK-NEXT: addq $8, %rax
22 ; CHECK-NEXT: jne .LBB0_1
23 ; CHECK-NEXT: # %bb.2: # %return
24 ; CHECK-NEXT: retq
1125 entry:
1226 br label %loop
1327
3549 ret void
3650 }
3751
38 ; CHECK-LABEL: count_down
39 ; CHECK-NOT: {{and|movz|sar|shl}}
40 ; CHECK: addq $-8
41 ; CHECK-NOT: {{and|movz|sar|shl}}
42 ; CHECK: jne
4352 define void @count_down(double* %d, i64 %n) nounwind {
53 ; CHECK-LABEL: count_down:
54 ; CHECK: # %bb.0: # %entry
55 ; CHECK-NEXT: movl $80, %eax
56 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
57 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
58 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
59 ; CHECK-NEXT: .p2align 4, 0x90
60 ; CHECK-NEXT: .LBB1_1: # %loop
61 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
62 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
63 ; CHECK-NEXT: mulsd %xmm0, %xmm3
64 ; CHECK-NEXT: mulsd %xmm1, %xmm3
65 ; CHECK-NEXT: mulsd %xmm2, %xmm3
66 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax)
67 ; CHECK-NEXT: addq $-8, %rax
68 ; CHECK-NEXT: jne .LBB1_1
69 ; CHECK-NEXT: # %bb.2: # %return
70 ; CHECK-NEXT: retq
4471 entry:
4572 br label %loop
4673
6895 ret void
6996 }
7097
71 ; CHECK-LABEL: count_up_signed
72 ; CHECK-NOT: {{and|movz|sar|shl}}
73 ; CHECK: addq $8
74 ; CHECK-NOT: {{and|movz|sar|shl}}
75 ; CHECK: jne
7698 define void @count_up_signed(double* %d, i64 %n) nounwind {
99 ; CHECK-LABEL: count_up_signed:
100 ; CHECK: # %bb.0: # %entry
101 ; CHECK-NEXT: movq $-80, %rax
102 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
103 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
104 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
105 ; CHECK-NEXT: .p2align 4, 0x90
106 ; CHECK-NEXT: .LBB2_1: # %loop
107 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
108 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
109 ; CHECK-NEXT: mulsd %xmm0, %xmm3
110 ; CHECK-NEXT: mulsd %xmm1, %xmm3
111 ; CHECK-NEXT: mulsd %xmm2, %xmm3
112 ; CHECK-NEXT: movsd %xmm3, 80(%rdi,%rax)
113 ; CHECK-NEXT: addq $8, %rax
114 ; CHECK-NEXT: jne .LBB2_1
115 ; CHECK-NEXT: # %bb.2: # %return
116 ; CHECK-NEXT: retq
77117 entry:
78118 br label %loop
79119
103143 ret void
104144 }
105145
106 ; CHECK-LABEL: count_down_signed
107 ; CHECK-NOT: {{and|movz|sar|shl}}
108 ; CHECK: addq $-8
109 ; CHECK-NOT: {{and|movz|sar|shl}}
110 ; CHECK: jne
111146 define void @count_down_signed(double* %d, i64 %n) nounwind {
147 ; CHECK-LABEL: count_down_signed:
148 ; CHECK: # %bb.0: # %entry
149 ; CHECK-NEXT: movl $80, %eax
150 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
151 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
152 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
153 ; CHECK-NEXT: .p2align 4, 0x90
154 ; CHECK-NEXT: .LBB3_1: # %loop
155 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
156 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
157 ; CHECK-NEXT: mulsd %xmm0, %xmm3
158 ; CHECK-NEXT: mulsd %xmm1, %xmm3
159 ; CHECK-NEXT: mulsd %xmm2, %xmm3
160 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax)
161 ; CHECK-NEXT: addq $-8, %rax
162 ; CHECK-NEXT: jne .LBB3_1
163 ; CHECK-NEXT: # %bb.2: # %return
164 ; CHECK-NEXT: retq
112165 entry:
113166 br label %loop
114167
138191 ret void
139192 }
140193
141 ; CHECK-LABEL: another_count_up
142 ; CHECK-NOT: {{and|movz|sar|shl}}
143 ; CHECK: addq $8
144 ; CHECK-NOT: {{and|movz|sar|shl}}
145 ; CHECK: jne
146194 define void @another_count_up(double* %d, i64 %n) nounwind {
195 ; CHECK-LABEL: another_count_up:
196 ; CHECK: # %bb.0: # %entry
197 ; CHECK-NEXT: movq $-8, %rax
198 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
199 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
200 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
201 ; CHECK-NEXT: .p2align 4, 0x90
202 ; CHECK-NEXT: .LBB4_1: # %loop
203 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
204 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
205 ; CHECK-NEXT: mulsd %xmm0, %xmm3
206 ; CHECK-NEXT: movsd %xmm3, 2048(%rdi,%rax)
207 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
208 ; CHECK-NEXT: mulsd %xmm1, %xmm3
209 ; CHECK-NEXT: movsd %xmm3, 134217728(%rdi,%rax)
210 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
211 ; CHECK-NEXT: mulsd %xmm2, %xmm3
212 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax)
213 ; CHECK-NEXT: addq $8, %rax
214 ; CHECK-NEXT: jne .LBB4_1
215 ; CHECK-NEXT: # %bb.2: # %return
216 ; CHECK-NEXT: retq
147217 entry:
148218 br label %loop
149219
171241 ret void
172242 }
173243
174 ; CHECK-LABEL: another_count_down
175 ; CHECK-NOT: {{and|movz|sar|shl}}
176 ; CHECK: addq $-8
177 ; CHECK-NOT: {{and|movz|sar|shl}}
178 ; CHECK: jne
179244 define void @another_count_down(double* %d, i64 %n) nounwind {
245 ; CHECK-LABEL: another_count_down:
246 ; CHECK: # %bb.0: # %entry
247 ; CHECK-NEXT: movq $-2040, %rax # imm = 0xF808
248 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
249 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
250 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
251 ; CHECK-NEXT: movq %rdi, %rcx
252 ; CHECK-NEXT: movq %rdi, %rdx
253 ; CHECK-NEXT: .p2align 4, 0x90
254 ; CHECK-NEXT: .LBB5_1: # %loop
255 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
256 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
257 ; CHECK-NEXT: mulsd %xmm0, %xmm3
258 ; CHECK-NEXT: movsd %xmm3, 2040(%rdi,%rax)
259 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
260 ; CHECK-NEXT: divsd %xmm1, %xmm3
261 ; CHECK-NEXT: movsd %xmm3, (%rcx)
262 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
263 ; CHECK-NEXT: mulsd %xmm2, %xmm3
264 ; CHECK-NEXT: movsd %xmm3, (%rdx)
265 ; CHECK-NEXT: addq $-8, %rdx
266 ; CHECK-NEXT: addq $134217720, %rcx # imm = 0x7FFFFF8
267 ; CHECK-NEXT: addq $2040, %rax # imm = 0x7F8
268 ; CHECK-NEXT: jne .LBB5_1
269 ; CHECK-NEXT: # %bb.2: # %return
270 ; CHECK-NEXT: retq
180271 entry:
181272 br label %loop
182273
204295 ret void
205296 }
206297
207 ; CHECK-LABEL: another_count_up_signed
208 ; CHECK-NOT: {{and|movz|sar|shl}}
209 ; CHECK: addq $8
210 ; CHECK-NOT: {{and|movz|sar|shl}}
211 ; CHECK: jne
212298 define void @another_count_up_signed(double* %d, i64 %n) nounwind {
299 ; CHECK-LABEL: another_count_up_signed:
300 ; CHECK: # %bb.0: # %entry
301 ; CHECK-NEXT: movq $-8, %rax
302 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
303 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
304 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
305 ; CHECK-NEXT: .p2align 4, 0x90
306 ; CHECK-NEXT: .LBB6_1: # %loop
307 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
308 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
309 ; CHECK-NEXT: mulsd %xmm0, %xmm3
310 ; CHECK-NEXT: divsd %xmm1, %xmm3
311 ; CHECK-NEXT: mulsd %xmm2, %xmm3
312 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax)
313 ; CHECK-NEXT: addq $8, %rax
314 ; CHECK-NEXT: jne .LBB6_1
315 ; CHECK-NEXT: # %bb.2: # %return
316 ; CHECK-NEXT: retq
213317 entry:
214318 br label %loop
215319
239343 ret void
240344 }
241345
242 ; CHECK-LABEL: another_count_down_signed
243 ; CHECK-NOT: {{and|movz|sar|shl}}
244 ; CHECK: addq $-8
245 ; CHECK-NOT: {{and|movz|sar|shl}}
246 ; CHECK: jne
247346 define void @another_count_down_signed(double* %d, i64 %n) nounwind {
347 ; CHECK-LABEL: another_count_down_signed:
348 ; CHECK: # %bb.0: # %entry
349 ; CHECK-NEXT: movl $8, %eax
350 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
351 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
352 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
353 ; CHECK-NEXT: .p2align 4, 0x90
354 ; CHECK-NEXT: .LBB7_1: # %loop
355 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
356 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
357 ; CHECK-NEXT: mulsd %xmm0, %xmm3
358 ; CHECK-NEXT: divsd %xmm1, %xmm3
359 ; CHECK-NEXT: mulsd %xmm2, %xmm3
360 ; CHECK-NEXT: movsd %xmm3, -8(%rdi,%rax)
361 ; CHECK-NEXT: addq $-8, %rax
362 ; CHECK-NEXT: jne .LBB7_1
363 ; CHECK-NEXT: # %bb.2: # %return
364 ; CHECK-NEXT: retq
248365 entry:
249366 br label %loop
250367
None ; RUN: llc < %s -mtriple=x86_64-- > %t
1 ; RUN: grep and %t | count 6
2 ; RUN: grep movzb %t | count 6
3 ; RUN: grep sar %t | count 12
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
42
53 ; Don't optimize away zext-inreg and sext-inreg on the loop induction
64 ; variable, because it isn't safe to do so in these cases.
75
86 define void @count_up(double* %d, i64 %n) nounwind {
7 ; CHECK-LABEL: count_up:
8 ; CHECK: # %bb.0: # %entry
9 ; CHECK-NEXT: movl $10, %eax
10 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
11 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
12 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
13 ; CHECK-NEXT: .p2align 4, 0x90
14 ; CHECK-NEXT: .LBB0_1: # %loop
15 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
16 ; CHECK-NEXT: movzbl %al, %ecx
17 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
18 ; CHECK-NEXT: mulsd %xmm0, %xmm3
19 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rcx,8)
20 ; CHECK-NEXT: movl %eax, %ecx
21 ; CHECK-NEXT: andl $16777215, %ecx # imm = 0xFFFFFF
22 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
23 ; CHECK-NEXT: mulsd %xmm1, %xmm3
24 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rcx,8)
25 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
26 ; CHECK-NEXT: mulsd %xmm2, %xmm3
27 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
28 ; CHECK-NEXT: incq %rax
29 ; CHECK-NEXT: jne .LBB0_1
30 ; CHECK-NEXT: # %bb.2: # %return
31 ; CHECK-NEXT: retq
932 entry:
1033 br label %loop
1134
3457 }
3558
3659 define void @count_down(double* %d, i64 %n) nounwind {
60 ; CHECK-LABEL: count_down:
61 ; CHECK: # %bb.0: # %entry
62 ; CHECK-NEXT: movl $10, %eax
63 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
64 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
65 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
66 ; CHECK-NEXT: .p2align 4, 0x90
67 ; CHECK-NEXT: .LBB1_1: # %loop
68 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
69 ; CHECK-NEXT: movzbl %al, %ecx
70 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
71 ; CHECK-NEXT: mulsd %xmm0, %xmm3
72 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rcx,8)
73 ; CHECK-NEXT: movl %eax, %ecx
74 ; CHECK-NEXT: andl $16777215, %ecx # imm = 0xFFFFFF
75 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
76 ; CHECK-NEXT: mulsd %xmm1, %xmm3
77 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rcx,8)
78 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
79 ; CHECK-NEXT: mulsd %xmm2, %xmm3
80 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
81 ; CHECK-NEXT: decq %rax
82 ; CHECK-NEXT: cmpq $20, %rax
83 ; CHECK-NEXT: jne .LBB1_1
84 ; CHECK-NEXT: # %bb.2: # %return
85 ; CHECK-NEXT: retq
3786 entry:
3887 br label %loop
3988
62111 }
63112
64113 define void @count_up_signed(double* %d, i64 %n) nounwind {
114 ; CHECK-LABEL: count_up_signed:
115 ; CHECK: # %bb.0: # %entry
116 ; CHECK-NEXT: movl $10, %eax
117 ; CHECK-NEXT: movl $167772160, %ecx # imm = 0xA000000
118 ; CHECK-NEXT: movl $2560, %edx # imm = 0xA00
119 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
120 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
121 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
122 ; CHECK-NEXT: .p2align 4, 0x90
123 ; CHECK-NEXT: .LBB2_1: # %loop
124 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
125 ; CHECK-NEXT: movq %rdx, %rsi
126 ; CHECK-NEXT: sarq $8, %rsi
127 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
128 ; CHECK-NEXT: mulsd %xmm0, %xmm3
129 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rsi,8)
130 ; CHECK-NEXT: movq %rcx, %rsi
131 ; CHECK-NEXT: sarq $24, %rsi
132 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
133 ; CHECK-NEXT: mulsd %xmm1, %xmm3
134 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rsi,8)
135 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
136 ; CHECK-NEXT: mulsd %xmm2, %xmm3
137 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
138 ; CHECK-NEXT: addq $16777216, %rcx # imm = 0x1000000
139 ; CHECK-NEXT: addq $256, %rdx # imm = 0x100
140 ; CHECK-NEXT: incq %rax
141 ; CHECK-NEXT: jne .LBB2_1
142 ; CHECK-NEXT: # %bb.2: # %return
143 ; CHECK-NEXT: retq
65144 entry:
66145 br label %loop
67146
92171 }
93172
94173 define void @count_down_signed(double* %d, i64 %n) nounwind {
174 ; CHECK-LABEL: count_down_signed:
175 ; CHECK: # %bb.0: # %entry
176 ; CHECK-NEXT: movq $-10, %rax
177 ; CHECK-NEXT: movl $167772160, %ecx # imm = 0xA000000
178 ; CHECK-NEXT: movl $2560, %edx # imm = 0xA00
179 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
180 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
181 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
182 ; CHECK-NEXT: .p2align 4, 0x90
183 ; CHECK-NEXT: .LBB3_1: # %loop
184 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
185 ; CHECK-NEXT: movq %rdx, %rsi
186 ; CHECK-NEXT: sarq $8, %rsi
187 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
188 ; CHECK-NEXT: mulsd %xmm0, %xmm3
189 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rsi,8)
190 ; CHECK-NEXT: movq %rcx, %rsi
191 ; CHECK-NEXT: sarq $24, %rsi
192 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
193 ; CHECK-NEXT: mulsd %xmm1, %xmm3
194 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rsi,8)
195 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
196 ; CHECK-NEXT: mulsd %xmm2, %xmm3
197 ; CHECK-NEXT: movsd %xmm3, 160(%rdi,%rax,8)
198 ; CHECK-NEXT: addq $-16777216, %rcx # imm = 0xFF000000
199 ; CHECK-NEXT: addq $-256, %rdx
200 ; CHECK-NEXT: decq %rax
201 ; CHECK-NEXT: jne .LBB3_1
202 ; CHECK-NEXT: # %bb.2: # %return
203 ; CHECK-NEXT: retq
95204 entry:
96205 br label %loop
97206
122231 }
123232
124233 define void @another_count_up(double* %d, i64 %n) nounwind {
234 ; CHECK-LABEL: another_count_up:
235 ; CHECK: # %bb.0: # %entry
236 ; CHECK-NEXT: xorl %eax, %eax
237 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
238 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
239 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
240 ; CHECK-NEXT: .p2align 4, 0x90
241 ; CHECK-NEXT: .LBB4_1: # %loop
242 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
243 ; CHECK-NEXT: movzbl %al, %ecx
244 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
245 ; CHECK-NEXT: mulsd %xmm0, %xmm3
246 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rcx,8)
247 ; CHECK-NEXT: movl %eax, %ecx
248 ; CHECK-NEXT: andl $16777215, %ecx # imm = 0xFFFFFF
249 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
250 ; CHECK-NEXT: mulsd %xmm1, %xmm3
251 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rcx,8)
252 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
253 ; CHECK-NEXT: mulsd %xmm2, %xmm3
254 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
255 ; CHECK-NEXT: incq %rax
256 ; CHECK-NEXT: cmpq %rax, %rsi
257 ; CHECK-NEXT: jne .LBB4_1
258 ; CHECK-NEXT: # %bb.2: # %return
259 ; CHECK-NEXT: retq
125260 entry:
126261 br label %loop
127262
150285 }
151286
152287 define void @another_count_down(double* %d, i64 %n) nounwind {
288 ; CHECK-LABEL: another_count_down:
289 ; CHECK: # %bb.0: # %entry
290 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
291 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
292 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
293 ; CHECK-NEXT: .p2align 4, 0x90
294 ; CHECK-NEXT: .LBB5_1: # %loop
295 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
296 ; CHECK-NEXT: movzbl %sil, %eax
297 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
298 ; CHECK-NEXT: mulsd %xmm0, %xmm3
299 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
300 ; CHECK-NEXT: movl %esi, %eax
301 ; CHECK-NEXT: andl $16777215, %eax # imm = 0xFFFFFF
302 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
303 ; CHECK-NEXT: mulsd %xmm1, %xmm3
304 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
305 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
306 ; CHECK-NEXT: mulsd %xmm2, %xmm3
307 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rsi,8)
308 ; CHECK-NEXT: decq %rsi
309 ; CHECK-NEXT: cmpq $10, %rsi
310 ; CHECK-NEXT: jne .LBB5_1
311 ; CHECK-NEXT: # %bb.2: # %return
312 ; CHECK-NEXT: retq
153313 entry:
154314 br label %loop
155315
178338 }
179339
180340 define void @another_count_up_signed(double* %d, i64 %n) nounwind {
341 ; CHECK-LABEL: another_count_up_signed:
342 ; CHECK: # %bb.0: # %entry
343 ; CHECK-NEXT: xorl %r8d, %r8d
344 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
345 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
346 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
347 ; CHECK-NEXT: xorl %ecx, %ecx
348 ; CHECK-NEXT: movq %rdi, %rdx
349 ; CHECK-NEXT: .p2align 4, 0x90
350 ; CHECK-NEXT: .LBB6_1: # %loop
351 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
352 ; CHECK-NEXT: movq %r8, %rax
353 ; CHECK-NEXT: sarq $8, %rax
354 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
355 ; CHECK-NEXT: mulsd %xmm0, %xmm3
356 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
357 ; CHECK-NEXT: movq %rcx, %rax
358 ; CHECK-NEXT: sarq $24, %rax
359 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
360 ; CHECK-NEXT: mulsd %xmm1, %xmm3
361 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
362 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
363 ; CHECK-NEXT: mulsd %xmm2, %xmm3
364 ; CHECK-NEXT: movsd %xmm3, (%rdx)
365 ; CHECK-NEXT: addq $8, %rdx
366 ; CHECK-NEXT: addq $16777216, %rcx # imm = 0x1000000
367 ; CHECK-NEXT: addq $256, %r8 # imm = 0x100
368 ; CHECK-NEXT: decq %rsi
369 ; CHECK-NEXT: jne .LBB6_1
370 ; CHECK-NEXT: # %bb.2: # %return
371 ; CHECK-NEXT: retq
181372 entry:
182373 br label %loop
183374
208399 }
209400
210401 define void @another_count_down_signed(double* %d, i64 %n) nounwind {
402 ; CHECK-LABEL: another_count_down_signed:
403 ; CHECK: # %bb.0: # %entry
404 ; CHECK-NEXT: movq %rsi, %rax
405 ; CHECK-NEXT: shlq $24, %rax
406 ; CHECK-NEXT: leaq -10(%rsi), %rcx
407 ; CHECK-NEXT: shlq $8, %rsi
408 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
409 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
410 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
411 ; CHECK-NEXT: .p2align 4, 0x90
412 ; CHECK-NEXT: .LBB7_1: # %loop
413 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
414 ; CHECK-NEXT: movq %rsi, %rdx
415 ; CHECK-NEXT: sarq $8, %rdx
416 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
417 ; CHECK-NEXT: mulsd %xmm0, %xmm3
418 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rdx,8)
419 ; CHECK-NEXT: movq %rax, %rdx
420 ; CHECK-NEXT: sarq $24, %rdx
421 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
422 ; CHECK-NEXT: mulsd %xmm1, %xmm3
423 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rdx,8)
424 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
425 ; CHECK-NEXT: mulsd %xmm2, %xmm3
426 ; CHECK-NEXT: movsd %xmm3, 80(%rdi,%rcx,8)
427 ; CHECK-NEXT: addq $-16777216, %rax # imm = 0xFF000000
428 ; CHECK-NEXT: addq $-256, %rsi
429 ; CHECK-NEXT: decq %rcx
430 ; CHECK-NEXT: jne .LBB7_1
431 ; CHECK-NEXT: # %bb.2: # %return
432 ; CHECK-NEXT: retq
211433 entry:
212434 br label %loop
213435
238460 }
239461
240462 define void @yet_another_count_down(double* %d, i64 %n) nounwind {
463 ; CHECK-LABEL: yet_another_count_down:
464 ; CHECK: # %bb.0: # %entry
465 ; CHECK-NEXT: movq $-2040, %rax # imm = 0xF808
466 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
467 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
468 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
469 ; CHECK-NEXT: movq %rdi, %rcx
470 ; CHECK-NEXT: movq %rdi, %rdx
471 ; CHECK-NEXT: .p2align 4, 0x90
472 ; CHECK-NEXT: .LBB8_1: # %loop
473 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
474 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
475 ; CHECK-NEXT: mulsd %xmm0, %xmm3
476 ; CHECK-NEXT: movsd %xmm3, 2040(%rdi,%rax)
477 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
478 ; CHECK-NEXT: mulsd %xmm1, %xmm3
479 ; CHECK-NEXT: movsd %xmm3, (%rcx)
480 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
481 ; CHECK-NEXT: mulsd %xmm2, %xmm3
482 ; CHECK-NEXT: movsd %xmm3, (%rdx)
483 ; CHECK-NEXT: addq $-8, %rdx
484 ; CHECK-NEXT: addq $134217720, %rcx # imm = 0x7FFFFF8
485 ; CHECK-NEXT: addq $2040, %rax # imm = 0x7F8
486 ; CHECK-NEXT: jne .LBB8_1
487 ; CHECK-NEXT: # %bb.2: # %return
488 ; CHECK-NEXT: retq
241489 entry:
242490 br label %loop
243491
266514 }
267515
268516 define void @yet_another_count_up(double* %d, i64 %n) nounwind {
517 ; CHECK-LABEL: yet_another_count_up:
518 ; CHECK: # %bb.0: # %entry
519 ; CHECK-NEXT: xorl %eax, %eax
520 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
521 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
522 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
523 ; CHECK-NEXT: .p2align 4, 0x90
524 ; CHECK-NEXT: .LBB9_1: # %loop
525 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
526 ; CHECK-NEXT: movzbl %al, %ecx
527 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
528 ; CHECK-NEXT: mulsd %xmm0, %xmm3
529 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rcx,8)
530 ; CHECK-NEXT: movl %eax, %ecx
531 ; CHECK-NEXT: andl $16777215, %ecx # imm = 0xFFFFFF
532 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
533 ; CHECK-NEXT: mulsd %xmm1, %xmm3
534 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rcx,8)
535 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
536 ; CHECK-NEXT: mulsd %xmm2, %xmm3
537 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
538 ; CHECK-NEXT: addq $3, %rax
539 ; CHECK-NEXT: cmpq $10, %rax
540 ; CHECK-NEXT: jne .LBB9_1
541 ; CHECK-NEXT: # %bb.2: # %return
542 ; CHECK-NEXT: retq
269543 entry:
270544 br label %loop
271545
294568 }
295569
296570 define void @still_another_count_down(double* %d, i64 %n) nounwind {
571 ; CHECK-LABEL: still_another_count_down:
572 ; CHECK: # %bb.0: # %entry
573 ; CHECK-NEXT: movl $10, %eax
574 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
575 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
576 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
577 ; CHECK-NEXT: .p2align 4, 0x90
578 ; CHECK-NEXT: .LBB10_1: # %loop
579 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
580 ; CHECK-NEXT: movzbl %al, %ecx
581 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
582 ; CHECK-NEXT: mulsd %xmm0, %xmm3
583 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rcx,8)
584 ; CHECK-NEXT: movl %eax, %ecx
585 ; CHECK-NEXT: andl $16777215, %ecx # imm = 0xFFFFFF
586 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
587 ; CHECK-NEXT: mulsd %xmm1, %xmm3
588 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rcx,8)
589 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
590 ; CHECK-NEXT: mulsd %xmm2, %xmm3
591 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
592 ; CHECK-NEXT: addq $-3, %rax
593 ; CHECK-NEXT: jne .LBB10_1
594 ; CHECK-NEXT: # %bb.2: # %return
595 ; CHECK-NEXT: retq
297596 entry:
298597 br label %loop
299598
322621 }
323622
324623 define void @yet_another_count_up_signed(double* %d, i64 %n) nounwind {
624 ; CHECK-LABEL: yet_another_count_up_signed:
625 ; CHECK: # %bb.0: # %entry
626 ; CHECK-NEXT: movq $-10, %rax
627 ; CHECK-NEXT: xorl %ecx, %ecx
628 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
629 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
630 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
631 ; CHECK-NEXT: xorl %edx, %edx
632 ; CHECK-NEXT: .p2align 4, 0x90
633 ; CHECK-NEXT: .LBB11_1: # %loop
634 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
635 ; CHECK-NEXT: movq %rcx, %rsi
636 ; CHECK-NEXT: sarq $8, %rsi
637 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
638 ; CHECK-NEXT: mulsd %xmm0, %xmm3
639 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rsi,8)
640 ; CHECK-NEXT: movq %rdx, %rsi
641 ; CHECK-NEXT: sarq $24, %rsi
642 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
643 ; CHECK-NEXT: mulsd %xmm1, %xmm3
644 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rsi,8)
645 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
646 ; CHECK-NEXT: mulsd %xmm2, %xmm3
647 ; CHECK-NEXT: movsd %xmm3, 80(%rdi,%rax,8)
648 ; CHECK-NEXT: addq $50331648, %rdx # imm = 0x3000000
649 ; CHECK-NEXT: addq $768, %rcx # imm = 0x300
650 ; CHECK-NEXT: addq $3, %rax
651 ; CHECK-NEXT: jne .LBB11_1
652 ; CHECK-NEXT: # %bb.2: # %return
653 ; CHECK-NEXT: retq
325654 entry:
326655 br label %loop
327656
352681 }
353682
354683 define void @yet_another_count_down_signed(double* %d, i64 %n) nounwind {
684 ; CHECK-LABEL: yet_another_count_down_signed:
685 ; CHECK: # %bb.0: # %entry
686 ; CHECK-NEXT: movl $10, %eax
687 ; CHECK-NEXT: movl $167772160, %ecx # imm = 0xA000000
688 ; CHECK-NEXT: movl $2560, %edx # imm = 0xA00
689 ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
690 ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
691 ; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
692 ; CHECK-NEXT: .p2align 4, 0x90
693 ; CHECK-NEXT: .LBB12_1: # %loop
694 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
695 ; CHECK-NEXT: movq %rdx, %rsi
696 ; CHECK-NEXT: sarq $8, %rsi
697 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
698 ; CHECK-NEXT: mulsd %xmm0, %xmm3
699 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rsi,8)
700 ; CHECK-NEXT: movq %rcx, %rsi
701 ; CHECK-NEXT: sarq $24, %rsi
702 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
703 ; CHECK-NEXT: mulsd %xmm1, %xmm3
704 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rsi,8)
705 ; CHECK-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
706 ; CHECK-NEXT: mulsd %xmm2, %xmm3
707 ; CHECK-NEXT: movsd %xmm3, (%rdi,%rax,8)
708 ; CHECK-NEXT: addq $-50331648, %rcx # imm = 0xFD000000
709 ; CHECK-NEXT: addq $-768, %rdx # imm = 0xFD00
710 ; CHECK-NEXT: addq $-3, %rax
711 ; CHECK-NEXT: jne .LBB12_1
712 ; CHECK-NEXT: # %bb.2: # %return
713 ; CHECK-NEXT: retq
355714 entry:
356715 br label %loop
357716
None ; RUN: llc -mtriple=i386-apple-darwin < %s | not grep memset
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=i386-apple-darwin < %s | FileCheck %s --implicit-check-not memset
12 ; PR6767
23
34 define void @t() nounwind ssp {
5 ; CHECK-LABEL: t:
6 ; CHECK: ## %bb.0: ## %entry
7 ; CHECK-NEXT: subl $512, %esp ## imm = 0x200
8 ; CHECK-NEXT: ud2
49 entry:
510 %buf = alloca [512 x i8], align 1
611 %ptr = getelementptr inbounds [512 x i8], [512 x i8]* %buf, i32 0, i32 0
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; Make sure that we realign the stack. Mingw32 uses 4 byte stack alignment, we
12 ; need 16 bytes for SSE and 32 bytes for AVX.
23
3 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium2 | FileCheck %s -check-prefix=NOSSE
4 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium3 | FileCheck %s -check-prefix=SSE1
5 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=yonah | FileCheck %s -check-prefix=SSE2
6 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX1
7 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2
4 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium2 | FileCheck %s --check-prefix=NOSSE
5 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=pentium3 | FileCheck %s --check-prefixes=SSE,SSE1
6 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=yonah | FileCheck %s --check-prefixes=SSE,SSE2
7 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=corei7-avx | FileCheck %s --check-prefixes=AVX,AVX1
8 ; RUN: llc < %s -mtriple=i386-pc-mingw32 -mcpu=core-avx2 | FileCheck %s --check-prefixes=AVX,AVX2
89
910 define void @test1(i32 %t) nounwind {
11 ; NOSSE-LABEL: test1:
12 ; NOSSE: # %bb.0:
13 ; NOSSE-NEXT: pushl %ebp
14 ; NOSSE-NEXT: movl %esp, %ebp
15 ; NOSSE-NEXT: subl $32, %esp
16 ; NOSSE-NEXT: movl 8(%ebp), %eax
17 ; NOSSE-NEXT: movl $0, -4(%ebp)
18 ; NOSSE-NEXT: movl $0, -8(%ebp)
19 ; NOSSE-NEXT: movl $0, -12(%ebp)
20 ; NOSSE-NEXT: movl $0, -16(%ebp)
21 ; NOSSE-NEXT: movl $0, -20(%ebp)
22 ; NOSSE-NEXT: movl $0, -24(%ebp)
23 ; NOSSE-NEXT: movl $0, -28(%ebp)
24 ; NOSSE-NEXT: movl $0, -32(%ebp)
25 ; NOSSE-NEXT: addl $3, %eax
26 ; NOSSE-NEXT: andl $-4, %eax
27 ; NOSSE-NEXT: calll __alloca
28 ; NOSSE-NEXT: movl %esp, %eax
29 ; NOSSE-NEXT: pushl %eax
30 ; NOSSE-NEXT: calll _dummy
31 ; NOSSE-NEXT: movl %ebp, %esp
32 ; NOSSE-NEXT: popl %ebp
33 ; NOSSE-NEXT: retl
34 ;
35 ; SSE-LABEL: test1:
36 ; SSE: # %bb.0:
37 ; SSE-NEXT: pushl %ebp
38 ; SSE-NEXT: movl %esp, %ebp
39 ; SSE-NEXT: pushl %esi
40 ; SSE-NEXT: andl $-16, %esp
41 ; SSE-NEXT: subl $48, %esp
42 ; SSE-NEXT: movl %esp, %esi
43 ; SSE-NEXT: movl 8(%ebp), %eax
44 ; SSE-NEXT: xorps %xmm0, %xmm0
45 ; SSE-NEXT: movaps %xmm0, 16(%esi)
46 ; SSE-NEXT: movaps %xmm0, (%esi)
47 ; SSE-NEXT: addl $3, %eax
48 ; SSE-NEXT: andl $-4, %eax
49 ; SSE-NEXT: calll __alloca
50 ; SSE-NEXT: movl %esp, %eax
51 ; SSE-NEXT: pushl %eax
52 ; SSE-NEXT: calll _dummy
53 ; SSE-NEXT: leal -4(%ebp), %esp
54 ; SSE-NEXT: popl %esi
55 ; SSE-NEXT: popl %ebp
56 ; SSE-NEXT: retl
57 ;
58 ; AVX-LABEL: test1:
59 ; AVX: # %bb.0:
60 ; AVX-NEXT: pushl %ebp
61 ; AVX-NEXT: movl %esp, %ebp
62 ; AVX-NEXT: pushl %esi
63 ; AVX-NEXT: andl $-32, %esp
64 ; AVX-NEXT: subl $64, %esp
65 ; AVX-NEXT: movl %esp, %esi
66 ; AVX-NEXT: movl 8(%ebp), %eax
67 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
68 ; AVX-NEXT: vmovaps %ymm0, (%esi)
69 ; AVX-NEXT: addl $3, %eax
70 ; AVX-NEXT: andl $-4, %eax
71 ; AVX-NEXT: calll __alloca
72 ; AVX-NEXT: movl %esp, %eax
73 ; AVX-NEXT: pushl %eax
74 ; AVX-NEXT: vzeroupper
75 ; AVX-NEXT: calll _dummy
76 ; AVX-NEXT: leal -4(%ebp), %esp
77 ; AVX-NEXT: popl %esi
78 ; AVX-NEXT: popl %ebp
79 ; AVX-NEXT: retl
1080 %tmp1210 = alloca i8, i32 32, align 4
1181 call void @llvm.memset.p0i8.i64(i8* align 4 %tmp1210, i8 0, i64 32, i1 false)
1282 %x = alloca i8, i32 %t
1383 call void @dummy(i8* %x)
1484 ret void
15
16 ; NOSSE-LABEL: test1:
17 ; NOSSE-NOT: and
18 ; NOSSE: movl $0
19
20 ; SSE1-LABEL: test1:
21 ; SSE1: andl $-16
22 ; SSE1: movl %esp, %esi
23 ; SSE1: movaps
24
25 ; SSE2-LABEL: test1:
26 ; SSE2: andl $-16
27 ; SSE2: movl %esp, %esi
28 ; SSE2: movaps
29
30 ; AVX1-LABEL: test1:
31 ; AVX1: andl $-32
32 ; AVX1: movl %esp, %esi
33 ; AVX1: vmovaps %ymm
34
35 ; AVX2-LABEL: test1:
36 ; AVX2: andl $-32
37 ; AVX2: movl %esp, %esi
38 ; AVX2: vmovaps %ymm
39
4085 }
4186
4287 define void @test2(i32 %t) nounwind {
88 ; NOSSE-LABEL: test2:
89 ; NOSSE: # %bb.0:
90 ; NOSSE-NEXT: pushl %ebp
91 ; NOSSE-NEXT: movl %esp, %ebp
92 ; NOSSE-NEXT: subl $16, %esp
93 ; NOSSE-NEXT: movl 8(%ebp), %eax
94 ; NOSSE-NEXT: movl $0, -4(%ebp)
95 ; NOSSE-NEXT: movl $0, -8(%ebp)
96 ; NOSSE-NEXT: movl $0, -12(%ebp)
97 ; NOSSE-NEXT: movl $0, -16(%ebp)
98 ; NOSSE-NEXT: addl $3, %eax
99 ; NOSSE-NEXT: andl $-4, %eax
100 ; NOSSE-NEXT: calll __alloca
101 ; NOSSE-NEXT: movl %esp, %eax
102 ; NOSSE-NEXT: pushl %eax
103 ; NOSSE-NEXT: calll _dummy
104 ; NOSSE-NEXT: movl %ebp, %esp
105 ; NOSSE-NEXT: popl %ebp
106 ; NOSSE-NEXT: retl
107 ;
108 ; SSE-LABEL: test2:
109 ; SSE: # %bb.0:
110 ; SSE-NEXT: pushl %ebp
111 ; SSE-NEXT: movl %esp, %ebp
112 ; SSE-NEXT: pushl %esi
113 ; SSE-NEXT: andl $-16, %esp
114 ; SSE-NEXT: subl $32, %esp
115 ; SSE-NEXT: movl %esp, %esi
116 ; SSE-NEXT: movl 8(%ebp), %eax
117 ; SSE-NEXT: xorps %xmm0, %xmm0
118 ; SSE-NEXT: movaps %xmm0, (%esi)
119 ; SSE-NEXT: addl $3, %eax
120 ; SSE-NEXT: andl $-4, %eax
121 ; SSE-NEXT: calll __alloca
122 ; SSE-NEXT: movl %esp, %eax
123 ; SSE-NEXT: pushl %eax
124 ; SSE-NEXT: calll _dummy
125 ; SSE-NEXT: leal -4(%ebp), %esp
126 ; SSE-NEXT: popl %esi
127 ; SSE-NEXT: popl %ebp
128 ; SSE-NEXT: retl
129 ;
130 ; AVX-LABEL: test2:
131 ; AVX: # %bb.0:
132 ; AVX-NEXT: pushl %ebp
133 ; AVX-NEXT: movl %esp, %ebp
134 ; AVX-NEXT: pushl %esi
135 ; AVX-NEXT: andl $-16, %esp
136 ; AVX-NEXT: subl $32, %esp
137 ; AVX-NEXT: movl %esp, %esi
138 ; AVX-NEXT: movl 8(%ebp), %eax
139 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
140 ; AVX-NEXT: vmovaps %xmm0, (%esi)
141 ; AVX-NEXT: addl $3, %eax
142 ; AVX-NEXT: andl $-4, %eax
143 ; AVX-NEXT: calll __alloca
144 ; AVX-NEXT: movl %esp, %eax
145 ; AVX-NEXT: pushl %eax
146 ; AVX-NEXT: calll _dummy
147 ; AVX-NEXT: leal -4(%ebp), %esp
148 ; AVX-NEXT: popl %esi
149 ; AVX-NEXT: popl %ebp
150 ; AVX-NEXT: retl
43151 %tmp1210 = alloca i8, i32 16, align 4
44152 call void @llvm.memset.p0i8.i64(i8* align 4 %tmp1210, i8 0, i64 16, i1 false)
45153 %x = alloca i8, i32 %t
46154 call void @dummy(i8* %x)
47155 ret void
48
49 ; NOSSE-LABEL: test2:
50 ; NOSSE-NOT: and
51 ; NOSSE: movl $0
52
53 ; SSE1-LABEL: test2:
54 ; SSE1: andl $-16
55 ; SSE1: movl %esp, %esi
56 ; SSE1: movaps
57
58 ; SSE2-LABEL: test2:
59 ; SSE2: andl $-16
60 ; SSE2: movl %esp, %esi
61 ; SSE2: movaps
62
63 ; AVX1-LABEL: test2:
64 ; AVX1: andl $-16
65 ; AVX1: movl %esp, %esi
66 ; AVX1: vmovaps %xmm
67
68 ; AVX2-LABEL: test2:
69 ; AVX2: andl $-16
70 ; AVX2: movl %esp, %esi
71 ; AVX2: vmovaps %xmm
72156 }
73157
74158 declare void @dummy(i8*)
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
12
2 ; CHECK-LABEL: {{^}}same_dynamic_index_fp_vector_type:
3 ; CHECK: # %bb.0:
4 ; CHECK-NEXT: retq
53 define float @same_dynamic_index_fp_vector_type(float %val, i32 %idx) {
4 ; CHECK-LABEL: same_dynamic_index_fp_vector_type:
5 ; CHECK: # %bb.0: # %bb
6 ; CHECK-NEXT: retq
67 bb:
78 %tmp0 = insertelement <4 x float> undef, float %val, i32 %idx
89 %tmp1 = extractelement <4 x float> %tmp0, i32 %idx
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
12
23 define void @redundant_add(i64 %n) {
34 ; Check that we don't create two additions for the sadd.with.overflow.
4 ; CHECK-LABEL: redundant_add
5 ; CHECK-NOT: leaq
6 ; CHECK-NOT: addq
7 ; CHECK: incq
8 ; CHECK-NEXT: jno
5 ; CHECK-LABEL: redundant_add:
6 ; CHECK: ## %bb.0: ## %entry
7 ; CHECK-NEXT: xorl %eax, %eax
8 ; CHECK-NEXT: .p2align 4, 0x90
9 ; CHECK-NEXT: LBB0_1: ## %exit_check
10 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
11 ; CHECK-NEXT: cmpq %rdi, %rax
12 ; CHECK-NEXT: jge LBB0_4
13 ; CHECK-NEXT: ## %bb.2: ## %loop
14 ; CHECK-NEXT: ## in Loop: Header=BB0_1 Depth=1
15 ; CHECK-NEXT: incq %rax
16 ; CHECK-NEXT: jno LBB0_1
17 ; CHECK-NEXT: ## %bb.3: ## %overflow
18 ; CHECK-NEXT: ud2
19 ; CHECK-NEXT: LBB0_4: ## %exit
20 ; CHECK-NEXT: retq
921 entry:
1022 br label %exit_check
1123
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
12
23 define i32 @test1(i64 %a) nounwind {
4 ; CHECK-LABEL: test1:
5 ; CHECK: # %bb.0:
6 ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
7 ; CHECK-NEXT: shrl %eax
8 ; CHECK-NEXT: cwtl
9 ; CHECK-NEXT: retl
310 %tmp29 = lshr i64 %a, 24 ; [#uses=1]
411 %tmp23 = trunc i64 %tmp29 to i32 ; [#uses=1]
512 %tmp410 = lshr i32 %tmp23, 9 ; [#uses=1]
613 %tmp45 = trunc i32 %tmp410 to i16 ; [#uses=1]
714 %tmp456 = sext i16 %tmp45 to i32 ; [#uses=1]
815 ret i32 %tmp456
9
10 ; CHECK-LABEL: test1:
11 ; CHECK: movl 8(%esp), %eax
12 ; CHECK: shrl %eax
13 ; CHECK: cwtl
1416 }
1517
None ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
12
23 ; Verify that DAGCombiner does not crash when checking if it is
34 ; safe to fold the shuffles in function @sample_test according to rule
1415 ; As a consequence, compiling the function below would have caused a crash.
1516
1617 define void @sample_test() {
18 ; CHECK-LABEL: sample_test:
19 ; CHECK: # %bb.0:
20 ; CHECK-NEXT: xorl %eax, %eax
21 ; CHECK-NEXT: testb %al, %al
22 ; CHECK-NEXT: jne .LBB0_2
23 ; CHECK-NEXT: # %bb.1:
24 ; CHECK-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
25 ; CHECK-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
26 ; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
27 ; CHECK-NEXT: movd %xmm0, (%rax)
28 ; CHECK-NEXT: .LBB0_2:
29 ; CHECK-NEXT: retq
1730 br i1 undef, label %5, label %1
1831
1932 ;
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 | FileCheck %s --check-prefix=SSE2
12 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE2
23 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx | FileCheck %s --check-prefix=AVX
34 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=AVX
45
56 define float @test_sqrt_f32(float %a) {
6 ; SSE2-LABEL: test_sqrt_f32
7 ; SSE2: sqrtss %xmm0, %xmm0
8 ; AVX-LABEL: test_sqrt_f32
9 ; AVX: vsqrtss %xmm0, %xmm0
7 ; SSE2-LABEL: test_sqrt_f32:
8 ; SSE2: ## %bb.0:
9 ; SSE2-NEXT: sqrtss %xmm0, %xmm0
10 ; SSE2-NEXT: retq
11 ;
12 ; AVX-LABEL: test_sqrt_f32:
13 ; AVX: ## %bb.0:
14 ; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
15 ; AVX-NEXT: retq
1016 %res = call float @llvm.sqrt.f32(float %a)
1117 ret float %res
1218 }
1319 declare float @llvm.sqrt.f32(float) nounwind readnone
1420
1521 define double @test_sqrt_f64(double %a) {
16 ; SSE2-LABEL: test_sqrt_f64
17 ; SSE2: sqrtsd %xmm0, %xmm0
18 ; AVX-LABEL: test_sqrt_f64
19 ; AVX: vsqrtsd %xmm0, %xmm0
22 ; SSE2-LABEL: test_sqrt_f64:
23 ; SSE2: ## %bb.0:
24 ; SSE2-NEXT: sqrtsd %xmm0, %xmm0
25 ; SSE2-NEXT: retq
26 ;
27 ; AVX-LABEL: test_sqrt_f64:
28 ; AVX: ## %bb.0:
29 ; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
30 ; AVX-NEXT: retq
2031 %res = call double @llvm.sqrt.f64(double %a)
2132 ret double %res
2233 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; rdar://7860110
1 ; RUN: llc -mtriple=x86_64-apple-darwin10.2 -asm-verbose=false < %s | FileCheck %s -check-prefix=X64
2 ; RUN: llc -mtriple=i686-apple-darwin10.2 -asm-verbose=false -fixup-byte-word-insts=1 < %s | FileCheck %s -check-prefix=X32 -check-prefix=X32-BWON
3 ; RUN: llc -mtriple=i686-apple-darwin10.2 -asm-verbose=false -fixup-byte-word-insts=0 < %s | FileCheck %s -check-prefix=X32 -check-prefix=X32-BWOFF
2 ; RUN: llc -mtriple=x86_64-apple-darwin10.2 < %s | FileCheck %s -check-prefix=X64
3 ; RUN: llc -mtriple=i686-apple-darwin10.2 -fixup-byte-word-insts=1 < %s | FileCheck %s -check-prefix=X32 -check-prefix=X32-BWON
4 ; RUN: llc -mtriple=i686-apple-darwin10.2 -fixup-byte-word-insts=0 < %s | FileCheck %s -check-prefix=X32 -check-prefix=X32-BWOFF
45 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
56
67 define void @test1(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
8 ; X64-LABEL: test1:
9 ; X64: ## %bb.0: ## %entry
10 ; X64-NEXT: movb %sil, (%rdi)
11 ; X64-NEXT: retq
12 ;
13 ; X32-LABEL: test1:
14 ; X32: ## %bb.0: ## %entry
15 ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
16 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
17 ; X32-NEXT: movb %al, (%ecx)
18 ; X32-NEXT: retl
719 entry:
820 %A = load i32, i32* %a0, align 4
921 %B = and i32 %A, -256 ; 0xFFFFFF00
1123 %D = or i32 %C, %B
1224 store i32 %D, i32* %a0, align 4
1325 ret void
14
15 ; X64-LABEL: test1:
16 ; X64: movb %sil, (%rdi)
17
18 ; X32-LABEL: test1:
19 ; X32: movb 8(%esp), %al
20 ; X32: movb %al, (%{{.*}})
2126 }
2227
2328 define void @test2(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
29 ; X64-LABEL: test2:
30 ; X64: ## %bb.0: ## %entry
31 ; X64-NEXT: movb %sil, 1(%rdi)
32 ; X64-NEXT: retq
33 ;
34 ; X32-LABEL: test2:
35 ; X32: ## %bb.0: ## %entry
36 ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
37 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
38 ; X32-NEXT: movb %al, 1(%ecx)
39 ; X32-NEXT: retl
2440 entry:
2541 %A = load i32, i32* %a0, align 4
2642 %B = and i32 %A, -65281 ; 0xFFFF00FF
2945 %D = or i32 %B, %CS
3046 store i32 %D, i32* %a0, align 4
3147 ret void
32 ; X64-LABEL: test2:
33 ; X64: movb %sil, 1(%rdi)
34
35 ; X32-LABEL: test2:
36 ; X32: movb 8(%esp), %[[REG:[abcd]]]l
37 ; X32: movb %[[REG]]l, 1(%{{.*}})
3848 }
3949
4050 define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
51 ; X64-LABEL: test3:
52 ; X64: ## %bb.0: ## %entry
53 ; X64-NEXT: movw %si, (%rdi)
54 ; X64-NEXT: retq
55 ;
56 ; X32-BWON-LABEL: test3:
57 ; X32-BWON: ## %bb.0: ## %entry
58 ; X32-BWON-NEXT: movzwl {{[0-9]+}}(%esp), %eax
59 ; X32-BWON-NEXT: movl {{[0-9]+}}(%esp), %ecx
60 ; X32-BWON-NEXT: movw %ax, (%ecx)
61 ; X32-BWON-NEXT: retl
62 ;
63 ; X32-BWOFF-LABEL: test3:
64 ; X32-BWOFF: ## %bb.0: ## %entry
65 ; X32-BWOFF-NEXT: movw {{[0-9]+}}(%esp), %ax
66 ; X32-BWOFF-NEXT: movl {{[0-9]+}}(%esp), %ecx
67 ; X32-BWOFF-NEXT: movw %ax, (%ecx)
68 ; X32-BWOFF-NEXT: retl
4169 entry:
4270 %A = load i32, i32* %a0, align 4
4371 %B = and i32 %A, -65536 ; 0xFFFF0000
4573 %D = or i32 %B, %C
4674 store i32 %D, i32* %a0, align 4
4775 ret void
48 ; X64-LABEL: test3:
49 ; X64: movw %si, (%rdi)
50
51 ; X32-LABEL: test3:
52 ; X32-BWON: movzwl 8(%esp), %eax
53 ; X32-BWOFF: movw 8(%esp), %ax
54 ; X32: movw %ax, (%{{.*}})
5576 }
5677
5778 define void @test4(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
79 ; X64-LABEL: test4:
80 ; X64: ## %bb.0: ## %entry
81 ; X64-NEXT: movw %si, 2(%rdi)
82 ; X64-NEXT: retq
83 ;
84 ; X32-BWON-LABEL: test4:
85 ; X32-BWON: ## %bb.0: ## %entry
86 ; X32-BWON-NEXT: movzwl {{[0-9]+}}(%esp), %eax
87 ; X32-BWON-NEXT: movl {{[0-9]+}}(%esp), %ecx
88 ; X32-BWON-NEXT: movw %ax, 2(%ecx)
89 ; X32-BWON-NEXT: retl
90 ;
91 ; X32-BWOFF-LABEL: test4:
92 ; X32-BWOFF: ## %bb.0: ## %entry
93 ; X32-BWOFF-NEXT: movw {{[0-9]+}}(%esp), %ax
94 ; X32-BWOFF-NEXT: movl {{[0-9]+}}(%esp), %ecx
95 ; X32-BWOFF-NEXT: movw %ax, 2(%ecx)
96 ; X32-BWOFF-NEXT: retl
5897 entry:
5998 %A = load i32, i32* %a0, align 4
6099 %B = and i32 %A, 65535 ; 0x0000FFFF
63102 %D = or i32 %B, %CS
64103 store i32 %D, i32* %a0, align 4
65104 ret void
66 ; X64-LABEL: test4:
67 ; X64: movw %si, 2(%rdi)
68
69 ; X32-LABEL: test4:
70 ; X32-BWON: movzwl 8(%esp), %e[[REG:[abcd]]]x
71 ; X32-BWOFF: movw 8(%esp), %[[REG:[abcd]]]x
72 ; X32: movw %[[REG]]x, 2(%{{.*}})
73105 }
74106
75107 define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp {
108 ; X64-LABEL: test5:
109 ; X64: ## %bb.0: ## %entry
110 ; X64-NEXT: movw %si, 2(%rdi)
111 ; X64-NEXT: retq
112 ;
113 ; X32-BWON-LABEL: test5:
114 ; X32-BWON: ## %bb.0: ## %entry
115 ; X32-BWON-NEXT: movzwl {{[0-9]+}}(%esp), %eax
116 ; X32-BWON-NEXT: movl {{[0-9]+}}(%esp), %ecx
117 ; X32-BWON-NEXT: movw %ax, 2(%ecx)
118 ; X32-BWON-NEXT: retl
119 ;
120 ; X32-BWOFF-LABEL: test5:
121 ; X32-BWOFF: ## %bb.0: ## %entry
122 ; X32-BWOFF-NEXT: movw {{[0-9]+}}(%esp), %ax
123 ; X32-BWOFF-NEXT: movl {{[0-9]+}}(%esp), %ecx
124 ; X32-BWOFF-NEXT: movw %ax, 2(%ecx)
125 ; X32-BWOFF-NEXT: retl
76126 entry:
77127 %A = load i64, i64* %a0, align 4
78128 %B = and i64 %A, -4294901761 ; 0xFFFFFFFF0000FFFF
81131 %D = or i64 %B, %CS
82132 store i64 %D, i64* %a0, align 4
83133 ret void
84 ; X64-LABEL: test5:
85 ; X64: movw %si, 2(%rdi)
86
87 ; X32-LABEL: test5:
88 ; X32-BWON: movzwl 8(%esp), %e[[REG:[abcd]]]x
89 ; X32-BWOFF: movw 8(%esp), %[[REG:[abcd]]]x
90 ; X32: movw %[[REG]]x, 2(%{{.*}})
91134 }
92135
93136 define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp {
137 ; X64-LABEL: test6:
138 ; X64: ## %bb.0: ## %entry
139 ; X64-NEXT: movb %sil, 5(%rdi)
140 ; X64-NEXT: retq
141 ;
142 ; X32-LABEL: test6:
143 ; X32: ## %bb.0: ## %entry
144 ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
145 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
146 ; X32-NEXT: movb %al, 5(%ecx)
147 ; X32-NEXT: retl
94148 entry:
95149 %A = load i64, i64* %a0, align 4
96150 %B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF
99153 %D = or i64 %B, %CS
100154 store i64 %D, i64* %a0, align 4
101155 ret void
102 ; X64-LABEL: test6:
103 ; X64: movb %sil, 5(%rdi)
104
105
106 ; X32-LABEL: test6:
107 ; X32: movb 8(%esp), %[[REG:[abcd]l]]
108 ; X32: movb %[[REG]], 5(%{{.*}})
109156 }
110157
111158 define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind {
159 ; X64-LABEL: test7:
160 ; X64: ## %bb.0: ## %entry
161 ; X64-NEXT: movl (%rdx), %eax
162 ; X64-NEXT: movb %sil, 5(%rdi)
163 ; X64-NEXT: retq
164 ;
165 ; X32-LABEL: test7:
166 ; X32: ## %bb.0: ## %entry
167 ; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
168 ; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
169 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
170 ; X32-NEXT: movl (%eax), %eax
171 ; X32-NEXT: movb %cl, 5(%edx)
172 ; X32-NEXT: retl
112173 entry:
113174 %OtherLoad = load i32 , i32 *%P2
114175 %A = load i64, i64* %a0, align 4
118179 %D = or i64 %B, %CS
119180 store i64 %D, i64* %a0, align 4
120181 ret i32 %OtherLoad
121 ; X64-LABEL: test7:
122 ; X64: movb %sil, 5(%rdi)
123
124
125 ; X32-LABEL: test7:
126 ; X32: movb 8(%esp), %[[REG:[abcd]l]]
127 ; X32: movb %[[REG]], 5(%{{.*}})
128182 }
129183
130184 ; PR7833
131185
132186 @g_16 = internal global i32 -1
133187
188 define void @test8() nounwind {
134189 ; X64-LABEL: test8:
135 ; X64-NEXT: orb $1, _g_16(%rip)
136 ; X64-NEXT: ret
137 define void @test8() nounwind {
190 ; X64: ## %bb.0:
191 ; X64-NEXT: orb $1, {{.*}}(%rip)
192 ; X64-NEXT: retq
193 ;
194 ; X32-LABEL: test8:
195 ; X32: ## %bb.0:
196 ; X32-NEXT: orb $1, _g_16
197 ; X32-NEXT: retl
138198 %tmp = load i32, i32* @g_16
139199 store i32 0, i32* @g_16
140200 %or = or i32 %tmp, 1
142202 ret void
143203 }
144204
205 define void @test9() nounwind {
145206 ; X64-LABEL: test9:
146 ; X64-NEXT: orb $1, _g_16(%rip)
147 ; X64-NEXT: ret
148 define void @test9() nounwind {
207 ; X64: ## %bb.0:
208 ; X64-NEXT: orb $1, {{.*}}(%rip)
209 ; X64-NEXT: retq
210 ;
211 ; X32-LABEL: test9:
212 ; X32: ## %bb.0:
213 ; X32-NEXT: orb $1, _g_16
214 ; X32-NEXT: retl
149215 %tmp = load i32, i32* @g_16
150216 %or = or i32 %tmp, 1
151217 store i32 %or, i32* @g_16
153219 }
154220
155221 ; rdar://8494845 + PR8244
222 define i8 @test10(i8* %P) nounwind ssp {
156223 ; X64-LABEL: test10:
157 ; X64-NEXT: movsbl (%rdi), %eax
158 ; X64-NEXT: shrl $8, %eax
159 ; X64-NEXT: ret
160 define i8 @test10(i8* %P) nounwind ssp {
224 ; X64: ## %bb.0: ## %entry
225 ; X64-NEXT: movsbl (%rdi), %eax
226 ; X64-NEXT: shrl $8, %eax
227 ; X64-NEXT: ## kill: def $al killed $al killed $eax
228 ; X64-NEXT: retq
229 ;
230 ; X32-LABEL: test10:
231 ; X32: ## %bb.0: ## %entry
232 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
233 ; X32-NEXT: movsbl (%eax), %eax
234 ; X32-NEXT: movb %ah, %al
235 ; X32-NEXT: retl
161236 entry:
162237 %tmp = load i8, i8* %P, align 1
163238 %conv = sext i8 %tmp to i32
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=x86_64-apple-macosx10.9.0 -mcpu=core2 -mattr=+64bit,+sse2 < %s | FileCheck %s
12
23 ; DAGCombine may choose to rewrite 2 loads feeding a select as a select of
67 declare void @sink(<2 x double>)
78
89 define void @test1(i1 %cmp) align 2 {
10 ; CHECK-LABEL: test1:
11 ; CHECK: ## %bb.0:
12 ; CHECK-NEXT: subq $40, %rsp
13 ; CHECK-NEXT: .cfi_def_cfa_offset 48
14 ; CHECK-NEXT: testb $1, %dil
15 ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax
16 ; CHECK-NEXT: movq %rsp, %rcx
17 ; CHECK-NEXT: cmovneq %rax, %rcx
18 ; CHECK-NEXT: movups (%rcx), %xmm0
19 ; CHECK-NEXT: callq _sink
20 ; CHECK-NEXT: addq $40, %rsp
21 ; CHECK-NEXT: retq
922 %1 = alloca <2 x double>, align 16
1023 %2 = alloca <2 x double>, align 8
1124
1427 %val3 = select i1 %cmp, <2 x double> %val, <2 x double> %val2
1528 call void @sink(<2 x double> %val3)
1629 ret void
17 ; CHECK: test1
18 ; CHECK: movups
19 ; CHECK: ret
2030 }
2131
2232 define void @test2(i1 %cmp) align 2 {
33 ; CHECK-LABEL: test2:
34 ; CHECK: ## %bb.0:
35 ; CHECK-NEXT: subq $40, %rsp
36 ; CHECK-NEXT: .cfi_def_cfa_offset 48
37 ; CHECK-NEXT: testb $1, %dil
38 ; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rax
39 ; CHECK-NEXT: movq %rsp, %rcx
40 ; CHECK-NEXT: cmovneq %rax, %rcx
41 ; CHECK-NEXT: movaps (%rcx), %xmm0
42 ; CHECK-NEXT: callq _sink
43 ; CHECK-NEXT: addq $40, %rsp
44 ; CHECK-NEXT: retq
2345 %1 = alloca <2 x double>, align 16
2446 %2 = alloca <2 x double>, align 8
2547
2850 %val3 = select i1 %cmp, <2 x double> %val, <2 x double> %val2
2951 call void @sink(<2 x double> %val3)
3052 ret void
31 ; CHECK: test2
32 ; CHECK: movaps
33 ; CHECK: ret
3453 }