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[AMDGPU] Disassembler: support for DPP Review: http://reviews.llvm.org/D18642 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265015 91177308-0d34-0410-b5e6-96231b3b80d8 Sam Kolton 4 years ago
3 changed file(s) with 112 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
8282 //
8383 //===----------------------------------------------------------------------===//
8484
85 static inline uint32_t eatB32(ArrayRef& Bytes) {
86 assert(Bytes.size() >= sizeof eatB32(Bytes));
87 const auto Res = support::endian::read32le(Bytes.data());
88 Bytes = Bytes.slice(sizeof Res);
85 template static inline T eatBytes(ArrayRef& Bytes) {
86 assert(Bytes.size() >= sizeof(T));
87 const auto Res = support::endian::read(Bytes.data());
88 Bytes = Bytes.slice(sizeof(T));
8989 return Res;
9090 }
9191
122122 do {
123123 // ToDo: better to switch encoding length using some bit predicate
124124 // but it is unknown yet, so try all we can
125
126 // Try to decode DPP first to solve conflict with VOP1 and VOP2 encodings
127 if (Bytes.size() >= 8) {
128 const uint64_t QW = eatBytes(Bytes);
129 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
130 if (Res) break;
131 }
132
133 // Reinitialize Bytes as DPP64 could have eaten too much
134 Bytes = Bytes_.slice(0, MaxInstBytesNum);
135
136 // Try decode 32-bit instruction
125137 if (Bytes.size() < 4) break;
126 const uint32_t DW = eatB32(Bytes);
138 const uint32_t DW = eatBytes(Bytes);
127139 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
128140 if (Res) break;
129141
131143 if (Res) break;
132144
133145 if (Bytes.size() < 4) break;
134 const uint64_t QW = ((uint64_t)eatB32(Bytes) << 32) | DW;
146 const uint64_t QW = ((uint64_t)eatBytes(Bytes) << 32) | DW;
135147 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
136148 if (Res) break;
137149
260272 if (Bytes.size() < 4)
261273 return errOperand(0, "cannot read literal, inst bytes left " +
262274 Twine(Bytes.size()));
263 return MCOperand::createImm(eatB32(Bytes));
275 return MCOperand::createImm(eatBytes(Bytes));
264276 }
265277
266278 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
17041704 VOP1_DPPe ,
17051705 VOP_DPP {
17061706 let AssemblerPredicates = [isVI];
1707 let DecoderNamespace = "DPP";
1708 let DisableDecoder = DisableVIDecoder;
17071709 let src0_modifiers = !if(p.HasModifiers, ?, 0);
17081710 let src1_modifiers = 0;
17091711 }
17661768 VOP2_DPPe ,
17671769 VOP_DPP {
17681770 let AssemblerPredicates = [isVI];
1771 let DecoderNamespace = "DPP";
1772 let DisableDecoder = DisableVIDecoder;
17691773 let src0_modifiers = !if(p.HasModifiers, ?, 0);
17701774 let src1_modifiers = !if(p.HasModifiers, ?, 0);
17711775 }
0 # RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
1
2 # VI: v_mov_b32_dpp v0, v0 quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x58,0x00,0xff]
3 0xfa 0x02 0x00 0x7e 0x00 0x58 0x00 0xff
4
5 # VI: v_mov_b32_dpp v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x01,0xff]
6 0xfa 0x02 0x00 0x7e 0x00 0x01 0x01 0xff
7
8 # VI: v_mov_b32_dpp v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x1f,0x01,0xff]
9 0xfa 0x02 0x00 0x7e 0x00 0x1f 0x01 0xff
10
11 # VI: v_mov_b32_dpp v0, v0 row_ror:12 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x2c,0x01,0xff]
12 0xfa 0x02 0x00 0x7e 0x00 0x2c 0x01 0xff
13
14 # VI: v_mov_b32_dpp v0, v0 wave_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x30,0x01,0xff]
15 0xfa 0x02 0x00 0x7e 0x00 0x30 0x01 0xff
16
17 # VI: v_mov_b32_dpp v0, v0 wave_rol:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x34,0x01,0xff]
18 0xfa 0x02 0x00 0x7e 0x00 0x34 0x01 0xff
19
20 # VI: v_mov_b32_dpp v0, v0 wave_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x38,0x01,0xff]
21 0xfa 0x02 0x00 0x7e 0x00 0x38 0x01 0xff
22
23 # VI: v_mov_b32_dpp v0, v0 wave_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x3c,0x01,0xff]
24 0xfa 0x02 0x00 0x7e 0x00 0x3c 0x01 0xff
25
26 # VI: v_mov_b32_dpp v0, v0 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x40,0x01,0xff]
27 0xfa 0x02 0x00 0x7e 0x00 0x40 0x01 0xff
28
29 # VI: v_mov_b32_dpp v0, v0 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x41,0x01,0xff]
30 0xfa 0x02 0x00 0x7e 0x00 0x41 0x01 0xff
31
32 # VI: v_mov_b32_dpp v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x42,0x01,0xff]
33 0xfa 0x02 0x00 0x7e 0x00 0x42 0x01 0xff
34
35 # VI: v_mov_b32_dpp v0, v0 row_bcast:31 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x43,0x01,0xff]
36 0xfa 0x02 0x00 0x7e 0x00 0x43 0x01 0xff
37
38 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xa1]
39 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xa1
40
41 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xaf]
42 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xaf
43
44 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xf1]
45 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xf1
46
47 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xff]
48 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xff
49
50 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x00,0xa1]
51 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x00 0xa1
52
53 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xaf]
54 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xaf
55
56 # VI: v_mov_b32_dpp v0, v0 quad_perm:[1,3,0,1] row_mask:0xf bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x4d,0x08,0xf1]
57 0xfa 0x02 0x00 0x7e 0x00 0x4d 0x08 0xf1
58
59 # VI: v_cvt_u32_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x0e,0x00,0x7e,0x00,0x01,0x09,0xa1]
60 0xfa 0x0e 0x00 0x7e 0x00 0x01 0x09 0xa1
61
62 # VI: v_fract_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x36,0x00,0x7e,0x00,0x01,0x09,0xa1]
63 0xfa 0x36 0x00 0x7e 0x00 0x01 0x09 0xa1
64
65 # VI: v_sin_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x52,0x00,0x7e,0x00,0x01,0x09,0xa1]
66 0xfa 0x52 0x00 0x7e 0x00 0x01 0x09 0xa1
67
68 # VI: v_add_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x09,0xa1]
69 0xfa 0x00 0x00 0x02 0x00 0x01 0x09 0xa1
70
71 # VI: v_min_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x14,0x00,0x01,0x09,0xa1]
72 0xfa 0x00 0x00 0x14 0x00 0x01 0x09 0xa1
73
74 # VI: v_and_b32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x26,0x00,0x01,0x09,0xa1]
75 0xfa 0x00 0x00 0x26 0x00 0x01 0x09 0xa1
76
77 # VI: v_add_f32_dpp v0, -v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x19,0xa1]
78 0xfa 0x00 0x00 0x02 0x00 0x01 0x19 0xa1
79
80 # VI: v_add_f32_dpp v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x89,0xa1]
81 0xfa 0x00 0x00 0x02 0x00 0x01 0x89 0xa1
82
83 # VI: v_add_f32_dpp v0, -v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x99,0xa1]
84 0xfa 0x00 0x00 0x02 0x00 0x01 0x99 0xa1
85
86 # VI: v_add_f32_dpp v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x69,0xa1]
87
88 0xfa 0x00 0x00 0x02 0x00 0x01 0x69 0xa1