llvm.org GIT mirror llvm / 8fb8da1
[ARM] Add ARMv8.2-A FP16 scalar instructions ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255762 91177308-0d34-0410-b5e6-96231b3b80d8 Oliver Stannard 4 years ago
18 changed file(s) with 1976 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
14941494 let D = VFPNeonDomain;
14951495 }
14961496
1497 class AHI5 opcod1, bits<2> opcod2, dag oops, dag iops,
1498 InstrItinClass itin,
1499 string opc, string asm, list pattern>
1500 : VFPI
1501 VFPLdStFrm, itin, opc, asm, "", pattern> {
1502 list Predicates = [HasFullFP16];
1503
1504 // Instruction operands.
1505 bits<5> Sd;
1506 bits<13> addr;
1507
1508 // Encode instruction operands.
1509 let Inst{23} = addr{8}; // U (add = (U == '1'))
1510 let Inst{22} = Sd{0};
1511 let Inst{19-16} = addr{12-9}; // Rn
1512 let Inst{15-12} = Sd{4-1};
1513 let Inst{7-0} = addr{7-0}; // imm8
1514
1515 let Inst{27-24} = opcod1;
1516 let Inst{21-20} = opcod2;
1517 let Inst{11-8} = 0b1001; // Half precision
1518
1519 // Loads & stores operate on both NEON and VFP pipelines.
1520 let D = VFPNeonDomain;
1521 }
1522
14971523 // VFP Load / store multiple pseudo instructions.
14981524 class PseudoVFPLdStM
14991525 list pattern>
18141840 let Inst{7} = Sn{0};
18151841 let Inst{15-12} = Sd{4-1};
18161842 let Inst{22} = Sd{0};
1843 }
1844
1845 // Half precision, unary, predicated
1846 class AHuI opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1847 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1848 string asm, list pattern>
1849 : VFPAI {
1850 list Predicates = [HasFullFP16];
1851
1852 // Instruction operands.
1853 bits<5> Sd;
1854 bits<5> Sm;
1855
1856 // Encode instruction operands.
1857 let Inst{3-0} = Sm{4-1};
1858 let Inst{5} = Sm{0};
1859 let Inst{15-12} = Sd{4-1};
1860 let Inst{22} = Sd{0};
1861
1862 let Inst{27-23} = opcod1;
1863 let Inst{21-20} = opcod2;
1864 let Inst{19-16} = opcod3;
1865 let Inst{11-8} = 0b1001; // Half precision
1866 let Inst{7-6} = opcod4;
1867 let Inst{4} = opcod5;
1868 }
1869
1870 // Half precision, unary, non-predicated
1871 class AHuInp opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1872 bit opcod5, dag oops, dag iops, InstrItinClass itin,
1873 string asm, list pattern>
1874 : VFPXI
1875 VFPUnaryFrm, itin, asm, "", pattern> {
1876 list Predicates = [HasFullFP16];
1877
1878 // Instruction operands.
1879 bits<5> Sd;
1880 bits<5> Sm;
1881
1882 let Inst{31-28} = 0b1111;
1883
1884 // Encode instruction operands.
1885 let Inst{3-0} = Sm{4-1};
1886 let Inst{5} = Sm{0};
1887 let Inst{15-12} = Sd{4-1};
1888 let Inst{22} = Sd{0};
1889
1890 let Inst{27-23} = opcod1;
1891 let Inst{21-20} = opcod2;
1892 let Inst{19-16} = opcod3;
1893 let Inst{11-8} = 0b1001; // Half precision
1894 let Inst{7-6} = opcod4;
1895 let Inst{4} = opcod5;
1896 }
1897
1898 // Half precision, binary
1899 class AHbI opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1900 InstrItinClass itin, string opc, string asm, list pattern>
1901 : VFPAI {
1902 list Predicates = [HasFullFP16];
1903
1904 // Instruction operands.
1905 bits<5> Sd;
1906 bits<5> Sn;
1907 bits<5> Sm;
1908
1909 // Encode instruction operands.
1910 let Inst{3-0} = Sm{4-1};
1911 let Inst{5} = Sm{0};
1912 let Inst{19-16} = Sn{4-1};
1913 let Inst{7} = Sn{0};
1914 let Inst{15-12} = Sd{4-1};
1915 let Inst{22} = Sd{0};
1916
1917 let Inst{27-23} = opcod1;
1918 let Inst{21-20} = opcod2;
1919 let Inst{11-8} = 0b1001; // Half precision
1920 let Inst{6} = op6;
1921 let Inst{4} = op4;
1922 }
1923
1924 // Half precision, binary, not predicated
1925 class AHbInp opcod1, bits<2> opcod2, bit opcod3, dag oops, dag iops,
1926 InstrItinClass itin, string asm, list pattern>
1927 : VFPXI
1928 VFPBinaryFrm, itin, asm, "", pattern> {
1929 list Predicates = [HasFullFP16];
1930
1931 // Instruction operands.
1932 bits<5> Sd;
1933 bits<5> Sn;
1934 bits<5> Sm;
1935
1936 let Inst{31-28} = 0b1111;
1937
1938 // Encode instruction operands.
1939 let Inst{3-0} = Sm{4-1};
1940 let Inst{5} = Sm{0};
1941 let Inst{19-16} = Sn{4-1};
1942 let Inst{7} = Sn{0};
1943 let Inst{15-12} = Sd{4-1};
1944 let Inst{22} = Sd{0};
1945
1946 let Inst{27-23} = opcod1;
1947 let Inst{21-20} = opcod2;
1948 let Inst{11-8} = 0b1001; // Half precision
1949 let Inst{6} = opcod3;
1950 let Inst{4} = 0;
18171951 }
18181952
18191953 // VFP conversion instructions
980980 let PrintMethod = "printAddrMode5Operand";
981981 }
982982
983 // addrmode5fp16 := reg +/- imm8*2
984 //
985 def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; }
986 class AddrMode5FP16 : Operand,
987 ComplexPattern {
988 let EncoderMethod = "getAddrMode5FP16OpValue";
989 let DecoderMethod = "DecodeAddrMode5FP16Operand";
990 let ParserMatchClass = AddrMode5FP16AsmOperand;
991 let MIOperandInfo = (ops GPR:$base, i32imm);
992 }
993
994 def addrmode5fp16 : AddrMode5FP16 {
995 let PrintMethod = "printAddrMode5FP16Operand";
996 }
997
983998 // addrmode6 := reg with optional alignment
984999 //
9851000 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
2929 let ParserMethod = "parseFPImm";
3030 }
3131
32 def vfp_f16imm : Operand,
33 PatLeaf<(f16 fpimm), [{
34 return ARM_AM::getFP16Imm(N->getValueAPF()) != -1;
35 }], SDNodeXForm
36 APFloat InVal = N->getValueAPF();
37 uint32_t enc = ARM_AM::getFP16Imm(InVal);
38 return CurDAG->getTargetConstant(enc, MVT::i32);
39 }]>> {
40 let PrintMethod = "printFPImmOperand";
41 let ParserMatchClass = FPImmOperand;
42 }
43
3244 def vfp_f32imm : Operand,
3345 PatLeaf<(f32 fpimm), [{
3446 return ARM_AM::getFP32Imm(N->getValueAPF()) != -1;
97109 let D = VFPNeonDomain;
98110 }
99111
112 def VLDRH : AHI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5fp16:$addr),
113 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr",
114 []>,
115 Requires<[HasFullFP16]>;
116
100117 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
101118
102119 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
110127 // pipelines.
111128 let D = VFPNeonDomain;
112129 }
130
131 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5fp16:$addr),
132 IIC_fpStore16, "vstr", ".16\t$Sd, $addr",
133 []>,
134 Requires<[HasFullFP16]>;
113135
114136 //===----------------------------------------------------------------------===//
115137 // Load / store multiple Instructions.
294316 let D = VFPNeonA8Domain;
295317 }
296318
319 let TwoOperandAliasConstraint = "$Sn = $Sd" in
320 def VADDH : AHbI<0b11100, 0b11, 0, 0,
321 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
322 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",
323 []>;
324
297325 let TwoOperandAliasConstraint = "$Dn = $Dd" in
298326 def VSUBD : ADbI<0b11100, 0b11, 1, 0,
299327 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
310338 let D = VFPNeonA8Domain;
311339 }
312340
341 let TwoOperandAliasConstraint = "$Sn = $Sd" in
342 def VSUBH : AHbI<0b11100, 0b11, 1, 0,
343 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
344 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
345 []>;
346
313347 let TwoOperandAliasConstraint = "$Dn = $Dd" in
314348 def VDIVD : ADbI<0b11101, 0b00, 0, 0,
315349 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
322356 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
323357 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
324358
359 let TwoOperandAliasConstraint = "$Sn = $Sd" in
360 def VDIVH : AHbI<0b11101, 0b00, 0, 0,
361 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
362 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",
363 []>;
364
325365 let TwoOperandAliasConstraint = "$Dn = $Dd" in
326366 def VMULD : ADbI<0b11100, 0b10, 0, 0,
327367 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
338378 let D = VFPNeonA8Domain;
339379 }
340380
381 let TwoOperandAliasConstraint = "$Sn = $Sd" in
382 def VMULH : AHbI<0b11100, 0b10, 0, 0,
383 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
384 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",
385 []>;
386
341387 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
342388 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
343389 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
352398 let D = VFPNeonA8Domain;
353399 }
354400
401 def VNMULH : AHbI<0b11100, 0b10, 1, 0,
402 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
403 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",
404 []>;
405
355406 multiclass vsel_inst opc, int CC> {
356407 let DecoderNamespace = "VFPV8", PostEncoderMethod = "",
357408 Uses = [CPSR], AddedComplexity = 4 in {
409 def H : AHbInp<0b11100, opc, 0,
410 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
411 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
412 []>,
413 Requires<[HasFullFP16]>;
414
358415 def S : ASbInp<0b11100, opc, 0,
359416 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
360417 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
377434
378435 multiclass vmaxmin_inst {
379436 let DecoderNamespace = "VFPV8", PostEncoderMethod = "" in {
437 def H : AHbInp<0b11101, 0b00, opc,
438 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
439 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),
440 []>,
441 Requires<[HasFullFP16]>;
442
380443 def S : ASbInp<0b11101, 0b00, opc,
381444 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
382445 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
417480 let D = VFPNeonA8Domain;
418481 }
419482
483 def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0,
484 (outs), (ins SPR:$Sd, SPR:$Sm),
485 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
486 []>;
487
488
420489 // FIXME: Verify encoding after integrated assembler is working.
421490 def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
422491 (outs), (ins DPR:$Dd, DPR:$Dm),
431500 // VFP pipelines on A8.
432501 let D = VFPNeonA8Domain;
433502 }
503
504 def VCMPH : AHuI<0b11101, 0b11, 0b0100, 0b01, 0,
505 (outs), (ins SPR:$Sd, SPR:$Sm),
506 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",
507 []>;
434508 } // Defs = [FPSCR_NZCV]
435509
436510 //===----------------------------------------------------------------------===//
450524 // VFP pipelines on A8.
451525 let D = VFPNeonA8Domain;
452526 }
527
528 def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0,
529 (outs SPR:$Sd), (ins SPR:$Sm),
530 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm",
531 []>;
453532
454533 let Defs = [FPSCR_NZCV] in {
455534 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
472551 let D = VFPNeonA8Domain;
473552 }
474553
554 def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,
555 (outs), (ins SPR:$Sd),
556 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",
557 []> {
558 let Inst{3-0} = 0b0000;
559 let Inst{5} = 0;
560 }
561
475562 // FIXME: Verify encoding after integrated assembler is working.
476563 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
477564 (outs), (ins DPR:$Dd),
492579 // VFP pipelines on A8.
493580 let D = VFPNeonA8Domain;
494581 }
582
583 def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,
584 (outs), (ins SPR:$Sd),
585 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",
586 []> {
587 let Inst{3-0} = 0b0000;
588 let Inst{5} = 0;
589 }
495590 } // Defs = [FPSCR_NZCV]
496591
497592 def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
626721 multiclass vcvt_inst rm,
627722 SDPatternOperator node = null_frag> {
628723 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
724 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,
725 (outs SPR:$Sd), (ins SPR:$Sm),
726 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),
727 []>,
728 Requires<[HasFullFP16]> {
729 let Inst{17-16} = rm;
730 }
731
732 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0,
733 (outs SPR:$Sd), (ins SPR:$Sm),
734 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"),
735 []>,
736 Requires<[HasFullFP16]> {
737 let Inst{17-16} = rm;
738 }
739
629740 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
630741 (outs SPR:$Sd), (ins SPR:$Sm),
631742 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
714825 let D = VFPNeonA8Domain;
715826 }
716827
828 def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
829 (outs SPR:$Sd), (ins SPR:$Sm),
830 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
831 []>;
832
717833 multiclass vrint_inst_zrx {
834 def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,
835 (outs SPR:$Sd), (ins SPR:$Sm),
836 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
837 []>,
838 Requires<[HasFullFP16]> {
839 let Inst{7} = op2;
840 let Inst{16} = op;
841 }
842
718843 def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
719844 (outs SPR:$Sd), (ins SPR:$Sm),
720845 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
732857 let Inst{16} = op;
733858 }
734859
860 def : InstAlias
861 (!cast(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p)>,
862 Requires<[HasFullFP16]>;
735863 def : InstAlias
736864 (!cast(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p)>,
737865 Requires<[HasFPARMv8]>;
747875 multiclass vrint_inst_anpm rm,
748876 SDPatternOperator node = null_frag> {
749877 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
878 def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0,
879 (outs SPR:$Sd), (ins SPR:$Sm),
880 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
881 []>,
882 Requires<[HasFullFP16]> {
883 let Inst{17-16} = rm;
884 }
750885 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
751886 (outs SPR:$Sd), (ins SPR:$Sm),
752887 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
786921 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
787922 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
788923
924 def VSQRTH : AHuI<0b11101, 0b11, 0b0001, 0b11, 0,
925 (outs SPR:$Sd), (ins SPR:$Sm),
926 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",
927 []>;
928
789929 let hasSideEffects = 0 in {
790930 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
791931 (outs DPR:$Dd), (ins DPR:$Dm),
794934 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
795935 (outs SPR:$Sd), (ins SPR:$Sm),
796936 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
937
938 let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
939 def VMOVH : ASuInp<0b11101, 0b11, 0b0000, 0b01, 0,
940 (outs SPR:$Sd), (ins SPR:$Sm),
941 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,
942 Requires<[HasFullFP16]>;
943
944 def VINSH : ASuInp<0b11101, 0b11, 0b0000, 0b11, 0,
945 (outs SPR:$Sd), (ins SPR:$Sm),
946 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,
947 Requires<[HasFullFP16]>;
948 } // PostEncoderMethod
797949 } // hasSideEffects
798950
799951 //===----------------------------------------------------------------------===//
9651117 let DecoderMethod = "DecodeVMOVSRR";
9661118 }
9671119
1120 // Move H->R, clearing top 16 bits
1121 def VMOVRH : AVConv2I<0b11100001, 0b1001,
1122 (outs GPR:$Rt), (ins SPR:$Sn),
1123 IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn",
1124 []>,
1125 Requires<[HasFullFP16]> {
1126 // Instruction operands.
1127 bits<4> Rt;
1128 bits<5> Sn;
1129
1130 // Encode instruction operands.
1131 let Inst{19-16} = Sn{4-1};
1132 let Inst{7} = Sn{0};
1133 let Inst{15-12} = Rt;
1134
1135 let Inst{6-5} = 0b00;
1136 let Inst{3-0} = 0b0000;
1137 }
1138
1139 // Move R->H, clearing top 16 bits
1140 def VMOVHR : AVConv4I<0b11100000, 0b1001,
1141 (outs SPR:$Sn), (ins GPR:$Rt),
1142 IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt",
1143 []>,
1144 Requires<[HasFullFP16]> {
1145 // Instruction operands.
1146 bits<5> Sn;
1147 bits<4> Rt;
1148
1149 // Encode instruction operands.
1150 let Inst{19-16} = Sn{4-1};
1151 let Inst{7} = Sn{0};
1152 let Inst{15-12} = Rt;
1153
1154 let Inst{6-5} = 0b00;
1155 let Inst{3-0} = 0b0000;
1156 }
1157
9681158 // FMRDH: SPR -> GPR
9691159 // FMRDL: SPR -> GPR
9701160 // FMRRS: SPR -> GPR
10101200 let Inst{22} = Sd{0};
10111201 }
10121202
1203 class AVConv1IHs_Encode opcod1, bits<2> opcod2, bits<4> opcod3,
1204 bits<4> opcod4, dag oops, dag iops,
1205 InstrItinClass itin, string opc, string asm,
1206 list pattern>
1207 : AVConv1I
1208 pattern> {
1209 // Instruction operands.
1210 bits<5> Sd;
1211 bits<5> Sm;
1212
1213 // Encode instruction operands.
1214 let Inst{3-0} = Sm{4-1};
1215 let Inst{5} = Sm{0};
1216 let Inst{15-12} = Sd{4-1};
1217 let Inst{22} = Sd{0};
1218
1219 let Predicates = [HasFullFP16];
1220 }
1221
10131222 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
10141223 (outs DPR:$Dd), (ins SPR:$Sm),
10151224 IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
10421251 def : VFPNoNEONPat<(f32 (sint_to_fp (i32 (alignedload32 addrmode5:$a)))),
10431252 (VSITOS (VLDRS addrmode5:$a))>;
10441253
1254 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1255 (outs SPR:$Sd), (ins SPR:$Sm),
1256 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm",
1257 []> {
1258 let Inst{7} = 1; // s32
1259 }
1260
10451261 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
10461262 (outs DPR:$Dd), (ins SPR:$Sm),
10471263 IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
10731289
10741290 def : VFPNoNEONPat<(f32 (uint_to_fp (i32 (alignedload32 addrmode5:$a)))),
10751291 (VUITOS (VLDRS addrmode5:$a))>;
1292
1293 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1294 (outs SPR:$Sd), (ins SPR:$Sm),
1295 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm",
1296 []> {
1297 let Inst{7} = 0; // u32
1298 }
10761299
10771300 // FP -> Int:
10781301
11121335 let Inst{22} = Sd{0};
11131336 }
11141337
1338 class AVConv1IsH_Encode opcod1, bits<2> opcod2, bits<4> opcod3,
1339 bits<4> opcod4, dag oops, dag iops,
1340 InstrItinClass itin, string opc, string asm,
1341 list pattern>
1342 : AVConv1I
1343 pattern> {
1344 // Instruction operands.
1345 bits<5> Sd;
1346 bits<5> Sm;
1347
1348 // Encode instruction operands.
1349 let Inst{3-0} = Sm{4-1};
1350 let Inst{5} = Sm{0};
1351 let Inst{15-12} = Sd{4-1};
1352 let Inst{22} = Sd{0};
1353
1354 let Predicates = [HasFullFP16];
1355 }
1356
11151357 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
11161358 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
11171359 (outs SPR:$Sd), (ins DPR:$Dm),
11461388 addrmode5:$ptr),
11471389 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
11481390
1391 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1392 (outs SPR:$Sd), (ins SPR:$Sm),
1393 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
1394 []> {
1395 let Inst{7} = 1; // Z bit
1396 }
1397
11491398 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
11501399 (outs SPR:$Sd), (ins DPR:$Dm),
11511400 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
11781427 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
11791428 addrmode5:$ptr),
11801429 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1430
1431 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1432 (outs SPR:$Sd), (ins SPR:$Sm),
1433 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",
1434 []> {
1435 let Inst{7} = 1; // Z bit
1436 }
11811437
11821438 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
11831439 let Uses = [FPSCR] in {
11961452 let Inst{7} = 0; // Z bit
11971453 }
11981454
1455 def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1456 (outs SPR:$Sd), (ins SPR:$Sm),
1457 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",
1458 []> {
1459 let Inst{7} = 0; // Z bit
1460 }
1461
11991462 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
12001463 (outs SPR:$Sd), (ins DPR:$Dm),
12011464 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
12071470 (outs SPR:$Sd), (ins SPR:$Sm),
12081471 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
12091472 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
1473 let Inst{7} = 0; // Z bit
1474 }
1475
1476 def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1477 (outs SPR:$Sd), (ins SPR:$Sm),
1478 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",
1479 []> {
12101480 let Inst{7} = 0; // Z bit
12111481 }
12121482 }
12481518 let Predicates = [HasVFP2, HasDPVFP];
12491519 }
12501520
1521 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,
1522 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1523 IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>,
1524 Requires<[HasFullFP16]>;
1525
1526 def VTOUHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 0,
1527 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1528 IIC_fpCVTHI, "vcvt", ".u16.f16\t$dst, $a, $fbits", []>,
1529 Requires<[HasFullFP16]>;
1530
1531 def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1,
1532 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1533 IIC_fpCVTHI, "vcvt", ".s32.f16\t$dst, $a, $fbits", []>,
1534 Requires<[HasFullFP16]>;
1535
1536 def VTOULH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 1,
1537 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1538 IIC_fpCVTHI, "vcvt", ".u32.f16\t$dst, $a, $fbits", []>,
1539 Requires<[HasFullFP16]>;
1540
12511541 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0,
12521542 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
12531543 IIC_fpCVTSI, "vcvt", ".s16.f32\t$dst, $a, $fbits", []> {
12971587 IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a, $fbits", []>;
12981588
12991589 // Fixed-Point to FP:
1590
1591 def VSHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 0,
1592 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1593 IIC_fpCVTIH, "vcvt", ".f16.s16\t$dst, $a, $fbits", []>,
1594 Requires<[HasFullFP16]>;
1595
1596 def VUHTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 0,
1597 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1598 IIC_fpCVTIH, "vcvt", ".f16.u16\t$dst, $a, $fbits", []>,
1599 Requires<[HasFullFP16]>;
1600
1601 def VSLTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1001, 1,
1602 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1603 IIC_fpCVTIH, "vcvt", ".f16.s32\t$dst, $a, $fbits", []>,
1604 Requires<[HasFullFP16]>;
1605
1606 def VULTOH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1011, 0b1001, 1,
1607 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1608 IIC_fpCVTIH, "vcvt", ".f16.u32\t$dst, $a, $fbits", []>,
1609 Requires<[HasFullFP16]>;
13001610
13011611 def VSHTOS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1010, 0b1010, 0,
13021612 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
13721682 let D = VFPNeonA8Domain;
13731683 }
13741684
1685 def VMLAH : AHbI<0b11100, 0b00, 0, 0,
1686 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1687 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm",
1688 []>,
1689 RegConstraint<"$Sdin = $Sd">,
1690 Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
1691
13751692 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
13761693 (VMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
13771694 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
13991716 let D = VFPNeonA8Domain;
14001717 }
14011718
1719 def VMLSH : AHbI<0b11100, 0b00, 1, 0,
1720 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1721 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm",
1722 []>,
1723 RegConstraint<"$Sdin = $Sd">,
1724 Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
1725
14021726 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
14031727 (VMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
14041728 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
14261750 let D = VFPNeonA8Domain;
14271751 }
14281752
1753 def VNMLAH : AHbI<0b11100, 0b01, 1, 0,
1754 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1755 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm",
1756 []>,
1757 RegConstraint<"$Sdin = $Sd">,
1758 Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
1759
14291760 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
14301761 (VNMLAD DPR:$dstin, DPR:$a, DPR:$b)>,
14311762 Requires<[HasVFP2,HasDPVFP,UseFPVMLx,DontUseFusedMAC]>;
14511782 // VFP pipelines on A8.
14521783 let D = VFPNeonA8Domain;
14531784 }
1785
1786 def VNMLSH : AHbI<0b11100, 0b01, 0, 0,
1787 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1788 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm",
1789 []>,
1790 RegConstraint<"$Sdin = $Sd">,
1791 Requires<[HasFullFP16,UseFPVMLx,DontUseFusedMAC]>;
14541792
14551793 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
14561794 (VNMLSD DPR:$dstin, DPR:$a, DPR:$b)>,
14811819 // VFP pipelines.
14821820 }
14831821
1822 def VFMAH : AHbI<0b11101, 0b10, 0, 0,
1823 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1824 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm",
1825 []>,
1826 RegConstraint<"$Sdin = $Sd">,
1827 Requires<[HasFullFP16,UseFusedMAC]>;
1828
14841829 def : Pat<(fadd_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
14851830 (VFMAD DPR:$dstin, DPR:$a, DPR:$b)>,
14861831 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
15151860 // Some single precision VFP instructions may be executed on both NEON and
15161861 // VFP pipelines.
15171862 }
1863
1864 def VFMSH : AHbI<0b11101, 0b10, 1, 0,
1865 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1866 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",
1867 []>,
1868 RegConstraint<"$Sdin = $Sd">,
1869 Requires<[HasFullFP16,UseFusedMAC]>;
15181870
15191871 def : Pat<(fsub_mlx DPR:$dstin, (fmul_su DPR:$a, (f64 DPR:$b))),
15201872 (VFMSD DPR:$dstin, DPR:$a, DPR:$b)>,
15581910 // VFP pipelines.
15591911 }
15601912
1913 def VFNMAH : AHbI<0b11101, 0b01, 1, 0,
1914 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1915 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm",
1916 []>,
1917 RegConstraint<"$Sdin = $Sd">,
1918 Requires<[HasFullFP16,UseFusedMAC]>;
1919
15611920 def : Pat<(fsub_mlx (fneg (fmul_su DPR:$a, (f64 DPR:$b))), DPR:$dstin),
15621921 (VFNMAD DPR:$dstin, DPR:$a, DPR:$b)>,
15631922 Requires<[HasVFP4,HasDPVFP,UseFusedMAC]>;
15981957 // Some single precision VFP instructions may be executed on both NEON and
15991958 // VFP pipelines.
16001959 }
1960
1961 def VFNMSH : AHbI<0b11101, 0b01, 0, 0,
1962 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
1963 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",
1964 []>,
1965 RegConstraint<"$Sdin = $Sd">,
1966 Requires<[HasFullFP16,UseFusedMAC]>;
16011967
16021968 def : Pat<(fsub_mlx (fmul_su DPR:$a, (f64 DPR:$b)), DPR:$dstin),
16031969 (VFNMSD DPR:$dstin, DPR:$a, DPR:$b)>,
17762142 let Inst{15-12} = Sd{4-1};
17772143 let Inst{11-9} = 0b101;
17782144 let Inst{8} = 0; // Single precision.
2145 let Inst{7-4} = 0b0000;
2146 let Inst{3-0} = imm{3-0};
2147 }
2148
2149 def FCONSTH : VFPAI<(outs SPR:$Sd), (ins vfp_f16imm:$imm),
2150 VFPMiscFrm, IIC_fpUNA16,
2151 "vmov", ".f16\t$Sd, $imm",
2152 []>, Requires<[HasFullFP16]> {
2153 bits<5> Sd;
2154 bits<8> imm;
2155
2156 let Inst{27-23} = 0b11101;
2157 let Inst{22} = Sd{0};
2158 let Inst{21-20} = 0b11;
2159 let Inst{19-16} = imm{7-4};
2160 let Inst{15-12} = Sd{4-1};
2161 let Inst{11-8} = 0b1001; // Half precision
17792162 let Inst{7-4} = 0b0000;
17802163 let Inst{3-0} = imm{3-0};
17812164 }
185185 def IIC_Preload : InstrItinClass;
186186 def IIC_Br : InstrItinClass;
187187 def IIC_fpSTAT : InstrItinClass;
188 def IIC_fpUNA16 : InstrItinClass;
188189 def IIC_fpUNA32 : InstrItinClass;
189190 def IIC_fpUNA64 : InstrItinClass;
191 def IIC_fpCMP16 : InstrItinClass;
190192 def IIC_fpCMP32 : InstrItinClass;
191193 def IIC_fpCMP64 : InstrItinClass;
192194 def IIC_fpCVTSD : InstrItinClass;
193195 def IIC_fpCVTDS : InstrItinClass;
194196 def IIC_fpCVTSH : InstrItinClass;
195197 def IIC_fpCVTHS : InstrItinClass;
198 def IIC_fpCVTIH : InstrItinClass;
196199 def IIC_fpCVTIS : InstrItinClass;
197200 def IIC_fpCVTID : InstrItinClass;
201 def IIC_fpCVTHI : InstrItinClass;
198202 def IIC_fpCVTSI : InstrItinClass;
199203 def IIC_fpCVTDI : InstrItinClass;
200204 def IIC_fpMOVIS : InstrItinClass;
201205 def IIC_fpMOVID : InstrItinClass;
202206 def IIC_fpMOVSI : InstrItinClass;
203207 def IIC_fpMOVDI : InstrItinClass;
208 def IIC_fpALU16 : InstrItinClass;
204209 def IIC_fpALU32 : InstrItinClass;
205210 def IIC_fpALU64 : InstrItinClass;
211 def IIC_fpMUL16 : InstrItinClass;
206212 def IIC_fpMUL32 : InstrItinClass;
207213 def IIC_fpMUL64 : InstrItinClass;
214 def IIC_fpMAC16 : InstrItinClass;
208215 def IIC_fpMAC32 : InstrItinClass;
209216 def IIC_fpMAC64 : InstrItinClass;
217 def IIC_fpFMAC16 : InstrItinClass;
210218 def IIC_fpFMAC32 : InstrItinClass;
211219 def IIC_fpFMAC64 : InstrItinClass;
220 def IIC_fpDIV16 : InstrItinClass;
212221 def IIC_fpDIV32 : InstrItinClass;
213222 def IIC_fpDIV64 : InstrItinClass;
223 def IIC_fpSQRT16 : InstrItinClass;
214224 def IIC_fpSQRT32 : InstrItinClass;
215225 def IIC_fpSQRT64 : InstrItinClass;
226 def IIC_fpLoad16 : InstrItinClass;
216227 def IIC_fpLoad32 : InstrItinClass;
217228 def IIC_fpLoad64 : InstrItinClass;
218229 def IIC_fpLoad_m : InstrItinClass;
219230 def IIC_fpLoad_mu : InstrItinClass;
231 def IIC_fpStore16 : InstrItinClass;
220232 def IIC_fpStore32 : InstrItinClass;
221233 def IIC_fpStore64 : InstrItinClass;
222234 def IIC_fpStore_m : InstrItinClass;
11821182 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
11831183 Val == INT32_MIN;
11841184 }
1185 bool isAddrMode5FP16() const {
1186 // If we have an immediate that's not a constant, treat it as a label
1187 // reference needing a fixup. If it is a constant, it's something else
1188 // and we reject it.
1189 if (isImm() && !isa(getImm()))
1190 return true;
1191 if (!isMem() || Memory.Alignment != 0) return false;
1192 // Check for register offset.
1193 if (Memory.OffsetRegNum) return false;
1194 // Immediate offset in range [-510, 510] and a multiple of 2.
1195 if (!Memory.OffsetImm) return true;
1196 int64_t Val = Memory.OffsetImm->getValue();
1197 return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || Val == INT32_MIN;
1198 }
11851199 bool isMemTBB() const {
11861200 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
11871201 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
21402154 if (Val == INT32_MIN) Val = 0;
21412155 if (Val < 0) Val = -Val;
21422156 Val = ARM_AM::getAM5Opc(AddSub, Val);
2157 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2158 Inst.addOperand(MCOperand::createImm(Val));
2159 }
2160
2161 void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2162 assert(N == 2 && "Invalid number of operands!");
2163 // If we have an immediate that's not a constant, treat it as a label
2164 // reference needing a fixup. If it is a constant, it's something else
2165 // and we reject it.
2166 if (isImm()) {
2167 Inst.addOperand(MCOperand::createExpr(getImm()));
2168 Inst.addOperand(MCOperand::createImm(0));
2169 return;
2170 }
2171
2172 // The lower bit is always zero and as such is not encoded.
2173 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2174 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2175 // Special case for #-0
2176 if (Val == INT32_MIN) Val = 0;
2177 if (Val < 0) Val = -Val;
2178 Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
21432179 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
21442180 Inst.addOperand(MCOperand::createImm(Val));
21452181 }
49725008 // vmov.i{8|16|32|64} , #imm
49735009 ARMOperand &TyOp = static_cast(*Operands[2]);
49745010 bool isVmovf = TyOp.isToken() &&
4975 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
5011 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
5012 TyOp.getToken() == ".f16");
49765013 ARMOperand &Mnemonic = static_cast(*Operands[0]);
49775014 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
49785015 Mnemonic.getToken() == "fconsts");
52645301 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
52655302 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
52665303 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5267 Mnemonic.startswith("vsel"))
5304 Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx")
52685305 return Mnemonic;
52695306
52705307 // First, split out any predication code. Ignore mnemonics we know aren't
53685405 Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
53695406 Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
53705407 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5371 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5408 (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
5409 Mnemonic == "vmovx" || Mnemonic == "vins") {
53725410 // These mnemonics are never predicable
53735411 CanAcceptPredicationCode = false;
53745412 } else if (!isThumb()) {
220220 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
221221 uint64_t Address, const void *Decoder);
222222 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
223225 uint64_t Address, const void *Decoder);
224226 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
225227 uint64_t Address, const void *Decoder);
21822184 DecodeStatus S = MCDisassembler::Success;
21832185
21842186 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2187 // U == 1 to add imm, 0 to subtract it.
21852188 unsigned U = fieldFromInstruction(Val, 8, 1);
21862189 unsigned imm = fieldFromInstruction(Val, 0, 8);
21872190
21922195 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
21932196 else
21942197 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2198
2199 return S;
2200 }
2201
2202 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2203 uint64_t Address, const void *Decoder) {
2204 DecodeStatus S = MCDisassembler::Success;
2205
2206 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2207 // U == 1 to add imm, 0 to subtract it.
2208 unsigned U = fieldFromInstruction(Val, 8, 1);
2209 unsigned imm = fieldFromInstruction(Val, 0, 8);
2210
2211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2212 return MCDisassembler::Fail;
2213
2214 if (U)
2215 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2216 else
2217 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
21952218
21962219 return S;
21972220 }
643643 O << "]" << markup(">");
644644 }
645645
646 template
647 void ARMInstPrinter::printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,
648 const MCSubtargetInfo &STI,
649 raw_ostream &O) {
650 const MCOperand &MO1 = MI->getOperand(OpNum);
651 const MCOperand &MO2 = MI->getOperand(OpNum+1);
652
653 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
654 printOperand(MI, OpNum, STI, O);
655 return;
656 }
657
658 O << markup("
659 printRegName(O, MO1.getReg());
660
661 unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
662 unsigned Op = ARM_AM::getAM5FP16Op(MO2.getImm());
663 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
664 O << ", "
665 << markup("
666 << "#"
667 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5FP16Op(MO2.getImm()))
668 << ImmOffs * 2
669 << markup(">");
670 }
671 O << "]" << markup(">");
672 }
673
646674 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
647675 const MCSubtargetInfo &STI,
648676 raw_ostream &O) {
7373 template
7474 void printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
7575 const MCSubtargetInfo &STI, raw_ostream &O);
76 template
77 void printAddrMode5FP16Operand(const MCInst *MI, unsigned OpNum,
78 const MCSubtargetInfo &STI, raw_ostream &O);
7679 void printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
7780 const MCSubtargetInfo &STI, raw_ostream &O);
7881 void printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
485485 // addrmode5 := reg +/- imm8*4
486486 //
487487 // The first operand is always a Reg. The second operand encodes the
488 // operation in bit 8 and the immediate in bits 0-7.
488 // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
489489
490490 /// getAM5Opc - This function encodes the addrmode5 opc field.
491491 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
496496 return AM5Opc & 0xFF;
497497 }
498498 static inline AddrOpc getAM5Op(unsigned AM5Opc) {
499 return ((AM5Opc >> 8) & 1) ? sub : add;
500 }
501
502 //===--------------------------------------------------------------------===//
503 // Addressing Mode #5 FP16
504 //===--------------------------------------------------------------------===//
505 //
506 // This is used for coprocessor instructions, such as 16-bit FP load/stores.
507 //
508 // addrmode5fp16 := reg +/- imm8*2
509 //
510 // The first operand is always a Reg. The second operand encodes the
511 // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
512
513 /// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
514 static inline unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset) {
515 bool isSub = Opc == sub;
516 return ((int)isSub << 8) | Offset;
517 }
518 static inline unsigned char getAM5FP16Offset(unsigned AM5Opc) {
519 return AM5Opc & 0xFF;
520 }
521 static inline AddrOpc getAM5FP16Op(unsigned AM5Opc) {
499522 return ((AM5Opc >> 8) & 1) ? sub : add;
500523 }
501524
649672 return FPUnion.F;
650673 }
651674
675 /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit
676 /// floating-point value. If the value cannot be represented as an 8-bit
677 /// floating-point value, then return -1.
678 static inline int getFP16Imm(const APInt &Imm) {
679 uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;
680 int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15
681 int64_t Mantissa = Imm.getZExtValue() & 0x3ff; // 10 bits
682
683 // We can handle 4 bits of mantissa.
684 // mantissa = (16+UInt(e:f:g:h))/16.
685 if (Mantissa & 0x3f)
686 return -1;
687 Mantissa >>= 6;
688
689 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
690 if (Exp < -3 || Exp > 4)
691 return -1;
692 Exp = ((Exp+3) & 0x7) ^ 4;
693
694 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
695 }
696
697 static inline int getFP16Imm(const APFloat &FPImm) {
698 return getFP16Imm(FPImm.bitcastToAPInt());
699 }
700
652701 /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
653702 /// floating-point value. If the value cannot be represented as an 8-bit
654703 /// floating-point value, then return -1.
5959 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
6060 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
6161 {"fixup_t2_pcrel_10", 0, 32,
62 MCFixupKindInfo::FKF_IsPCRel |
63 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
64 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
65 {"fixup_t2_pcrel_9", 0, 32,
6266 MCFixupKindInfo::FKF_IsPCRel |
6367 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
6468 {"fixup_thumb_adr_pcrel_10", 0, 8,
104108 {"fixup_t2_pcrel_10", 0, 32,
105109 MCFixupKindInfo::FKF_IsPCRel |
106110 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
111 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
112 {"fixup_t2_pcrel_9", 0, 32,
113 MCFixupKindInfo::FKF_IsPCRel |
114 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
107115 {"fixup_thumb_adr_pcrel_10", 8, 8,
108116 MCFixupKindInfo::FKF_IsPCRel |
109117 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
623631
624632 return Value;
625633 }
634 case ARM::fixup_arm_pcrel_9:
635 Value = Value - 4; // ARM fixups offset by an additional word and don't
636 // need to adjust for the half-word ordering.
637 // Fall through.
638 case ARM::fixup_t2_pcrel_9: {
639 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
640 Value = Value - 4;
641 bool isAdd = true;
642 if ((int64_t)Value < 0) {
643 Value = -Value;
644 isAdd = false;
645 }
646 // These values don't encode the low bit since it's always zero.
647 if (Ctx && (Value & 1)) {
648 Ctx->reportError(Fixup.getLoc(), "invalid value for this fixup");
649 return 0;
650 }
651 Value >>= 1;
652 if (Ctx && Value >= 256) {
653 Ctx->reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
654 return 0;
655 }
656 Value |= isAdd << 23;
657
658 // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
659 // swapped.
660 if (Kind == ARM::fixup_t2_pcrel_9)
661 return swapHalfWords(Value, IsLittleEndian);
662
663 return Value;
664 }
626665 }
627666 }
628667
694733 case ARM::fixup_arm_pcrel_10_unscaled:
695734 case ARM::fixup_arm_ldst_pcrel_12:
696735 case ARM::fixup_arm_pcrel_10:
736 case ARM::fixup_arm_pcrel_9:
697737 case ARM::fixup_arm_adr_pcrel_12:
698738 case ARM::fixup_arm_uncondbl:
699739 case ARM::fixup_arm_condbl:
707747 case ARM::fixup_t2_condbranch:
708748 case ARM::fixup_t2_uncondbranch:
709749 case ARM::fixup_t2_pcrel_10:
750 case ARM::fixup_t2_pcrel_9:
710751 case ARM::fixup_t2_adr_pcrel_12:
711752 case ARM::fixup_arm_thumb_bl:
712753 case ARM::fixup_arm_thumb_blx:
3232 // fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
3333 // the short-swapped encoding of Thumb2 instructions.
3434 fixup_t2_pcrel_10,
35 // fixup_arm_pcrel_9 - 9-bit PC relative relocation for symbol addresses
36 // used in VFP instructions where bit 0 not encoded (so it's encoded as an
37 // 8-bit immediate).
38 fixup_arm_pcrel_9,
39 // fixup_t2_pcrel_9 - Equivalent to fixup_arm_pcrel_9, accounting for
40 // the short-swapped encoding of Thumb2 instructions.
41 fixup_t2_pcrel_9,
3542 // fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
3643 // addresses where the lower 2 bits are not encoded (so it's encoded as an
3744 // 8-bit immediate).
254254 SmallVectorImpl &Fixups,
255255 const MCSubtargetInfo &STI) const;
256256
257 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
257 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
258258 uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
259 SmallVectorImpl &Fixups,
260 const MCSubtargetInfo &STI) const;
261
262 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
263 uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
259264 SmallVectorImpl &Fixups,
260265 const MCSubtargetInfo &STI) const;
261266
12511256 return (MO.getImm() >> 2);
12521257 }
12531258
1254 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
1259 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
12551260 uint32_t ARMMCCodeEmitter::
12561261 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
12571262 SmallVectorImpl &Fixups,
12751280 Kind = MCFixupKind(ARM::fixup_t2_pcrel_10);
12761281 else
12771282 Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
1283 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1284
1285 ++MCNumCPRelocations;
1286 } else {
1287 EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1288 isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1289 }
1290
1291 uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1292 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1293 if (isAdd)
1294 Binary |= (1 << 8);
1295 Binary |= (Reg << 9);
1296 return Binary;
1297 }
1298
1299 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1300 uint32_t ARMMCCodeEmitter::
1301 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1302 SmallVectorImpl &Fixups,
1303 const MCSubtargetInfo &STI) const {
1304 // {12-9} = reg
1305 // {8} = (U)nsigned (add == '1', sub == '0')
1306 // {7-0} = imm8
1307 unsigned Reg, Imm8;
1308 bool isAdd;
1309 // If The first operand isn't a register, we have a label reference.
1310 const MCOperand &MO = MI.getOperand(OpIdx);
1311 if (!MO.isReg()) {
1312 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1313 Imm8 = 0;
1314 isAdd = false; // 'U' bit is handled as part of the fixup.
1315
1316 assert(MO.isExpr() && "Unexpected machine operand type!");
1317 const MCExpr *Expr = MO.getExpr();
1318 MCFixupKind Kind;
1319 if (isThumb2(STI))
1320 Kind = MCFixupKind(ARM::fixup_t2_pcrel_9);
1321 else
1322 Kind = MCFixupKind(ARM::fixup_arm_pcrel_9);
12781323 Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
12791324
12801325 ++MCNumCPRelocations;
0 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16 -show-encoding < %s 2>&1 | FileCheck %s
1 @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+thumb-mode -show-encoding < %s 2>&1 | FileCheck %s
2
3 vadd.f16 s0, s1, s0
4 @ CHECK: error: instruction requires:
5
6 vsub.f16 s0, s1, s0
7 @ CHECK: error: instruction requires:
8
9 vdiv.f16 s0, s1, s0
10 @ CHECK: error: instruction requires:
11
12 vmul.f16 s0, s1, s0
13 @ CHECK: error: instruction requires:
14
15 vnmul.f16 s0, s1, s0
16 @ CHECK: error: instruction requires:
17
18 vmla.f16 s1, s2, s0
19 @ CHECK: error: instruction requires:
20
21 vmls.f16 s1, s2, s0
22 @ CHECK: error: instruction requires:
23
24 vnmla.f16 s1, s2, s0
25 @ CHECK: error: instruction requires:
26
27 vnmls.f16 s1, s2, s0
28 @ CHECK: error: instruction requires:
29
30 vcmp.f16 s0, s1
31 @ CHECK: error: instruction requires:
32
33 vcmp.f16 s2, #0
34 @ CHECK: error: instruction requires:
35
36 vcmpe.f16 s1, s0
37 @ CHECK: error: instruction requires:
38
39 vcmpe.f16 s0, #0
40 @ CHECK: error: instruction requires:
41
42 vabs.f16 s0, s0
43 @ CHECK: error: instruction requires:
44
45 vneg.f16 s0, s0
46 @ CHECK: error: instruction requires:
47
48 vsqrt.f16 s0, s0
49 @ CHECK: error: instruction requires:
50
51 vcvt.f16.s32 s0, s0
52 vcvt.f16.u32 s0, s0
53 vcvt.s32.f16 s0, s0
54 vcvt.u32.f16 s0, s0
55 @ CHECK: error: instruction requires:
56 @ CHECK: error: instruction requires:
57 @ CHECK: error: instruction requires:
58 @ CHECK: error: instruction requires:
59
60 vcvtr.s32.f16 s0, s1
61 vcvtr.u32.f16 s0, s1
62 @ CHECK: error: instruction requires:
63 @ CHECK: error: instruction requires:
64
65 vcvt.f16.u32 s0, s0, #20
66 vcvt.f16.u16 s0, s0, #1
67 vcvt.f16.s32 s1, s1, #20
68 vcvt.f16.s16 s17, s17, #1
69 vcvt.u32.f16 s12, s12, #20
70 vcvt.u16.f16 s28, s28, #1
71 vcvt.s32.f16 s1, s1, #20
72 vcvt.s16.f16 s17, s17, #1
73 @ CHECK: error: instruction requires:
74 @ CHECK: error: instruction requires:
75 @ CHECK: error: instruction requires:
76 @ CHECK: error: instruction requires:
77 @ CHECK: error: instruction requires:
78 @ CHECK: error: instruction requires:
79 @ CHECK: error: instruction requires:
80 @ CHECK: error: instruction requires:
81
82 vcvta.s32.f16 s2, s3
83 @ CHECK: error: instruction requires:
84
85 vcvtn.s32.f16 s6, s23
86 @ CHECK: error: instruction requires:
87
88 vcvtp.s32.f16 s0, s4
89 @ CHECK: error: instruction requires:
90
91 vcvtm.s32.f16 s17, s8
92 @ CHECK: error: instruction requires:
93
94 vcvta.u32.f16 s2, s3
95 @ CHECK: error: instruction requires:
96
97 vcvtn.u32.f16 s6, s23
98 @ CHECK: error: instruction requires:
99
100 vcvtp.u32.f16 s0, s4
101 @ CHECK: error: instruction requires:
102
103 vcvtm.u32.f16 s17, s8
104 @ CHECK: error: instruction requires:
105
106 vselge.f16 s4, s1, s23
107 @ CHECK: error: instruction requires:
108
109 vselgt.f16 s0, s1, s0
110 @ CHECK: error: instruction requires:
111
112 vseleq.f16 s30, s28, s23
113 @ CHECK: error: instruction requires:
114
115 vselvs.f16 s21, s16, s14
116 @ CHECK: error: instruction requires:
117
118 vmaxnm.f16 s5, s12, s0
119 @ CHECK: error: instruction requires:
120
121 vminnm.f16 s0, s0, s12
122 @ CHECK: error: instruction requires:
123
124 vrintz.f16 s3, s24
125 @ CHECK: error: instruction requires:
126
127 vrintr.f16 s0, s9
128 @ CHECK: error: instruction requires:
129
130 vrintx.f16 s10, s14
131 @ CHECK: error: instruction requires:
132
133 vrinta.f16 s12, s1
134 @ CHECK: error: instruction requires:
135
136 vrintn.f16 s12, s1
137 @ CHECK: error: instruction requires:
138
139 vrintp.f16 s12, s1
140 @ CHECK: error: instruction requires:
141
142 vrintm.f16 s12, s1
143 @ CHECK: error: instruction requires:
144
145 vfma.f16 s2, s7, s4
146 @ CHECK: error: instruction requires:
147
148 vfms.f16 s2, s7, s4
149 @ CHECK: error: instruction requires:
150
151 vfnma.f16 s2, s7, s4
152 @ CHECK: error: instruction requires:
153
154 vfnms.f16 s2, s7, s4
155 @ CHECK: error: instruction requires:
156
157 vmovx.f16 s2, s5
158 vins.f16 s2, s5
159 @ CHECK: error: instruction requires:
160 @ CHECK: error: instruction requires:
161
162
163 vldr.16 s1, [pc, #6]
164 vldr.16 s2, [pc, #510]
165 vldr.16 s3, [pc, #-510]
166 vldr.16 s4, [r4, #-18]
167 @ CHECK: error: instruction requires:
168 @ CHECK: error: instruction requires:
169 @ CHECK: error: instruction requires:
170 @ CHECK: error: instruction requires:
171
172
173 vstr.16 s1, [pc, #6]
174 vstr.16 s2, [pc, #510]
175 vstr.16 s3, [pc, #-510]
176 vstr.16 s4, [r4, #-18]
177 @ CHECK: error: instruction requires:
178 @ CHECK: error: instruction requires:
179 @ CHECK: error: instruction requires:
180 @ CHECK: error: instruction requires:
181
182 vmov.f16 s0, #1.0
183 @ CHECK: error: instruction requires:
184
185 vmov.f16 s1, r2
186 vmov.f16 r3, s4
187 @ CHECK: error: instruction requires:
188 @ CHECK: error: instruction requires:
0 @ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16 -show-encoding < %s | FileCheck %s --check-prefix=ARM
1 @ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+thumb-mode -show-encoding < %s | FileCheck %s --check-prefix=THUMB
2
3 vadd.f16 s0, s1, s0
4 @ ARM: vadd.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x30,0xee]
5 @ THUMB: vadd.f16 s0, s1, s0 @ encoding: [0x30,0xee,0x80,0x09]
6
7 vsub.f16 s0, s1, s0
8 @ ARM: vsub.f16 s0, s1, s0 @ encoding: [0xc0,0x09,0x30,0xee]
9 @ THUMB: vsub.f16 s0, s1, s0 @ encoding: [0x30,0xee,0xc0,0x09]
10
11 vdiv.f16 s0, s1, s0
12 @ ARM: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x80,0xee]
13 @ THUMB: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0xee,0x80,0x09]
14
15 vmul.f16 s0, s1, s0
16 @ ARM: vmul.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x20,0xee]
17 @ THUMB: vmul.f16 s0, s1, s0 @ encoding: [0x20,0xee,0x80,0x09]
18
19 vnmul.f16 s0, s1, s0
20 @ ARM: vnmul.f16 s0, s1, s0 @ encoding: [0xc0,0x09,0x20,0xee]
21 @ THUMB: vnmul.f16 s0, s1, s0 @ encoding: [0x20,0xee,0xc0,0x09]
22
23 vmla.f16 s1, s2, s0
24 @ ARM: vmla.f16 s1, s2, s0 @ encoding: [0x00,0x09,0x41,0xee]
25 @ THUMB: vmla.f16 s1, s2, s0 @ encoding: [0x41,0xee,0x00,0x09]
26
27 vmls.f16 s1, s2, s0
28 @ ARM: vmls.f16 s1, s2, s0 @ encoding: [0x40,0x09,0x41,0xee]
29 @ THUMB: vmls.f16 s1, s2, s0 @ encoding: [0x41,0xee,0x40,0x09]
30
31 vnmla.f16 s1, s2, s0
32 @ ARM: vnmla.f16 s1, s2, s0 @ encoding: [0x40,0x09,0x51,0xee]
33 @ THUMB: vnmla.f16 s1, s2, s0 @ encoding: [0x51,0xee,0x40,0x09]
34
35 vnmls.f16 s1, s2, s0
36 @ ARM: vnmls.f16 s1, s2, s0 @ encoding: [0x00,0x09,0x51,0xee]
37 @ THUMB: vnmls.f16 s1, s2, s0 @ encoding: [0x51,0xee,0x00,0x09]
38
39 vcmp.f16 s0, s1
40 @ ARM: vcmp.f16 s0, s1 @ encoding: [0x60,0x09,0xb4,0xee]
41 @ THUMB: vcmp.f16 s0, s1 @ encoding: [0xb4,0xee,0x60,0x09]
42
43 vcmp.f16 s2, #0
44 @ ARM: vcmp.f16 s2, #0 @ encoding: [0x40,0x19,0xb5,0xee]
45 @ THUMB: vcmp.f16 s2, #0 @ encoding: [0xb5,0xee,0x40,0x19]
46
47 vcmpe.f16 s1, s0
48 @ ARM: vcmpe.f16 s1, s0 @ encoding: [0xc0,0x09,0xf4,0xee]
49 @ THUMB: vcmpe.f16 s1, s0 @ encoding: [0xf4,0xee,0xc0,0x09]
50
51 vcmpe.f16 s0, #0
52 @ ARM: vcmpe.f16 s0, #0 @ encoding: [0xc0,0x09,0xb5,0xee]
53 @ THUMB: vcmpe.f16 s0, #0 @ encoding: [0xb5,0xee,0xc0,0x09]
54
55 vabs.f16 s0, s0
56 @ ARM: vabs.f16 s0, s0 @ encoding: [0xc0,0x09,0xb0,0xee]
57 @ THUMB: vabs.f16 s0, s0 @ encoding: [0xb0,0xee,0xc0,0x09]
58
59 vneg.f16 s0, s0
60 @ ARM: vneg.f16 s0, s0 @ encoding: [0x40,0x09,0xb1,0xee]
61 @ THUMB: vneg.f16 s0, s0 @ encoding: [0xb1,0xee,0x40,0x09]
62
63 vsqrt.f16 s0, s0
64 @ ARM: vsqrt.f16 s0, s0 @ encoding: [0xc0,0x09,0xb1,0xee]
65 @ THUMB: vsqrt.f16 s0, s0 @ encoding: [0xb1,0xee,0xc0,0x09]
66
67 vcvt.f16.s32 s0, s0
68 vcvt.f16.u32 s0, s0
69 vcvt.s32.f16 s0, s0
70 vcvt.u32.f16 s0, s0
71 @ ARM: vcvt.f16.s32 s0, s0 @ encoding: [0xc0,0x09,0xb8,0xee]
72 @ ARM: vcvt.f16.u32 s0, s0 @ encoding: [0x40,0x09,0xb8,0xee]
73 @ ARM: vcvt.s32.f16 s0, s0 @ encoding: [0xc0,0x09,0xbd,0xee]
74 @ ARM: vcvt.u32.f16 s0, s0 @ encoding: [0xc0,0x09,0xbc,0xee]
75 @ THUMB: vcvt.f16.s32 s0, s0 @ encoding: [0xb8,0xee,0xc0,0x09]
76 @ THUMB: vcvt.f16.u32 s0, s0 @ encoding: [0xb8,0xee,0x40,0x09]
77 @ THUMB: vcvt.s32.f16 s0, s0 @ encoding: [0xbd,0xee,0xc0,0x09]
78 @ THUMB: vcvt.u32.f16 s0, s0 @ encoding: [0xbc,0xee,0xc0,0x09]
79
80 vcvtr.s32.f16 s0, s1
81 vcvtr.u32.f16 s0, s1
82 @ ARM: vcvtr.s32.f16 s0, s1 @ encoding: [0x60,0x09,0xbd,0xee]
83 @ ARM: vcvtr.u32.f16 s0, s1 @ encoding: [0x60,0x09,0xbc,0xee]
84 @ THUMB: vcvtr.s32.f16 s0, s1 @ encoding: [0xbd,0xee,0x60,0x09]
85 @ THUMB: vcvtr.u32.f16 s0, s1 @ encoding: [0xbc,0xee,0x60,0x09]
86
87 vcvt.f16.u32 s0, s0, #20
88 vcvt.f16.u16 s0, s0, #1
89 vcvt.f16.s32 s1, s1, #20
90 vcvt.f16.s16 s17, s17, #1
91 vcvt.u32.f16 s12, s12, #20
92 vcvt.u16.f16 s28, s28, #1
93 vcvt.s32.f16 s1, s1, #20
94 vcvt.s16.f16 s17, s17, #1
95 @ ARM: vcvt.f16.u32 s0, s0, #20 @ encoding: [0xc6,0x09,0xbb,0xee]
96 @ ARM: vcvt.f16.u16 s0, s0, #1 @ encoding: [0x67,0x09,0xbb,0xee]
97 @ ARM: vcvt.f16.s32 s1, s1, #20 @ encoding: [0xc6,0x09,0xfa,0xee]
98 @ ARM: vcvt.f16.s16 s17, s17, #1 @ encoding: [0x67,0x89,0xfa,0xee]
99 @ ARM: vcvt.u32.f16 s12, s12, #20 @ encoding: [0xc6,0x69,0xbf,0xee]
100 @ ARM: vcvt.u16.f16 s28, s28, #1 @ encoding: [0x67,0xe9,0xbf,0xee]
101 @ ARM: vcvt.s32.f16 s1, s1, #20 @ encoding: [0xc6,0x09,0xfe,0xee]
102 @ ARM: vcvt.s16.f16 s17, s17, #1 @ encoding: [0x67,0x89,0xfe,0xee]
103 @ THUMB: vcvt.f16.u32 s0, s0, #20 @ encoding: [0xbb,0xee,0xc6,0x09]
104 @ THUMB: vcvt.f16.u16 s0, s0, #1 @ encoding: [0xbb,0xee,0x67,0x09]
105 @ THUMB: vcvt.f16.s32 s1, s1, #20 @ encoding: [0xfa,0xee,0xc6,0x09]
106 @ THUMB: vcvt.f16.s16 s17, s17, #1 @ encoding: [0xfa,0xee,0x67,0x89]
107 @ THUMB: vcvt.u32.f16 s12, s12, #20 @ encoding: [0xbf,0xee,0xc6,0x69]
108 @ THUMB: vcvt.u16.f16 s28, s28, #1 @ encoding: [0xbf,0xee,0x67,0xe9]
109 @ THUMB: vcvt.s32.f16 s1, s1, #20 @ encoding: [0xfe,0xee,0xc6,0x09]
110 @ THUMB: vcvt.s16.f16 s17, s17, #1 @ encoding: [0xfe,0xee,0x67,0x89]
111
112 vcvta.s32.f16 s2, s3
113 @ ARM: vcvta.s32.f16 s2, s3 @ encoding: [0xe1,0x19,0xbc,0xfe]
114 @ THUMB: vcvta.s32.f16 s2, s3 @ encoding: [0xbc,0xfe,0xe1,0x19]
115
116 vcvtn.s32.f16 s6, s23
117 @ ARM: vcvtn.s32.f16 s6, s23 @ encoding: [0xeb,0x39,0xbd,0xfe]
118 @ THUMB: vcvtn.s32.f16 s6, s23 @ encoding: [0xbd,0xfe,0xeb,0x39]
119
120 vcvtp.s32.f16 s0, s4
121 @ ARM: vcvtp.s32.f16 s0, s4 @ encoding: [0xc2,0x09,0xbe,0xfe]
122 @ THUMB: vcvtp.s32.f16 s0, s4 @ encoding: [0xbe,0xfe,0xc2,0x09]
123
124 vcvtm.s32.f16 s17, s8
125 @ ARM: vcvtm.s32.f16 s17, s8 @ encoding: [0xc4,0x89,0xff,0xfe]
126 @ THUMB: vcvtm.s32.f16 s17, s8 @ encoding: [0xff,0xfe,0xc4,0x89]
127
128 vcvta.u32.f16 s2, s3
129 @ ARM: vcvta.u32.f16 s2, s3 @ encoding: [0x61,0x19,0xbc,0xfe]
130 @ THUMB: vcvta.u32.f16 s2, s3 @ encoding: [0xbc,0xfe,0x61,0x19]
131
132 vcvtn.u32.f16 s6, s23
133 @ ARM: vcvtn.u32.f16 s6, s23 @ encoding: [0x6b,0x39,0xbd,0xfe]
134 @ THUMB: vcvtn.u32.f16 s6, s23 @ encoding: [0xbd,0xfe,0x6b,0x39]
135
136 vcvtp.u32.f16 s0, s4
137 @ ARM: vcvtp.u32.f16 s0, s4 @ encoding: [0x42,0x09,0xbe,0xfe]
138 @ THUMB: vcvtp.u32.f16 s0, s4 @ encoding: [0xbe,0xfe,0x42,0x09]
139
140 vcvtm.u32.f16 s17, s8
141 @ ARM: vcvtm.u32.f16 s17, s8 @ encoding: [0x44,0x89,0xff,0xfe]
142 @ THUMB: vcvtm.u32.f16 s17, s8 @ encoding: [0xff,0xfe,0x44,0x89]
143
144 vselge.f16 s4, s1, s23
145 @ ARM: vselge.f16 s4, s1, s23 @ encoding: [0xab,0x29,0x20,0xfe]
146 @ THUMB: vselge.f16 s4, s1, s23 @ encoding: [0x20,0xfe,0xab,0x29]
147
148 vselgt.f16 s0, s1, s0
149 @ ARM: vselgt.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x30,0xfe]
150 @ THUMB: vselgt.f16 s0, s1, s0 @ encoding: [0x30,0xfe,0x80,0x09]
151
152 vseleq.f16 s30, s28, s23
153 @ ARM: vseleq.f16 s30, s28, s23 @ encoding: [0x2b,0xf9,0x0e,0xfe]
154 @ THUMB: vseleq.f16 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xf9]
155
156 vselvs.f16 s21, s16, s14
157 @ ARM: vselvs.f16 s21, s16, s14 @ encoding: [0x07,0xa9,0x58,0xfe]
158 @ THUMB: vselvs.f16 s21, s16, s14 @ encoding: [0x58,0xfe,0x07,0xa9]
159
160 vmaxnm.f16 s5, s12, s0
161 @ ARM: vmaxnm.f16 s5, s12, s0 @ encoding: [0x00,0x29,0xc6,0xfe]
162 @ THUMB: vmaxnm.f16 s5, s12, s0 @ encoding: [0xc6,0xfe,0x00,0x29]
163
164 vminnm.f16 s0, s0, s12
165 @ ARM: vminnm.f16 s0, s0, s12 @ encoding: [0x46,0x09,0x80,0xfe]
166 @ THUMB: vminnm.f16 s0, s0, s12 @ encoding: [0x80,0xfe,0x46,0x09]
167
168 vrintz.f16 s3, s24
169 @ ARM: vrintz.f16 s3, s24 @ encoding: [0xcc,0x19,0xf6,0xee]
170 @ THUMB: vrintz.f16 s3, s24 @ encoding: [0xf6,0xee,0xcc,0x19]
171
172 vrintr.f16 s0, s9
173 @ ARM: vrintr.f16 s0, s9 @ encoding: [0x64,0x09,0xb6,0xee]
174 @ THUMB: vrintr.f16 s0, s9 @ encoding: [0xb6,0xee,0x64,0x09]
175
176 vrintx.f16 s10, s14
177 @ ARM: vrintx.f16 s10, s14 @ encoding: [0x47,0x59,0xb7,0xee]
178 @ THUMB: vrintx.f16 s10, s14 @ encoding: [0xb7,0xee,0x47,0x59]
179
180 vrinta.f16 s12, s1
181 @ ARM: vrinta.f16 s12, s1 @ encoding: [0x60,0x69,0xb8,0xfe]
182 @ THUMB: vrinta.f16 s12, s1 @ encoding: [0xb8,0xfe,0x60,0x69]
183
184 vrintn.f16 s12, s1
185 @ ARM: vrintn.f16 s12, s1 @ encoding: [0x60,0x69,0xb9,0xfe]
186 @ THUMB: vrintn.f16 s12, s1 @ encoding: [0xb9,0xfe,0x60,0x69]
187
188 vrintp.f16 s12, s1
189 @ ARM: vrintp.f16 s12, s1 @ encoding: [0x60,0x69,0xba,0xfe]
190 @ THUMB: vrintp.f16 s12, s1 @ encoding: [0xba,0xfe,0x60,0x69]
191
192 vrintm.f16 s12, s1
193 @ ARM: vrintm.f16 s12, s1 @ encoding: [0x60,0x69,0xbb,0xfe]
194 @ THUMB: vrintm.f16 s12, s1 @ encoding: [0xbb,0xfe,0x60,0x69]
195
196 vfma.f16 s2, s7, s4
197 @ ARM: vfma.f16 s2, s7, s4 @ encoding: [0x82,0x19,0xa3,0xee]
198 @ THUMB: vfma.f16 s2, s7, s4 @ encoding: [0xa3,0xee,0x82,0x19]
199
200 vfms.f16 s2, s7, s4
201 @ ARM: vfms.f16 s2, s7, s4 @ encoding: [0xc2,0x19,0xa3,0xee]
202 @ THUMB: vfms.f16 s2, s7, s4 @ encoding: [0xa3,0xee,0xc2,0x19]
203
204 vfnma.f16 s2, s7, s4
205 @ ARM: vfnma.f16 s2, s7, s4 @ encoding: [0xc2,0x19,0x93,0xee]
206 @ THUMB: vfnma.f16 s2, s7, s4 @ encoding: [0x93,0xee,0xc2,0x19]
207
208 vfnms.f16 s2, s7, s4
209 @ ARM: vfnms.f16 s2, s7, s4 @ encoding: [0x82,0x19,0x93,0xee]
210 @ THUMB: vfnms.f16 s2, s7, s4 @ encoding: [0x93,0xee,0x82,0x19]
211
212 vmovx.f16 s2, s5
213 vins.f16 s2, s5
214 @ ARM: vmovx.f16 s2, s5 @ encoding: [0x62,0x1a,0xb0,0xfe]
215 @ ARM: vins.f16 s2, s5 @ encoding: [0xe2,0x1a,0xb0,0xfe]
216 @ THUMB: vmovx.f16 s2, s5 @ encoding: [0xb0,0xfe,0x62,0x1a]
217 @ THUMB: vins.f16 s2, s5 @ encoding: [0xb0,0xfe,0xe2,0x1a]
218
219
220 vldr.16 s1, [pc, #6]
221 vldr.16 s2, [pc, #510]
222 vldr.16 s3, [pc, #-510]
223 vldr.16 s4, [r4, #-18]
224 @ ARM: vldr.16 s1, [pc, #6] @ encoding: [0x03,0x09,0xdf,0xed]
225 @ ARM: vldr.16 s2, [pc, #510] @ encoding: [0xff,0x19,0x9f,0xed]
226 @ ARM: vldr.16 s3, [pc, #-510] @ encoding: [0xff,0x19,0x5f,0xed]
227 @ ARM: vldr.16 s4, [r4, #-18] @ encoding: [0x09,0x29,0x14,0xed]
228 @ THUMB: vldr.16 s1, [pc, #6] @ encoding: [0xdf,0xed,0x03,0x09]
229 @ THUMB: vldr.16 s2, [pc, #510] @ encoding: [0x9f,0xed,0xff,0x19]
230 @ THUMB: vldr.16 s3, [pc, #-510] @ encoding: [0x5f,0xed,0xff,0x19]
231 @ THUMB: vldr.16 s4, [r4, #-18] @ encoding: [0x14,0xed,0x09,0x29]
232
233
234 vstr.16 s1, [pc, #6]
235 vstr.16 s2, [pc, #510]
236 vstr.16 s3, [pc, #-510]
237 vstr.16 s4, [r4, #-18]
238 @ ARM: vstr.16 s1, [pc, #6] @ encoding: [0x03,0x09,0xcf,0xed]
239 @ ARM: vstr.16 s2, [pc, #510] @ encoding: [0xff,0x19,0x8f,0xed]
240 @ ARM: vstr.16 s3, [pc, #-510] @ encoding: [0xff,0x19,0x4f,0xed]
241 @ ARM: vstr.16 s4, [r4, #-18] @ encoding: [0x09,0x29,0x04,0xed]
242 @ THUMB: vstr.16 s1, [pc, #6] @ encoding: [0xcf,0xed,0x03,0x09]
243 @ THUMB: vstr.16 s2, [pc, #510] @ encoding: [0x8f,0xed,0xff,0x19]
244 @ THUMB: vstr.16 s3, [pc, #-510] @ encoding: [0x4f,0xed,0xff,0x19]
245 @ THUMB: vstr.16 s4, [r4, #-18] @ encoding: [0x04,0xed,0x09,0x29]
246
247 vmov.f16 s0, #1.0
248 @ ARM: vmov.f16 s0, #1.000000e+00 @ encoding: [0x00,0x09,0xb7,0xee]
249 @ THUMB: vmov.f16 s0, #1.000000e+00 @ encoding: [0xb7,0xee,0x00,0x09]
250
251 vmov.f16 s1, r2
252 vmov.f16 r3, s4
253 @ ARM: vmov.f16 s1, r2 @ encoding: [0x90,0x29,0x00,0xee]
254 @ ARM: vmov.f16 r3, s4 @ encoding: [0x10,0x39,0x12,0xee]
255 @ THUMB: vmov.f16 s1, r2 @ encoding: [0x00,0xee,0x90,0x29]
256 @ THUMB: vmov.f16 r3, s4 @ encoding: [0x12,0xee,0x10,0x39]
0 # RUN: not llvm-mc -disassemble -triple armv8a-none-eabi -mattr=-fullfp16 -show-encoding < %s 2>&1 | FileCheck %s
1
2 # CHECK: warning: invalid instruction encoding
3 [0x80,0x09,0x30,0xee]
4
5 # CHECK: warning: invalid instruction encoding
6 [0xc0,0x09,0x30,0xee]
7
8 # CHECK: warning: invalid instruction encoding
9 [0x80,0x09,0x80,0xee]
10
11 # CHECK: warning: invalid instruction encoding
12 [0x80,0x09,0x20,0xee]
13
14 # CHECK: warning: invalid instruction encoding
15 [0xc0,0x09,0x20,0xee]
16
17 # CHECK: warning: invalid instruction encoding
18 [0x00,0x09,0x41,0xee]
19
20 # CHECK: warning: invalid instruction encoding
21 [0x40,0x09,0x41,0xee]
22
23 # CHECK: warning: invalid instruction encoding
24 [0x40,0x09,0x51,0xee]
25
26 # CHECK: warning: invalid instruction encoding
27 [0x00,0x09,0x51,0xee]
28
29 # CHECK: warning: invalid instruction encoding
30 [0x60,0x09,0xb4,0xee]
31
32 # CHECK: warning: invalid instruction encoding
33 [0x40,0x19,0xb5,0xee]
34
35 # CHECK: warning: invalid instruction encoding
36 [0xc0,0x09,0xf4,0xee]
37
38 # CHECK: warning: invalid instruction encoding
39 [0xc0,0x09,0xb5,0xee]
40
41 # CHECK: warning: invalid instruction encoding
42 [0xc0,0x09,0xb0,0xee]
43
44 # CHECK: warning: invalid instruction encoding
45 [0x40,0x09,0xb1,0xee]
46
47 # CHECK: warning: invalid instruction encoding
48 [0xc0,0x09,0xb1,0xee]
49
50 # CHECK: warning: invalid instruction encoding
51 # CHECK: warning: invalid instruction encoding
52 # CHECK: warning: invalid instruction encoding
53 # CHECK: warning: invalid instruction encoding
54 [0xc0,0x09,0xb8,0xee]
55 [0x40,0x09,0xb8,0xee]
56 [0xc0,0x09,0xbd,0xee]
57 [0xc0,0x09,0xbc,0xee]
58
59 # CHECK: warning: invalid instruction encoding
60 # CHECK: warning: invalid instruction encoding
61 [0x60,0x09,0xbd,0xee]
62 [0x60,0x09,0xbc,0xee]
63
64 # CHECK: warning: invalid instruction encoding
65 # CHECK: warning: invalid instruction encoding
66 # CHECK: warning: invalid instruction encoding
67 # CHECK: warning: invalid instruction encoding
68 # CHECK: warning: invalid instruction encoding
69 # CHECK: warning: invalid instruction encoding
70 # CHECK: warning: invalid instruction encoding
71 # CHECK: warning: invalid instruction encoding
72 [0xc6,0x09,0xbb,0xee]
73 [0x67,0x09,0xbb,0xee]
74 [0xc6,0x09,0xfa,0xee]
75 [0x67,0x89,0xfa,0xee]
76 [0xc6,0x69,0xbf,0xee]
77 [0x67,0xe9,0xbf,0xee]
78 [0xc6,0x09,0xfe,0xee]
79 [0x67,0x89,0xfe,0xee]
80
81 # CHECK: warning: invalid instruction encoding
82 [0xe1,0x19,0xbc,0xfe]
83
84 # CHECK: warning: invalid instruction encoding
85 [0xeb,0x39,0xbd,0xfe]
86
87 # CHECK: warning: invalid instruction encoding
88 [0xc2,0x09,0xbe,0xfe]
89
90 # CHECK: warning: invalid instruction encoding
91 [0xc4,0x89,0xff,0xfe]
92
93 # CHECK: warning: invalid instruction encoding
94 [0x61,0x19,0xbc,0xfe]
95
96 # CHECK: warning: invalid instruction encoding
97 [0x6b,0x39,0xbd,0xfe]
98
99 # CHECK: warning: invalid instruction encoding
100 [0x42,0x09,0xbe,0xfe]
101
102 # CHECK: warning: invalid instruction encoding
103 [0x44,0x89,0xff,0xfe]
104
105 # CHECK: warning: invalid instruction encoding
106 [0xab,0x29,0x20,0xfe]
107
108 # CHECK: warning: invalid instruction encoding
109 [0x80,0x09,0x30,0xfe]
110
111 # CHECK: warning: invalid instruction encoding
112 [0x2b,0xf9,0x0e,0xfe]
113
114 # CHECK: warning: invalid instruction encoding
115 [0x07,0xa9,0x58,0xfe]
116
117 # CHECK: warning: invalid instruction encoding
118 [0x00,0x29,0xc6,0xfe]
119
120 # CHECK: warning: invalid instruction encoding
121 [0x46,0x09,0x80,0xfe]
122
123 # CHECK: warning: invalid instruction encoding
124 [0xcc,0x19,0xf6,0xee]
125
126 # CHECK: warning: invalid instruction encoding
127 [0x64,0x09,0xb6,0xee]
128
129 # CHECK: warning: invalid instruction encoding
130 [0x47,0x59,0xb7,0xee]
131
132 # CHECK: warning: invalid instruction encoding
133 [0x60,0x69,0xb8,0xfe]
134
135 # CHECK: warning: invalid instruction encoding
136 [0x60,0x69,0xb9,0xfe]
137
138 # CHECK: warning: invalid instruction encoding
139 [0x60,0x69,0xba,0xfe]
140
141 # CHECK: warning: invalid instruction encoding
142 [0x60,0x69,0xbb,0xfe]
143
144 # CHECK: warning: invalid instruction encoding
145 [0x82,0x19,0xa3,0xee]
146
147 # CHECK: warning: invalid instruction encoding
148 [0xc2,0x19,0xa3,0xee]
149
150 # CHECK: warning: invalid instruction encoding
151 [0xc2,0x19,0x93,0xee]
152
153 # CHECK: warning: invalid instruction encoding
154 [0x82,0x19,0x93,0xee]
155
156 # CHECK: warning: invalid instruction encoding
157 # CHECK: warning: invalid instruction encoding
158 [0x62,0x1a,0xb0,0xfe]
159 [0xe2,0x1a,0xb0,0xfe]
160
161 # CHECK: warning: invalid instruction encoding
162 # CHECK: warning: invalid instruction encoding
163 # CHECK: warning: invalid instruction encoding
164 # CHECK: warning: invalid instruction encoding
165 [0x03,0x09,0xdf,0xed]
166 [0xff,0x19,0x9f,0xed]
167 [0xff,0x19,0x5f,0xed]
168 [0x09,0x29,0x14,0xed]
169
170 # CHECK: warning: invalid instruction encoding
171 # CHECK: warning: invalid instruction encoding
172 # CHECK: warning: invalid instruction encoding
173 # CHECK: warning: invalid instruction encoding
174 [0x03,0x09,0xcf,0xed]
175 [0xff,0x19,0x8f,0xed]
176 [0xff,0x19,0x4f,0xed]
177 [0x09,0x29,0x04,0xed]
178
179 # CHECK: warning: invalid instruction encoding
180 [0x00,0x09,0xb7,0xee]
181
182 # CHECK: warning: invalid instruction encoding
183 # CHECK: warning: invalid instruction encoding
184 [0x90,0x29,0x00,0xee]
185 [0x10,0x39,0x12,0xee]
186
187 # CHECK-NOT: warning: invalid instruction encoding
0 # RUN: llvm-mc -disassemble -triple armv8a-none-eabi -mattr=+fullfp16 -show-encoding < %s | FileCheck %s
1
2 # CHECK: vadd.f16 s0, s1, s0
3 [0x80,0x09,0x30,0xee]
4
5 # CHECK: vsub.f16 s0, s1, s0
6 [0xc0,0x09,0x30,0xee]
7
8 # CHECK: vdiv.f16 s0, s1, s0
9 [0x80,0x09,0x80,0xee]
10
11 # CHECK: vmul.f16 s0, s1, s0
12 [0x80,0x09,0x20,0xee]
13
14 # CHECK: vnmul.f16 s0, s1, s0
15 [0xc0,0x09,0x20,0xee]
16
17 # CHECK: vmla.f16 s1, s2, s0
18 [0x00,0x09,0x41,0xee]
19
20 # CHECK: vmls.f16 s1, s2, s0
21 [0x40,0x09,0x41,0xee]
22
23 # CHECK: vnmla.f16 s1, s2, s0
24 [0x40,0x09,0x51,0xee]
25
26 # CHECK: vnmls.f16 s1, s2, s0
27 [0x00,0x09,0x51,0xee]
28
29 # CHECK: vcmp.f16 s0, s1
30 [0x60,0x09,0xb4,0xee]
31
32 # CHECK: vcmp.f16 s2, #0
33 [0x40,0x19,0xb5,0xee]
34
35 # CHECK: vcmpe.f16 s1, s0
36 [0xc0,0x09,0xf4,0xee]
37
38 # CHECK: vcmpe.f16 s0, #0
39 [0xc0,0x09,0xb5,0xee]
40
41 # CHECK: vabs.f16 s0, s0
42 [0xc0,0x09,0xb0,0xee]
43
44 # CHECK: vneg.f16 s0, s0
45 [0x40,0x09,0xb1,0xee]
46
47 # CHECK: vsqrt.f16 s0, s0
48 [0xc0,0x09,0xb1,0xee]
49
50 # CHECK: vcvt.f16.s32 s0, s0
51 # CHECK: vcvt.f16.u32 s0, s0
52 # CHECK: vcvt.s32.f16 s0, s0
53 # CHECK: vcvt.u32.f16 s0, s0
54 [0xc0,0x09,0xb8,0xee]
55 [0x40,0x09,0xb8,0xee]
56 [0xc0,0x09,0xbd,0xee]
57 [0xc0,0x09,0xbc,0xee]
58
59 # CHECK: vcvtr.s32.f16 s0, s1
60 # CHECK: vcvtr.u32.f16 s0, s1
61 [0x60,0x09,0xbd,0xee]
62 [0x60,0x09,0xbc,0xee]
63
64 # CHECK: vcvt.f16.u32 s0, s0, #20
65 # CHECK: vcvt.f16.u16 s0, s0, #1
66 # CHECK: vcvt.f16.s32 s1, s1, #20
67 # CHECK: vcvt.f16.s16 s17, s17, #1
68 # CHECK: vcvt.u32.f16 s12, s12, #20
69 # CHECK: vcvt.u16.f16 s28, s28, #1
70 # CHECK: vcvt.s32.f16 s1, s1, #20
71 # CHECK: vcvt.s16.f16 s17, s17, #1
72 [0xc6,0x09,0xbb,0xee]
73 [0x67,0x09,0xbb,0xee]
74 [0xc6,0x09,0xfa,0xee]
75 [0x67,0x89,0xfa,0xee]
76 [0xc6,0x69,0xbf,0xee]
77 [0x67,0xe9,0xbf,0xee]
78 [0xc6,0x09,0xfe,0xee]
79 [0x67,0x89,0xfe,0xee]
80
81 # CHECK: vcvta.s32.f16 s2, s3
82 [0xe1,0x19,0xbc,0xfe]
83
84 # CHECK: vcvtn.s32.f16 s6, s23
85 [0xeb,0x39,0xbd,0xfe]
86
87 # CHECK: vcvtp.s32.f16 s0, s4
88 [0xc2,0x09,0xbe,0xfe]
89
90 # CHECK: vcvtm.s32.f16 s17, s8
91 [0xc4,0x89,0xff,0xfe]
92
93 # CHECK: vcvta.u32.f16 s2, s3
94 [0x61,0x19,0xbc,0xfe]
95
96 # CHECK: vcvtn.u32.f16 s6, s23
97 [0x6b,0x39,0xbd,0xfe]
98
99 # CHECK: vcvtp.u32.f16 s0, s4
100 [0x42,0x09,0xbe,0xfe]
101
102 # CHECK: vcvtm.u32.f16 s17, s8
103 [0x44,0x89,0xff,0xfe]
104
105 # CHECK: vselge.f16 s4, s1, s23
106 [0xab,0x29,0x20,0xfe]
107
108 # CHECK: vselgt.f16 s0, s1, s0
109 [0x80,0x09,0x30,0xfe]
110
111 # CHECK: vseleq.f16 s30, s28, s23
112 [0x2b,0xf9,0x0e,0xfe]
113
114 # CHECK: vselvs.f16 s21, s16, s14
115 [0x07,0xa9,0x58,0xfe]
116
117 # CHECK: vmaxnm.f16 s5, s12, s0
118 [0x00,0x29,0xc6,0xfe]
119
120 # CHECK: vminnm.f16 s0, s0, s12
121 [0x46,0x09,0x80,0xfe]
122
123 # CHECK: vrintz.f16 s3, s24
124 [0xcc,0x19,0xf6,0xee]
125
126 # CHECK: vrintr.f16 s0, s9
127 [0x64,0x09,0xb6,0xee]
128
129 # CHECK: vrintx.f16 s10, s14
130 [0x47,0x59,0xb7,0xee]
131
132 # CHECK: vrinta.f16 s12, s1
133 [0x60,0x69,0xb8,0xfe]
134
135 # CHECK: vrintn.f16 s12, s1
136 [0x60,0x69,0xb9,0xfe]
137
138 # CHECK: vrintp.f16 s12, s1
139 [0x60,0x69,0xba,0xfe]
140
141 # CHECK: vrintm.f16 s12, s1
142 [0x60,0x69,0xbb,0xfe]
143
144 # CHECK: vfma.f16 s2, s7, s4
145 [0x82,0x19,0xa3,0xee]
146
147 # CHECK: vfms.f16 s2, s7, s4
148 [0xc2,0x19,0xa3,0xee]
149
150 # CHECK: vfnma.f16 s2, s7, s4
151 [0xc2,0x19,0x93,0xee]
152
153 # CHECK: vfnms.f16 s2, s7, s4
154 [0x82,0x19,0x93,0xee]
155
156 # CHECK: vmovx.f16 s2, s5
157 # CHECK: vins.f16 s2, s5
158 [0x62,0x1a,0xb0,0xfe]
159 [0xe2,0x1a,0xb0,0xfe]
160
161 # CHECK: vldr.16 s1, [pc, #6]
162 # CHECK: vldr.16 s2, [pc, #510]
163 # CHECK: vldr.16 s3, [pc, #-510]
164 # CHECK: vldr.16 s4, [r4, #-18]
165 [0x03,0x09,0xdf,0xed]
166 [0xff,0x19,0x9f,0xed]
167 [0xff,0x19,0x5f,0xed]
168 [0x09,0x29,0x14,0xed]
169
170 # CHECK: vstr.16 s1, [pc, #6]
171 # CHECK: vstr.16 s2, [pc, #510]
172 # CHECK: vstr.16 s3, [pc, #-510]
173 # CHECK: vstr.16 s4, [r4, #-18]
174 [0x03,0x09,0xcf,0xed]
175 [0xff,0x19,0x8f,0xed]
176 [0xff,0x19,0x4f,0xed]
177 [0x09,0x29,0x04,0xed]
178
179 # CHECK: vmov.f16 s0, #1.0
180 [0x00,0x09,0xb7,0xee]
181
182 # CHECK: vmov.f16 s1, r2
183 # CHECK: vmov.f16 r3, s4
184 [0x90,0x29,0x00,0xee]
185 [0x10,0x39,0x12,0xee]
0 # RUN: not llvm-mc -disassemble -triple thumbv8a-none-eabi -mattr=-fullfp16,+thumb-mode -show-encoding < %s 2>&1 | FileCheck %s
1
2 # CHECK: warning: invalid instruction encoding
3 [0x30,0xee,0x80,0x09]
4
5 # CHECK: warning: invalid instruction encoding
6 [0x30,0xee,0xc0,0x09]
7
8 # CHECK: warning: invalid instruction encoding
9 [0x80,0xee,0x80,0x09]
10
11 # CHECK: warning: invalid instruction encoding
12 [0x20,0xee,0x80,0x09]
13
14 # CHECK: warning: invalid instruction encoding
15 [0x20,0xee,0xc0,0x09]
16
17 # CHECK: warning: invalid instruction encoding
18 [0x41,0xee,0x00,0x09]
19
20 # CHECK: warning: invalid instruction encoding
21 [0x41,0xee,0x40,0x09]
22
23 # CHECK: warning: invalid instruction encoding
24 [0x51,0xee,0x40,0x09]
25
26 # CHECK: warning: invalid instruction encoding
27 [0x51,0xee,0x00,0x09]
28
29 # CHECK: warning: invalid instruction encoding
30 [0xb4,0xee,0x60,0x09]
31
32 # CHECK: warning: invalid instruction encoding
33 [0xb5,0xee,0x40,0x19]
34
35 # CHECK: warning: invalid instruction encoding
36 [0xf4,0xee,0xc0,0x09]
37
38 # CHECK: warning: invalid instruction encoding
39 [0xb5,0xee,0xc0,0x09]
40
41 # CHECK: warning: invalid instruction encoding
42 [0xb0,0xee,0xc0,0x09]
43
44 # CHECK: warning: invalid instruction encoding
45 [0xb1,0xee,0x40,0x09]
46
47 # CHECK: warning: invalid instruction encoding
48 [0xb1,0xee,0xc0,0x09]
49
50 # CHECK: warning: invalid instruction encoding
51 # CHECK: warning: invalid instruction encoding
52 # CHECK: warning: invalid instruction encoding
53 # CHECK: warning: invalid instruction encoding
54 [0xb8,0xee,0xc0,0x09]
55 [0xb8,0xee,0x40,0x09]
56 [0xbd,0xee,0xc0,0x09]
57 [0xbc,0xee,0xc0,0x09]
58
59 # CHECK: warning: invalid instruction encoding
60 # CHECK: warning: invalid instruction encoding
61 [0xbd,0xee,0x60,0x09]
62 [0xbc,0xee,0x60,0x09]
63
64 # CHECK: warning: invalid instruction encoding
65 # CHECK: warning: invalid instruction encoding
66 # CHECK: warning: invalid instruction encoding
67 # CHECK: warning: invalid instruction encoding
68 # CHECK: warning: invalid instruction encoding
69 # CHECK: warning: invalid instruction encoding
70 # CHECK: warning: invalid instruction encoding
71 # CHECK: warning: invalid instruction encoding
72 [0xbb,0xee,0xc6,0x09]
73 [0xbb,0xee,0x67,0x09]
74 [0xfa,0xee,0xc6,0x09]
75 [0xfa,0xee,0x67,0x89]
76 [0xbf,0xee,0xc6,0x69]
77 [0xbf,0xee,0x67,0xe9]
78 [0xfe,0xee,0xc6,0x09]
79 [0xfe,0xee,0x67,0x89]
80
81 # CHECK: warning: invalid instruction encoding
82 [0xbc,0xfe,0xe1,0x19]
83
84 # CHECK: warning: invalid instruction encoding
85 [0xbd,0xfe,0xeb,0x39]
86
87 # CHECK: warning: invalid instruction encoding
88 [0xbe,0xfe,0xc2,0x09]
89
90 # CHECK: warning: invalid instruction encoding
91 [0xff,0xfe,0xc4,0x89]
92
93 # CHECK: warning: invalid instruction encoding
94 [0xbc,0xfe,0x61,0x19]
95
96 # CHECK: warning: invalid instruction encoding
97 [0xbd,0xfe,0x6b,0x39]
98
99 # CHECK: warning: invalid instruction encoding
100 [0xbe,0xfe,0x42,0x09]
101
102 # CHECK: warning: invalid instruction encoding
103 [0xff,0xfe,0x44,0x89]
104
105 # CHECK: warning: invalid instruction encoding
106 [0x20,0xfe,0xab,0x29]
107
108 # CHECK: warning: invalid instruction encoding
109 [0x30,0xfe,0x80,0x09]
110
111 # CHECK: warning: invalid instruction encoding
112 [0x0e,0xfe,0x2b,0xf9]
113
114 # CHECK: warning: invalid instruction encoding
115 [0x58,0xfe,0x07,0xa9]
116
117 # CHECK: warning: invalid instruction encoding
118 [0xc6,0xfe,0x00,0x29]
119
120 # CHECK: warning: invalid instruction encoding
121 [0x80,0xfe,0x46,0x09]
122
123 # CHECK: warning: invalid instruction encoding
124 [0xf6,0xee,0xcc,0x19]
125
126 # CHECK: warning: invalid instruction encoding
127 [0xb6,0xee,0x64,0x09]
128
129 # CHECK: warning: invalid instruction encoding
130 [0xb7,0xee,0x47,0x59]
131
132 # CHECK: warning: invalid instruction encoding
133 [0xb8,0xfe,0x60,0x69]
134
135 # CHECK: warning: invalid instruction encoding
136 [0xb9,0xfe,0x60,0x69]
137
138 # CHECK: warning: invalid instruction encoding
139 [0xba,0xfe,0x60,0x69]
140
141 # CHECK: warning: invalid instruction encoding
142 [0xbb,0xfe,0x60,0x69]
143
144 # CHECK: warning: invalid instruction encoding
145 [0xa3,0xee,0x82,0x19]
146
147 # CHECK: warning: invalid instruction encoding
148 [0xa3,0xee,0xc2,0x19]
149
150 # CHECK: warning: invalid instruction encoding
151 [0x93,0xee,0xc2,0x19]
152
153 # CHECK: warning: invalid instruction encoding
154 [0x93,0xee,0x82,0x19]
155
156 # CHECK: warning: invalid instruction encoding
157 # CHECK: warning: invalid instruction encoding
158 [0xb0,0xfe,0x62,0x1a]
159 [0xb0,0xfe,0xe2,0x1a]
160
161 # CHECK: warning: invalid instruction encoding
162 # CHECK: warning: invalid instruction encoding
163 # CHECK: warning: invalid instruction encoding
164 # CHECK: warning: invalid instruction encoding
165 [0xdf,0xed,0x03,0x09]
166 [0x9f,0xed,0xff,0x19]
167 [0x5f,0xed,0xff,0x19]
168 [0x14,0xed,0x09,0x29]
169
170 # CHECK: warning: invalid instruction encoding
171 # CHECK: warning: invalid instruction encoding
172 # CHECK: warning: invalid instruction encoding
173 # CHECK: warning: invalid instruction encoding
174 [0xcf,0xed,0x03,0x09]
175 [0x8f,0xed,0xff,0x19]
176 [0x4f,0xed,0xff,0x19]
177 [0x04,0xed,0x09,0x29]
178
179 # CHECK: warning: invalid instruction encoding
180 [0xb7,0xee,0x00,0x09]
181
182 # CHECK: warning: invalid instruction encoding
183 # CHECK: warning: invalid instruction encoding
184 [0x00,0xee,0x90,0x29]
185 [0x12,0xee,0x10,0x39]
0 # RUN: llvm-mc -disassemble -triple thumbv8a-none-eabi -mattr=+fullfp16,+thumb-mode -show-encoding < %s | FileCheck %s
1
2 # CHECK: vadd.f16 s0, s1, s0
3 [0x30,0xee,0x80,0x09]
4
5 # CHECK: vsub.f16 s0, s1, s0
6 [0x30,0xee,0xc0,0x09]
7
8 # CHECK: vdiv.f16 s0, s1, s0
9 [0x80,0xee,0x80,0x09]
10
11 # CHECK: vmul.f16 s0, s1, s0
12 [0x20,0xee,0x80,0x09]
13
14 # CHECK: vnmul.f16 s0, s1, s0
15 [0x20,0xee,0xc0,0x09]
16
17 # CHECK: vmla.f16 s1, s2, s0
18 [0x41,0xee,0x00,0x09]
19
20 # CHECK: vmls.f16 s1, s2, s0
21 [0x41,0xee,0x40,0x09]
22
23 # CHECK: vnmla.f16 s1, s2, s0
24 [0x51,0xee,0x40,0x09]
25
26 # CHECK: vnmls.f16 s1, s2, s0
27 [0x51,0xee,0x00,0x09]
28
29 # CHECK: vcmp.f16 s0, s1
30 [0xb4,0xee,0x60,0x09]
31
32 # CHECK: vcmp.f16 s2, #0
33 [0xb5,0xee,0x40,0x19]
34
35 # CHECK: vcmpe.f16 s1, s0
36 [0xf4,0xee,0xc0,0x09]
37
38 # CHECK: vcmpe.f16 s0, #0
39 [0xb5,0xee,0xc0,0x09]
40
41 # CHECK: vabs.f16 s0, s0
42 [0xb0,0xee,0xc0,0x09]
43
44 # CHECK: vneg.f16 s0, s0
45 [0xb1,0xee,0x40,0x09]
46
47 # CHECK: vsqrt.f16 s0, s0
48 [0xb1,0xee,0xc0,0x09]
49
50 # CHECK: vcvt.f16.s32 s0, s0
51 # CHECK: vcvt.f16.u32 s0, s0
52 # CHECK: vcvt.s32.f16 s0, s0
53 # CHECK: vcvt.u32.f16 s0, s0
54 [0xb8,0xee,0xc0,0x09]
55 [0xb8,0xee,0x40,0x09]
56 [0xbd,0xee,0xc0,0x09]
57 [0xbc,0xee,0xc0,0x09]
58
59 # CHECK: vcvtr.s32.f16 s0, s1
60 # CHECK: vcvtr.u32.f16 s0, s1
61 [0xbd,0xee,0x60,0x09]
62 [0xbc,0xee,0x60,0x09]
63
64 # CHECK: vcvt.f16.u32 s0, s0, #20
65 # CHECK: vcvt.f16.u16 s0, s0, #1
66 # CHECK: vcvt.f16.s32 s1, s1, #20
67 # CHECK: vcvt.f16.s16 s17, s17, #1
68 # CHECK: vcvt.u32.f16 s12, s12, #20
69 # CHECK: vcvt.u16.f16 s28, s28, #1
70 # CHECK: vcvt.s32.f16 s1, s1, #20
71 # CHECK: vcvt.s16.f16 s17, s17, #1
72 [0xbb,0xee,0xc6,0x09]
73 [0xbb,0xee,0x67,0x09]
74 [0xfa,0xee,0xc6,0x09]
75 [0xfa,0xee,0x67,0x89]
76 [0xbf,0xee,0xc6,0x69]
77 [0xbf,0xee,0x67,0xe9]
78 [0xfe,0xee,0xc6,0x09]
79 [0xfe,0xee,0x67,0x89]
80
81 # CHECK: vcvta.s32.f16 s2, s3
82 [0xbc,0xfe,0xe1,0x19]
83
84 # CHECK: vcvtn.s32.f16 s6, s23
85 [0xbd,0xfe,0xeb,0x39]
86
87 # CHECK: vcvtp.s32.f16 s0, s4
88 [0xbe,0xfe,0xc2,0x09]
89
90 # CHECK: vcvtm.s32.f16 s17, s8
91 [0xff,0xfe,0xc4,0x89]
92
93 # CHECK: vcvta.u32.f16 s2, s3
94 [0xbc,0xfe,0x61,0x19]
95
96 # CHECK: vcvtn.u32.f16 s6, s23
97 [0xbd,0xfe,0x6b,0x39]
98
99 # CHECK: vcvtp.u32.f16 s0, s4
100 [0xbe,0xfe,0x42,0x09]
101
102 # CHECK: vcvtm.u32.f16 s17, s8
103 [0xff,0xfe,0x44,0x89]
104
105 # CHECK: vselge.f16 s4, s1, s23
106 [0x20,0xfe,0xab,0x29]
107
108 # CHECK: vselgt.f16 s0, s1, s0
109 [0x30,0xfe,0x80,0x09]
110
111 # CHECK: vseleq.f16 s30, s28, s23
112 [0x0e,0xfe,0x2b,0xf9]
113
114 # CHECK: vselvs.f16 s21, s16, s14
115 [0x58,0xfe,0x07,0xa9]
116
117 # CHECK: vmaxnm.f16 s5, s12, s0
118 [0xc6,0xfe,0x00,0x29]
119
120 # CHECK: vminnm.f16 s0, s0, s12
121 [0x80,0xfe,0x46,0x09]
122
123 # CHECK: vrintz.f16 s3, s24
124 [0xf6,0xee,0xcc,0x19]
125
126 # CHECK: vrintr.f16 s0, s9
127 [0xb6,0xee,0x64,0x09]
128
129 # CHECK: vrintx.f16 s10, s14
130 [0xb7,0xee,0x47,0x59]
131
132 # CHECK: vrinta.f16 s12, s1
133 [0xb8,0xfe,0x60,0x69]
134
135 # CHECK: vrintn.f16 s12, s1
136 [0xb9,0xfe,0x60,0x69]
137
138 # CHECK: vrintp.f16 s12, s1
139 [0xba,0xfe,0x60,0x69]
140
141 # CHECK: vrintm.f16 s12, s1
142 [0xbb,0xfe,0x60,0x69]
143
144 # CHECK: vfma.f16 s2, s7, s4
145 [0xa3,0xee,0x82,0x19]
146
147 # CHECK: vfms.f16 s2, s7, s4
148 [0xa3,0xee,0xc2,0x19]
149
150 # CHECK: vfnma.f16 s2, s7, s4
151 [0x93,0xee,0xc2,0x19]
152
153 # CHECK: vfnms.f16 s2, s7, s4
154 [0x93,0xee,0x82,0x19]
155
156 # CHECK: vmovx.f16 s2, s5
157 # CHECK: vins.f16 s2, s5
158 [0xb0,0xfe,0x62,0x1a]
159 [0xb0,0xfe,0xe2,0x1a]
160
161 # CHECK: vldr.16 s1, [pc, #6]
162 # CHECK: vldr.16 s2, [pc, #510]
163 # CHECK: vldr.16 s3, [pc, #-510]
164 # CHECK: vldr.16 s4, [r4, #-18]
165 [0xdf,0xed,0x03,0x09]
166 [0x9f,0xed,0xff,0x19]
167 [0x5f,0xed,0xff,0x19]
168 [0x14,0xed,0x09,0x29]
169
170 # CHECK: vstr.16 s1, [pc, #6]
171 # CHECK: vstr.16 s2, [pc, #510]
172 # CHECK: vstr.16 s3, [pc, #-510]
173 # CHECK: vstr.16 s4, [r4, #-18]
174 [0xcf,0xed,0x03,0x09]
175 [0x8f,0xed,0xff,0x19]
176 [0x4f,0xed,0xff,0x19]
177 [0x04,0xed,0x09,0x29]
178
179 # CHECK: vmov.f16 s0, #1.0
180 [0xb7,0xee,0x00,0x09]
181
182 # CHECK: vmov.f16 s1, r2
183 # CHECK: vmov.f16 r3, s4
184 [0x00,0xee,0x90,0x29]
185 [0x12,0xee,0x10,0x39]