llvm.org GIT mirror llvm / 8f707e1
rename hasVariableOperands() -> isVariadic(). Add some comments. Evan, please review the comments I added to getNumDefs to make sure that they are accurate, thx. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45687 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 11 years ago
8 changed file(s) with 33 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
124124 // block.
125125 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
126126
127 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
128 // operands in addition to the minimum number operands specified.
129 const unsigned M_VARIABLE_OPS = 1 << 13;
127 const unsigned M_VARIADIC = 1 << 13;
130128
131129 // M_PREDICABLE - Set if this instruction has a predicate operand that
132130 // controls execution. It may be set to 'always'.
140138 // (e.g. instructions with unique labels attached).
141139 const unsigned M_NOT_DUPLICABLE = 1 << 16;
142140
143 // M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
144 // ARM instructions which can set condition code if 's' bit is set.
145141 const unsigned M_HAS_OPTIONAL_DEF = 1 << 17;
146142
147143 // M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that
181177 /// it is set. Returns -1 if it is not set.
182178 int getOperandConstraint(unsigned OpNum,
183179 TOI::OperandConstraint Constraint) const {
184 assert((OpNum < NumOperands || hasVariableOperands()) &&
180 assert((OpNum < NumOperands || isVariadic()) &&
185181 "Invalid operand # of TargetInstrInfo");
186182 if (OpNum < NumOperands &&
187183 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
201197 return Name;
202198 }
203199
200 /// getNumOperands - Return the number of declared MachineOperands for this
201 /// MachineInstruction. Note that variadic (isVariadic() returns true)
202 /// instructions may have additional operands at the end of the list, and note
203 /// that the machine instruction may include implicit register def/uses as
204 /// well.
204205 unsigned getNumOperands() const {
205206 return NumOperands;
206207 }
207208
209 /// getNumDefs - Return the number of MachineOperands that are register
210 /// definitions. Register definitions always occur at the start of the
211 /// machine operand list. This is the number of "outs" in the .td file.
208212 unsigned getNumDefs() const {
209213 return NumDefs;
210214 }
211215
212 bool hasVariableOperands() const {
213 return Flags & M_VARIABLE_OPS;
214 }
215
216 /// isVariadic - Return true if this instruction can have a variable number of
217 /// operands. In this case, the variable operands will be after the normal
218 /// operands but before the implicit definitions and uses (if any are
219 /// present).
220 bool isVariadic() const {
221 return Flags & M_VARIADIC;
222 }
223
224 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
225 /// ARM instructions which can set condition code if 's' bit is set.
216226 bool hasOptionalDef() const {
217227 return Flags & M_HAS_OPTIONAL_DEF;
218228 }
487487 ///
488488 bool MachineInstr::OperandsComplete() const {
489489 unsigned short NumOperands = TID->getNumOperands();
490 if (TID->hasVariableOperands() == 0 &&
491 getNumOperands()-NumImplicitOps >= NumOperands)
490 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
492491 return true; // Broken: we have all the operands of this instruction!
493492 return false;
494493 }
497496 ///
498497 unsigned MachineInstr::getNumExplicitOperands() const {
499498 unsigned NumOperands = TID->getNumOperands();
500 if (TID->hasVariableOperands() == 0)
499 if (!TID->isVariadic())
501500 return NumOperands;
502501
503502 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
293293 const TargetInstrDescriptor *II,
294294 unsigned Op) {
295295 if (Op >= II->getNumOperands()) {
296 assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
296 assert(II->isVariadic() && "Invalid operand # of instruction");
297297 return NULL;
298298 }
299299 if (II->OpInfo[Op].isLookupPtrRegClass())
677677 II.getImplicitDefs() != 0;
678678 #ifndef NDEBUG
679679 assert((II.getNumOperands() == NumMIOperands ||
680 HasPhysRegOuts || II.hasVariableOperands()) &&
680 HasPhysRegOuts || II.isVariadic()) &&
681681 "#operands for dag node doesn't match .td file!");
682682 #endif
683683
798798 break;
799799 }
800800
801 assert((Desc->Flags & M_VARIABLE_OPS) != 0 ||
802 CurOp == NumOps && "Unknown encoding!");
803 }
801 assert((Desc->isVariadic() || CurOp == NumOps) && "Unknown encoding!");
802 }
9898 mayHaveSideEffects = R->getValueAsBit("mayHaveSideEffects");
9999 neverHasSideEffects = R->getValueAsBit("neverHasSideEffects");
100100 hasOptionalDef = false;
101 hasVariableNumberOfOperands = false;
101 isVariadic = false;
102102
103103 if (mayHaveSideEffects && neverHasSideEffects)
104104 throw R->getName() +
158158 else if (Rec->isSubClassOf("OptionalDefOperand"))
159159 hasOptionalDef = true;
160160 } else if (Rec->getName() == "variable_ops") {
161 hasVariableNumberOfOperands = true;
161 isVariadic = true;
162162 continue;
163163 } else if (!Rec->isSubClassOf("RegisterClass") &&
164164 Rec->getName() != "ptr_rc")
9898 bool isReMaterializable;
9999 bool hasDelaySlot;
100100 bool usesCustomDAGSchedInserter;
101 bool hasVariableNumberOfOperands;
101 bool isVariadic;
102102 bool hasCtrlDep;
103103 bool isNotDuplicable;
104104 bool hasOptionalDef;
834834 if (InstPatNode && InstPatNode->getOperator()->getName() == "set") {
835835 InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1);
836836 }
837 bool HasVarOps = isRoot && II.hasVariableNumberOfOperands;
837 bool HasVarOps = isRoot && II.isVariadic;
838838 // FIXME: fix how we deal with physical register operands.
839839 bool HasImpInputs = isRoot && Inst.getNumImpOperands() > 0;
840840 bool HasImpResults = isRoot && DstRegs.size() > 0;
319319 if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF";
320320 if (Inst.usesCustomDAGSchedInserter)
321321 OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
322 if (Inst.hasVariableNumberOfOperands) OS << "|M_VARIABLE_OPS";
323 if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
324 if (NeverHasSideEffects) OS << "|M_NEVER_HAS_SIDE_EFFECTS";
322 if (Inst.isVariadic) OS << "|M_VARIADIC";
323 if (Inst.mayHaveSideEffects) OS << "|M_MAY_HAVE_SIDE_EFFECTS";
324 if (NeverHasSideEffects) OS << "|M_NEVER_HAS_SIDE_EFFECTS";
325325 OS << ", 0";
326326
327327 // Emit all of the target-specific flags...