llvm.org GIT mirror llvm / 8f16e02
Allow the machine verifier to be run outside the PassManager. Verify LiveVariables information when present. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89241 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 11 years ago
2 changed file(s) with 168 addition(s) and 25 deletion(s). Raw diff Collapse all Expand all
232232
233233 /// verify - Run the current MachineFunction through the machine code
234234 /// verifier, useful for debugger use.
235 void verify() const;
235 void verify(Pass *p=NULL, bool allowDoubleDefs=false) const;
236236
237237 // Provide accessors for the MachineBasicBlock list...
238238 typedef BasicBlockListType::iterator iterator;
4141 using namespace llvm;
4242
4343 namespace {
44 struct MachineVerifier : public MachineFunctionPass {
45 static char ID; // Pass ID, replacement for typeid
46
47 MachineVerifier(bool allowDoubleDefs = false) :
48 MachineFunctionPass(&ID),
44 struct MachineVerifier {
45
46 MachineVerifier(Pass *pass, bool allowDoubleDefs) :
47 PASS(pass),
4948 allowVirtDoubleDefs(allowDoubleDefs),
5049 allowPhysDoubleDefs(allowDoubleDefs),
5150 OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
52 {}
53
54 void getAnalysisUsage(AnalysisUsage &AU) const {
55 AU.setPreservesAll();
56 MachineFunctionPass::getAnalysisUsage(AU);
57 }
51 {}
5852
5953 bool runOnMachineFunction(MachineFunction &MF);
6054
55 Pass *const PASS;
6156 const bool allowVirtDoubleDefs;
6257 const bool allowPhysDoubleDefs;
6358
110105 // Vregs that pass through MBB untouched. This set is disjoint from
111106 // regsKilled and regsLiveOut.
112107 RegSet vregsPassed;
108
109 // Vregs that must pass through MBB because they are needed by a successor
110 // block. This set is disjoint from regsLiveOut.
111 RegSet vregsRequired;
113112
114113 BBInfo() : reachable(false) {}
115114
132131 return changed;
133132 }
134133
134 // Add register to vregsRequired if it belongs there. Return true if
135 // anything changed.
136 bool addRequired(unsigned Reg) {
137 if (!TargetRegisterInfo::isVirtualRegister(Reg))
138 return false;
139 if (regsLiveOut.count(Reg))
140 return false;
141 return vregsRequired.insert(Reg).second;
142 }
143
144 // Same for a full set.
145 bool addRequired(const RegSet &RS) {
146 bool changed = false;
147 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
148 if (addRequired(*I))
149 changed = true;
150 return changed;
151 }
152
153 // Same for a full map.
154 bool addRequired(const RegMap &RM) {
155 bool changed = false;
156 for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
157 if (addRequired(I->first))
158 changed = true;
159 return changed;
160 }
161
135162 // Live-out registers are either in regsLiveOut or vregsPassed.
136163 bool isLiveOut(unsigned Reg) const {
137164 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
144171 bool isReserved(unsigned Reg) {
145172 return Reg < regsReserved.size() && regsReserved.test(Reg);
146173 }
174
175 // Analysis information if available
176 LiveVariables *LiveVars;
147177
148178 void visitMachineFunctionBefore();
149179 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
162192 void calcMaxRegsPassed();
163193 void calcMinRegsPassed();
164194 void checkPHIOps(const MachineBasicBlock *MBB);
195
196 void calcRegsRequired();
197 void verifyLiveVariables();
165198 };
166 }
167
168 char MachineVerifier::ID = 0;
169 static RegisterPass
199
200 struct MachineVerifierPass : public MachineFunctionPass {
201 static char ID; // Pass ID, replacement for typeid
202 bool AllowDoubleDefs;
203
204 explicit MachineVerifierPass(bool allowDoubleDefs = false)
205 : MachineFunctionPass(&ID),
206 AllowDoubleDefs(allowDoubleDefs) {}
207
208 void getAnalysisUsage(AnalysisUsage &AU) const {
209 AU.setPreservesAll();
210 MachineFunctionPass::getAnalysisUsage(AU);
211 }
212
213 bool runOnMachineFunction(MachineFunction &MF) {
214 MF.verify(this, AllowDoubleDefs);
215 return false;
216 }
217 };
218
219 }
220
221 char MachineVerifierPass::ID = 0;
222 static RegisterPass
170223 MachineVer("machineverifier", "Verify generated machine code");
171224 static const PassInfo *const MachineVerifyID = &MachineVer;
172225
173226 FunctionPass *llvm::createMachineVerifierPass(bool allowPhysDoubleDefs) {
174 return new MachineVerifier(allowPhysDoubleDefs);
175 }
176
177 void MachineFunction::verify() const {
178 MachineVerifier().runOnMachineFunction(const_cast(*this));
227 return new MachineVerifierPass(allowPhysDoubleDefs);
228 }
229
230 void MachineFunction::verify(Pass *p, bool allowDoubleDefs) const {
231 MachineVerifier(p, allowDoubleDefs)
232 .runOnMachineFunction(const_cast(*this));
179233 }
180234
181235 bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
200254 TM = &MF.getTarget();
201255 TRI = TM->getRegisterInfo();
202256 MRI = &MF.getRegInfo();
257
258 if (PASS) {
259 LiveVars = PASS->getAnalysisIfAvailable();
260 } else {
261 LiveVars = NULL;
262 }
203263
204264 visitMachineFunctionBefore();
205265 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
517577 } else if (MO->isUse()) {
518578 regsLiveInButUnused.erase(Reg);
519579
580 bool isKill = false;
520581 if (MO->isKill()) {
521 addRegWithSubRegs(regsKilled, Reg);
582 isKill = true;
522583 // Tied operands on two-address instuctions MUST NOT have a flag.
523584 if (MI->isRegTiedToDefOperand(MONum))
524585 report("Illegal kill flag on two-address instruction operand",
528589 unsigned defIdx;
529590 if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
530591 MI->getOperand(defIdx).getReg() == Reg)
531 addRegWithSubRegs(regsKilled, Reg);
532 }
592 isKill = true;
593 }
594 if (isKill) {
595 addRegWithSubRegs(regsKilled, Reg);
596
597 // Check that LiveVars knows this kill
598 if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg)) {
599 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
600 if (std::find(VI.Kills.begin(),
601 VI.Kills.end(), MI) == VI.Kills.end())
602 report("Kill missing from LiveVariables", MO, MONum);
603 }
604 }
605
533606 // Use of a dead register.
534607 if (!regsLive.count(Reg)) {
535608 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
733806 }
734807 }
735808
809 // Calculate the set of virtual registers that must be passed through each basic
810 // block in order to satisfy the requirements of successor blocks. This is very
811 // similar to calcMaxRegsPassed, only backwards.
812 void MachineVerifier::calcRegsRequired() {
813 // First push live-in regs to predecessors' vregsRequired.
814 DenseSet todo;
815 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
816 MFI != MFE; ++MFI) {
817 const MachineBasicBlock &MBB(*MFI);
818 BBInfo &MInfo = MBBInfoMap[&MBB];
819 for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
820 PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
821 BBInfo &PInfo = MBBInfoMap[*PrI];
822 if (PInfo.addRequired(MInfo.vregsLiveIn))
823 todo.insert(*PrI);
824 }
825 }
826
827 // Iteratively push vregsRequired to predecessors. This will converge to the
828 // same final state regardless of DenseSet iteration order.
829 while (!todo.empty()) {
830 const MachineBasicBlock *MBB = *todo.begin();
831 todo.erase(MBB);
832 BBInfo &MInfo = MBBInfoMap[MBB];
833 for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
834 PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
835 if (*PrI == MBB)
836 continue;
837 BBInfo &SInfo = MBBInfoMap[*PrI];
838 if (SInfo.addRequired(MInfo.vregsRequired))
839 todo.insert(*PrI);
840 }
841 }
842 }
843
736844 // Check PHI instructions at the beginning of MBB. It is assumed that
737845 // calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
738846 void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
848956 }
849957 }
850958 }
851 }
959
960 // Now check LiveVariables info if available
961 if (LiveVars) {
962 calcRegsRequired();
963 verifyLiveVariables();
964 }
965 }
966
967 void MachineVerifier::verifyLiveVariables() {
968 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
969 for (unsigned Reg = TargetRegisterInfo::FirstVirtualRegister,
970 RegE = MRI->getLastVirtReg()-1; Reg != RegE; ++Reg) {
971 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
972 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
973 MFI != MFE; ++MFI) {
974 BBInfo &MInfo = MBBInfoMap[MFI];
975
976 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
977 if (MInfo.vregsRequired.count(Reg)) {
978 if (!VI.AliveBlocks.test(MFI->getNumber())) {
979 report("LiveVariables: Block missing from AliveBlocks", MFI);
980 *OS << "Virtual register %reg" << Reg
981 << " must be live through the block.\n";
982 }
983 } else {
984 if (VI.AliveBlocks.test(MFI->getNumber())) {
985 report("LiveVariables: Block should not be in AliveBlocks", MFI);
986 *OS << "Virtual register %reg" << Reg
987 << " is not needed live through the block.\n";
988 }
989 }
990 }
991 }
992 }
993
994