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How to write an LLVM backend, first draft. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16203 91177308-0d34-0410-b5e6-96231b3b80d8 Misha Brukman 15 years ago
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4 Writing an LLVM backend
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11 Writing an LLVM backend
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  • Introduction
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  • Writing a backend
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  • Machine backends
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  • Outline
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  • Implementation details
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  • Machine backends
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  • Language backends
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  • Related reading material
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    Written by Misha Brukman

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    35 Introduction
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    This document describes techniques for writing backends for LLVM which

    42 convert the LLVM representation to machine assembly code or other languages.

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    48 Writing a backend
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    54 Machine backends
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    59 Outline
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    In general, you want to follow the format of X86 or PowerPC (in

    65 lib/Target).

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    To create a static compiler (one that emits text assembly), you need to

    68 implement the following:

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  • Describe the register set
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  • Create a TableGen description of
  • 74 the register set and register classes
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  • Implement a subclass of
  • 76 href="CodeGenerator.html#mregisterinfo">MRegisterInfo
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  • Describe the instruction set
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  • Create a TableGen description of
  • 81 the instruction set
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  • Implement a subclass of
  • 83 href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo
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  • Describe the target machine
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  • Create a TableGen description of
  • 88 the target that describes the pointer size and references the instruction
    89 set
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  • Implement a subclass of
  • 91 href="CodeGenerator.html#targetmachine">TargetMachine, which
    92 configures TargetData
    93 correctly
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  • Implement the assembly printer for the architecture. Usually, if you have
  • 96 described the instruction set with the assembly printer generator in mind, that
    97 step can be almost automated.
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    Now, for static code generation you also need to write an instruction

    101 selector for your platform: see lib/Target/*/*ISelSimple.cpp which
    102 is no longer "simple" but it gives you the idea: you have to be able to create
    103 MachineInstrs for any given LLVM instruction using the InstVisitor
    104 pattern, and produce a MachineFunction with
    105 MachineBasicBlocks full of
    106 href="CodeGenerator.html#machineinstr">MachineInstrs for a
    107 corresponding LLVM Function. Creating an instruction selector is perhaps the
    108 most time-consuming part of creating a back-end.

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    To create a JIT for your platform:

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  • Create a subclass of
  • 114 href="CodeGenerator.html#targetjitinfo">TargetJITInfo
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  • Create a machine code emitter that will be used to emit binary code
  • 116 directly into memory, given MachineInstrs
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    Note that lib/target/Skeleton is a clean skeleton for a new target,

    120 so you might want to start with that and adapt it for your target, and if you
    121 are wondering how things are done, peek in the X86 or PowerPC target.

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    The Skeleton target is non-functional but provides the basic building blocks

    124 you will need for your endeavor.

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  • TableGen register info description - describe a class which

  • 138 will store the register's number in the binary encoding of the instruction
    139 (e.g., for JIT purposes).

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    You also need to define register classes to contain these registers, such as

    142 the integer register class and floating-point register class, so that you can
    143 allocate virtual registers to instructions from these sets, and let the
    144 target-independent register allocator automatically choose the actual
    145 architected registers.

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    149 // class Register is defined in Target.td
    150 class TargetReg : Register {
    151 let Namespace = "Target";
    152 }
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    154 class IntReg<bits<5> num> : TargetReg {
    155 field bits<5> Num = num;
    156 }
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    158 def R0 : IntReg<0>;
    159 ...
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    161 // class RegisterClass is defined in Target.td
    162 def IReg : RegisterClass<i64, 64, [R0, ... ]>;
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  • TableGen instruction info description - break up instructions into

  • 168 classes, usually that's already done by the manufacturer (see instruction
    169 manual). Define a class for each instruction category. Define each opcode as a
    170 subclass of the category, with appropriate parameters such as the fixed binary
    171 encoding of opcodes and extended opcodes, and map the register bits to the bits
    172 of the instruction which they are encoded in (for the JIT). Also specify how
    173 the instruction should be printed so it can use the automatic assembly printer,
    174 e.g.:

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    178 // class Instruction is defined in Target.td
    179 class Form<bits<6> opcode, dag OL, string asmstr> : Instruction {
    180 field bits<42> Inst;
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    182 let Namespace = "Target";
    183 let Inst{0-6} = opcode;
    184 let OperandList = OL;
    185 let AsmString = asmstr;
    186 }
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    188 def ADD : Form<42, (ops IReg:$rD, IReg:$rA, IReg:$rB), "add $rD, $rA, $rB">;
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    199 Language backends
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    For now, just take a look at lib/Target/CBackend for an example of

    205 how the C backend is written.

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  • Code generator -
  • 219 describes some of the classes in code generation at a high level, but
    220 it is not (yet) complete.
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  • TableGen fundamentals -
  • 222 describes how to use TableGen to describe your target information succinctly
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    237 Misha Brukman
    238 The LLVM Compiler Infrastructure
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