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Use subclassing to print lane-like immediates (w/o hash) eliminating 'no_hash' modifier. Hopefully this will make Daniel happy :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 11 years ago
5 changed file(s) with 37 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
326326 let MIOperandInfo = (ops GPR, i32imm);
327327 }
328328
329 def lane_cst : Operand {
330 let PrintMethod = "printLaneOperand";
331 }
332
329333 //===----------------------------------------------------------------------===//
330334
331335 include "ARMInstrFormats.td"
576580 []>;
577581
578582 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
579 (ins i32imm:$label, i32imm:$id, pred:$p),
583 (ins i32imm:$label, lane_cst:$id, pred:$p),
580584 Pseudo, IIC_iLoad,
581585 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
582 "(${label}_${id:no_hash}-(",
586 "(${label}_${id}-(",
583587 "${:private}PCRELL${:uid}+8))\n"),
584588 !strconcat("${:private}PCRELL${:uid}:\n\t",
585589 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
16171617 // VMOV : Vector Get Lane (move scalar to ARM core register)
16181618
16191619 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1620 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1621 NoItinerary, "vmov", ".s8\t$dst, $src[${lane:no_hash}]",
1620 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1621 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
16221622 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
16231623 imm:$lane))]>;
16241624 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1625 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1626 NoItinerary, "vmov", ".s16\t$dst, $src[${lane:no_hash}]",
1625 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1626 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
16271627 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
16281628 imm:$lane))]>;
16291629 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1630 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1631 NoItinerary, "vmov", ".u8\t$dst, $src[${lane:no_hash}]",
1630 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1631 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
16321632 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
16331633 imm:$lane))]>;
16341634 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1635 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1636 NoItinerary, "vmov", ".u16\t$dst, $src[${lane:no_hash}]",
1635 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1636 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
16371637 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
16381638 imm:$lane))]>;
16391639 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1640 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1641 NoItinerary, "vmov", ".32\t$dst, $src[${lane:no_hash}]",
1640 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1641 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
16421642 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
16431643 imm:$lane))]>;
16441644 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
16741674
16751675 let Constraints = "$src1 = $dst" in {
16761676 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1677 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1678 NoItinerary, "vmov", ".8\t$dst[${lane:no_hash}], $src2",
1677 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1678 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
16791679 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
16801680 GPR:$src2, imm:$lane))]>;
16811681 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1682 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1683 NoItinerary, "vmov", ".16\t$dst[${lane:no_hash}], $src2",
1682 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1683 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
16841684 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
16851685 GPR:$src2, imm:$lane))]>;
16861686 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1687 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1688 NoItinerary, "vmov", ".32\t$dst[${lane:no_hash}], $src2",
1687 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1688 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
16891689 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
16901690 GPR:$src2, imm:$lane))]>;
16911691 }
17681768
17691769 class VDUPLND op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
17701770 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1771 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane), NoItinerary,
1772 !strconcat(OpcodeStr, "\t$dst, $src[${lane:no_hash}]"), "",
1771 (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1772 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
17731773 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
17741774
17751775 // vector_shuffle requires that the source and destination types match, so
17771777 class VDUPLNQ op19_18, bits<2> op17_16, string OpcodeStr,
17781778 ValueType ResTy, ValueType OpTy>
17791779 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1780 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane), NoItinerary,
1781 !strconcat(OpcodeStr, "\t$dst, $src[${lane:no_hash}]"), "",
1780 (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1781 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
17821782 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
17831783
17841784 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
613613 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label), IIC_iALU,
614614 "adr $dst, #$label", []>;
615615
616 def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id), IIC_iALU,
617 "adr $dst, #${label}_${id:no_hash}", []>;
616 def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, lane_cst:$id), IIC_iALU,
617 "adr $dst, #${label}_${id}", []>;
618618
619619 //===----------------------------------------------------------------------===//
620620 // TLS Instructions
428428 "adr$p.w $dst, #$label", []>;
429429
430430 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
431 (ins i32imm:$label, i32imm:$id, pred:$p), IIC_iALU,
432 "adr$p.w $dst, #${label}_${id:no_hash}", []>;
431 (ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALU,
432 "adr$p.w $dst, #${label}_${id}", []>;
433433
434434
435435 // ADD r, sp, {so_imm|i12}
161161 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
162162 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
163163 void printTBAddrMode(const MachineInstr *MI, int OpNum);
164 void printLaneOperand(const MachineInstr *MI, int OpNum);
164165
165166 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
166167 unsigned AsmVariant, const char *ExtraCode);
357358 break;
358359 }
359360 case MachineOperand::MO_Immediate: {
360 if (!Modifier || strcmp(Modifier, "no_hash") != 0)
361 O << '#';
362
363 O << MO.getImm();
361 O << '#' << MO.getImm();
364362 break;
365363 }
366364 case MachineOperand::MO_MachineBasicBlock:
10101008 O << ']';
10111009 }
10121010
1011 void ARMAsmPrinter::printLaneOperand(const MachineInstr *MI, int OpNum) {
1012 O << MI->getOperand(OpNum).getImm();
1013 }
10131014
10141015 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
10151016 unsigned AsmVariant, const char *ExtraCode){
10161017 // Does this asm operand have a single letter operand modifier?
10171018 if (ExtraCode && ExtraCode[0]) {
10181019 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1019
1020
10201021 switch (ExtraCode[0]) {
10211022 default: return true; // Unknown modifier.
10221023 case 'a': // Print as a memory address.
10261027 }
10271028 // Fallthrough
10281029 case 'c': // Don't print "#" before an immediate operand.
1029 printOperand(MI, OpNum, "no_hash");
1030 printLaneOperand(MI, OpNum);
10301031 return false;
10311032 case 'P': // Print a VFP double precision register.
10321033 printOperand(MI, OpNum);