llvm.org GIT mirror llvm / 8e78012
R600: Add support for i8 and i16 local memory stores git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 6 years ago
9 changed file(s) with 80 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
494494 Store->getBasePtr(),
495495 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
496496 PtrVT));
497 Chains.push_back(DAG.getStore(Store->getChain(), SL, Val, Ptr,
497 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
498498 MachinePointerInfo(Store->getMemOperand()->getValue()),
499 Store->isVolatile(), Store->isNonTemporal(),
499 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
500500 Store->getAlignment()));
501501 }
502502 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, &Chains[0], NumElts);
7272 SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
7373 [SDNPHasChain, SDNPMayStore]>;
7474
75 // MSKOR instructions are atomic memory instructions used mainly for storing
76 // 8-bit and 16-bit values. The definition is:
77 //
78 // MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
79 //
80 // src0: vec4(src, 0, 0, mask)
81 // src1: dst - rat offset (aka pointer) in dwords
7582 def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
7683 SDTypeProfile<0, 2, []>,
7784 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
155155 return isGlobalStore(dyn_cast(N));
156156 }]>;
157157
158 def local_store : PatFrag<(ops node:$val, node:$ptr),
159 (store node:$val, node:$ptr), [{
160 return isLocalStore(dyn_cast(N));
161 }]>;
162
163 def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
164 (truncstorei8 node:$val, node:$ptr), [{
165 return isLocalStore(dyn_cast(N));
166 }]>;
167
168 def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
169 (truncstorei16 node:$val, node:$ptr), [{
170 return isLocalStore(dyn_cast(N));
171 }]>;
172
158173 def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
159174 return isLocalLoad(dyn_cast(N));
160 }]>;
161
162 def local_store : PatFrag<(ops node:$val, node:$ptr),
163 (store node:$val, node:$ptr), [{
164 return isLocalStore(dyn_cast(N));
165175 }]>;
166176
167177 def mskor_global : PatFrag<(ops node:$val, node:$ptr),
4444 ALU_INST = (1 << 14),
4545 LDS_1A = (1 << 15),
4646 LDS_1A1D = (1 << 16),
47 IS_EXPORT = (1 << 17)
47 IS_EXPORT = (1 << 17),
48 LDS_1A2D = (1 << 18)
4849 };
4950 }
5051
2929 bit TEXInst = 0;
3030 bit ALUInst = 0;
3131 bit IsExport = 0;
32 bit LDS_1A2D = 0;
3233
3334 let Namespace = "AMDGPU";
3435 let OutOperandList = outs;
5455 let TSFlags{15} = LDS_1A;
5556 let TSFlags{16} = LDS_1A1D;
5657 let TSFlags{17} = IsExport;
58 let TSFlags{18} = LDS_1A2D;
5759 }
5860
5961 //===----------------------------------------------------------------------===//
148148 unsigned TargetFlags = get(Opcode).TSFlags;
149149
150150 return ((TargetFlags & R600_InstFlag::LDS_1A) |
151 (TargetFlags & R600_InstFlag::LDS_1A1D));
151 (TargetFlags & R600_InstFlag::LDS_1A1D) |
152 (TargetFlags & R600_InstFlag::LDS_1A2D));
152153 }
153154
154155 bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
16561656 let LDS_1A1D = 1;
16571657 }
16581658
1659 class R600_LDS_1A2D lds_op, string name, list pattern> :
1660 R600_LDS <
1661 lds_op,
1662 (outs),
1663 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
1664 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel,
1665 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel,
1666 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle),
1667 " "#name# "$last $src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
1668 pattern> {
1669 let LDS_1A2D = 1;
1670 }
1671
1672 def LDS_WRITE : R600_LDS_1A1D <0xD, "LDS_WRITE",
1673 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
1674 >;
1675 def LDS_BYTE_WRITE : R600_LDS_1A1D<0x12, "LDS_BYTE_WRITE",
1676 [(truncstorei8_local i32:$src1, i32:$src0)]
1677 >;
1678 def LDS_SHORT_WRITE : R600_LDS_1A1D<0x13, "LDS_SHORT_WRITE",
1679 [(truncstorei16_local i32:$src1, i32:$src0)]
1680 >;
16591681 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET",
16601682 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))]
1661 >;
1662
1663 def LDS_WRITE : R600_LDS_1A1D <0xD, "LDS_WRITE",
1664 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)]
16651683 >;
16661684
16671685 // TRUNC is used for the FLT_TO_INT instructions to work around a
391391 } // End isCompare = 1
392392
393393 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
394 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>;
395 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>;
394396 def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
395397
396398 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
17491751 (i32 (DS_READ_B32 0, $src0, $src0, $src0, 0, 0))
17501752 >;
17511753
1752 def : Pat <
1753 (local_store i32:$src1, i32:$src0),
1754 (DS_WRITE_B32 0, $src0, $src1, $src1, 0, 0)
1755 >;
1754 class DSWritePat : Pat <
1755 (frag i32:$src1, i32:$src0),
1756 (inst 0, $src0, $src1, $src1, 0, 0)
1757 >;
1758
1759 def : DSWritePat ;
1760 def : DSWritePat ;
1761 def : DSWritePat ;
17561762
17571763 /********** ================== **********/
17581764 /********** SMRD Patterns **********/
171171 ; Local Address Space
172172 ;===------------------------------------------------------------------------===;
173173
174 ; EG-CHECK: @store_local_i8
175 ; EG-CHECK: LDS_BYTE_WRITE
176 ; SI-CHECK: @store_local_i8
177 ; SI-CHECK: DS_WRITE_B8
178 define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) {
179 store i8 %in, i8 addrspace(3)* %out
180 ret void
181 }
182
183 ; EG-CHECK: @store_local_i16
184 ; EG-CHECK: LDS_SHORT_WRITE
185 ; SI-CHECK: @store_local_i16
186 ; SI-CHECK: DS_WRITE_B16
187 define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) {
188 store i16 %in, i16 addrspace(3)* %out
189 ret void
190 }
191
174192 ; EG-CHECK: @store_local_v2i16
175193 ; EG-CHECK: LDS_WRITE
176194 ; CM-CHECK: @store_local_v2i16