llvm.org GIT mirror llvm / 8e63a83
[GlobalISel] Print/Parse FailedISel MachineFunction property FailedISel MachineFunction property is part of the CodeGen pipeline state as much as every other property, notably, Legalized, RegBankSelected, and Selected. Let's make that part of the state also serializable / de-serializable, so if GlobalISel aborts on some of the functions of a large module, but not the others, it could be easily seen and the state of the pipeline could be maintained through llc's invocations with -stop-after / -start-after. To make MIR printable and generally to not to break it too much too soon, this patch also defers cleaning up the vreg -> LLT map until ResetMachineFunctionPass. To make MIR with FailedISel: true also machine verifiable, machine verifier is changed so it treats a MIR-module as non-regbankselected and non-selected if there is FailedISel property set. Reviewers: qcolombet, ab Reviewed By: dsanders Subscribers: javed.absar, rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42877 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326343 91177308-0d34-0410-b5e6-96231b3b80d8 Roman Tereshin 2 years ago
7 changed file(s) with 94 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
471471 bool Legalized = false;
472472 bool RegBankSelected = false;
473473 bool Selected = false;
474 bool FailedISel = false;
474475 // Register information
475476 bool TracksRegLiveness = false;
476477 std::vector VirtualRegisters;
494495 YamlIO.mapOptional("legalized", MF.Legalized, false);
495496 YamlIO.mapOptional("regBankSelected", MF.RegBankSelected, false);
496497 YamlIO.mapOptional("selected", MF.Selected, false);
498 YamlIO.mapOptional("failedISel", MF.FailedISel, false);
497499 YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness, false);
498500 YamlIO.mapOptional("registers", MF.VirtualRegisters,
499501 std::vector());
1111
1212 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
1313 #include "llvm/ADT/PostOrderIterator.h"
14 #include "llvm/ADT/ScopeExit.h"
1514 #include "llvm/ADT/Twine.h"
1615 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
1716 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
6059 }
6160
6261 bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
63 const MachineRegisterInfo &MRI = MF.getRegInfo();
64
65 // No matter what happens, whether we successfully select the function or not,
66 // nothing is going to use the vreg types after us. Make sure they disappear.
67 auto ClearVRegTypesOnReturn =
68 make_scope_exit([&]() { MRI.getVRegToType().clear(); });
69
7062 // If the ISel pipeline failed, do not bother running that pass.
7163 if (MF.getProperties().hasProperty(
7264 MachineFunctionProperties::Property::FailedISel))
8476
8577 // FIXME: There are many other MF/MFI fields we need to initialize.
8678
79 const MachineRegisterInfo &MRI = MF.getRegInfo();
8780 #ifndef NDEBUG
8881 // Check that our input is fully legal: we require the function to have the
8982 // Legalized property, so it should be.
237230 .getTarget()
238231 .getBackendName());
239232
233 // If we successfully selected the function nothing is going to use the vreg
234 // types after us (otherwise MIRPrinter would need them). Make sure the types
235 // disappear.
236 MRI.getVRegToType().clear();
237
240238 // FIXME: Should we accurately track changes?
241239 return true;
242240 }
361361 MachineFunctionProperties::Property::RegBankSelected);
362362 if (YamlMF.Selected)
363363 MF.getProperties().set(MachineFunctionProperties::Property::Selected);
364 if (YamlMF.FailedISel)
365 MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
364366
365367 PerFunctionMIParsingState PFS(MF, SM, IRSlots, Names2RegClasses,
366368 Names2RegBanks);
206206 MachineFunctionProperties::Property::RegBankSelected);
207207 YamlMF.Selected = MF.getProperties().hasProperty(
208208 MachineFunctionProperties::Property::Selected);
209 YamlMF.FailedISel = MF.getProperties().hasProperty(
210 MachineFunctionProperties::Property::FailedISel);
209211
210212 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
211213 ModuleSlotTracker MST(MF.getFunction().getParent());
358358 TRI = MF.getSubtarget().getRegisterInfo();
359359 MRI = &MF.getRegInfo();
360360
361 isFunctionRegBankSelected = MF.getProperties().hasProperty(
362 MachineFunctionProperties::Property::RegBankSelected);
363 isFunctionSelected = MF.getProperties().hasProperty(
364 MachineFunctionProperties::Property::Selected);
365
361 const bool isFunctionFailedISel = MF.getProperties().hasProperty(
362 MachineFunctionProperties::Property::FailedISel);
363 isFunctionRegBankSelected =
364 !isFunctionFailedISel &&
365 MF.getProperties().hasProperty(
366 MachineFunctionProperties::Property::RegBankSelected);
367 isFunctionSelected = !isFunctionFailedISel &&
368 MF.getProperties().hasProperty(
369 MachineFunctionProperties::Property::Selected);
366370 LiveVars = nullptr;
367371 LiveInts = nullptr;
368372 LiveStks = nullptr;
1212 /// happen is that the MachineFunction has the FailedISel property.
1313 //===----------------------------------------------------------------------===//
1414
15 #include "llvm/ADT/ScopeExit.h"
1516 #include "llvm/ADT/Statistic.h"
1617 #include "llvm/CodeGen/MachineFunction.h"
1718 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
1820 #include "llvm/CodeGen/Passes.h"
1921 #include "llvm/IR/DiagnosticInfo.h"
2022 #include "llvm/Support/Debug.h"
4244 StringRef getPassName() const override { return "ResetMachineFunction"; }
4345
4446 bool runOnMachineFunction(MachineFunction &MF) override {
47 // No matter what happened, whether we successfully selected the function
48 // or not, nothing is going to use the vreg types after us. Make sure they
49 // disappear.
50 auto ClearVRegTypesOnReturn =
51 make_scope_exit([&MF]() { MF.getRegInfo().getVRegToType().clear(); });
52
4553 if (MF.getProperties().hasProperty(
4654 MachineFunctionProperties::Property::FailedISel)) {
4755 if (AbortOnFailedISel)
0 # RUN: llc -mtriple aarch64-- -run-pass instruction-select -simplify-mir \
1 # RUN: -verify-machineinstrs %s -o - | FileCheck %s
2 #
3 # RUN: llc -mtriple aarch64-- -global-isel=true -global-isel-abort=2 \
4 # RUN: -start-after=regbankselect -stop-before=expand-isel-pseudos \
5 # RUN: -simplify-mir -verify-machineinstrs %s -o - 2>&1 \
6 # RUN: | FileCheck %s --check-prefix=FALLBACK
7
8 # Test that:
9 # 1) MIRParser can deserialize FailedISel property.
10 # 2) Machine Verifier respects FailedISel and doesn't complain needlessly.
11 # 3) MIRPrinter is able to print FailedISel MIR after InstructionSelect pass.
12 # 4) MIRPrinter can serialize FailedISel property.
13 # 5) It's possible to start llc mid-GlobalISel pipeline from a MIR file with
14 # the FailedISel property set to true and watch it properly fallback to
15 # FastISel / SelectionDAG ISel.
16 --- |
17 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
18 target triple = "aarch64--"
19
20 define i32 @test(i32 %a, i32 %b) #0 {
21 entry:
22 %add = add i32 %b, %a
23 ret i32 %add
24 }
25
26 attributes #0 = { nounwind readnone ssp }
27 ...
28 ---
29 # CHECK-LABEL: name: test
30 # CHECK: failedISel: true
31 #
32 # FALLBACK: warning: Instruction selection used fallback path for test
33 # FALLBACK-LABEL: name: test
34 # FALLBACK-NOT: failedISel
35 name: test
36 alignment: 2
37 legalized: true
38 regBankSelected: true
39 failedISel: true
40 tracksRegLiveness: true
41 body: |
42 bb.1.entry:
43 liveins: $w0, $w1
44
45 ; CHECK: liveins: $w0, $w1
46 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
47 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
48 ; CHECK: [[ADD:%[0-9]+]]:gpr(s32) = G_ADD [[COPY1]], [[COPY]]
49 ; CHECK: $w0 = COPY [[ADD]](s32)
50 ; CHECK: RET_ReallyLR implicit $w0
51 ;
52 ; FALLBACK: liveins: $w0, $w1
53 ; FALLBACK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
54 ; FALLBACK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
55 ; FALLBACK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
56 ; FALLBACK: $w0 = COPY [[ADDWrr]]
57 ; FALLBACK: RET_ReallyLR implicit $w0
58
59 %0:_(s32) = COPY $w0
60 %1:_(s32) = COPY $w1
61 %2:gpr(s32) = G_ADD %1, %0
62 $w0 = COPY %2(s32)
63 RET_ReallyLR implicit $w0
64 ...