llvm.org GIT mirror llvm / 8e5f2c6
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 12 years ago
37 changed file(s) with 633 addition(s) and 524 deletion(s). Raw diff Collapse all Expand all
2121
2222 MachineBasicBlock* SplitCriticalMachineEdge(MachineBasicBlock* src,
2323 MachineBasicBlock* dst) {
24 MachineFunction &MF = *src->getParent();
2425 const BasicBlock* srcBB = src->getBasicBlock();
2526
26 MachineBasicBlock* crit_mbb = new MachineBasicBlock(srcBB);
27 MachineBasicBlock* crit_mbb = MF.CreateMachineBasicBlock(srcBB);
2728
2829 // modify the llvm control flow graph
2930 src->removeSuccessor(dst);
3132 crit_mbb->addSuccessor(dst);
3233
3334 // insert the new block into the machine function.
34 src->getParent()->getBasicBlockList().insert(src->getParent()->end(),
35 crit_mbb);
35 MF.push_back(crit_mbb);
3636
3737 // insert a unconditional branch linking the new block to dst
38 const TargetMachine& TM = src->getParent()->getTarget();
38 const TargetMachine& TM = MF.getTarget();
3939 const TargetInstrInfo* TII = TM.getInstrInfo();
4040 std::vector emptyConditions;
4141 TII->InsertBranch(*crit_mbb, dst, (MachineBasicBlock*)0,
1515
1616 #include "llvm/CodeGen/MachineInstr.h"
1717 #include "llvm/ADT/GraphTraits.h"
18 #include "llvm/ADT/ilist.h"
1918 #include "llvm/Support/Streams.h"
2019
2120 namespace llvm {
2221 class MachineFunction;
2322
24 // ilist_traits
2523 template <>
26 struct ilist_traits<MachineInstr> {
24 struct alist_traitsMachineInstr> {
2725 protected:
28 // this is only set by the MachineBasicBlock owning the ilist
26 // this is only set by the MachineBasicBlock owning the LiveList
2927 friend class MachineBasicBlock;
30 MachineBasicBlock* parent;
28 MachineBasicBlock* Parent;
29
30 typedef alist_iterator iterator;
3131
3232 public:
33 ilist_traits() : parent(0) { }
34
35 static MachineInstr* getPrev(MachineInstr* N) { return N->Prev; }
36 static MachineInstr* getNext(MachineInstr* N) { return N->Next; }
37
38 static const MachineInstr*
39 getPrev(const MachineInstr* N) { return N->Prev; }
40
41 static const MachineInstr*
42 getNext(const MachineInstr* N) { return N->Next; }
43
44 static void setPrev(MachineInstr* N, MachineInstr* prev) { N->Prev = prev; }
45 static void setNext(MachineInstr* N, MachineInstr* next) { N->Next = next; }
46
47 static MachineInstr* createSentinel();
48 static void destroySentinel(MachineInstr *MI) { delete MI; }
33 alist_traits() : Parent(0) { }
34
4935 void addNodeToList(MachineInstr* N);
5036 void removeNodeFromList(MachineInstr* N);
51 void transferNodesFromList(
52 iplist >& toList,
53 ilist_iterator first,
54 ilist_iterator last);
37 void transferNodesFromList(alist_traits &, iterator, iterator);
38 void deleteNode(MachineInstr *N);
5539 };
5640
5741 class BasicBlock;
5842
5943 class MachineBasicBlock {
60 typedef ilist Instructions;
44 typedef alist Instructions;
6145 Instructions Insts;
62 MachineBasicBlock *Prev, *Next;
6346 const BasicBlock *BB;
6447 int Number;
6548 MachineFunction *xParent;
6649
67 void setParent(MachineFunction *P) { xParent = P; }
68
6950 /// Predecessors/Successors - Keep track of the predecessor / successor
7051 /// basicblocks.
7152 std::vector Predecessors;
8364 /// exception handler.
8465 bool IsLandingPad;
8566
67 explicit MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb);
68
69 ~MachineBasicBlock() {}
70
71 // MachineBasicBlocks are allocated and owned by MachineFunction.
72 friend class MachineFunction;
73
8674 public:
87 explicit MachineBasicBlock(const BasicBlock *bb = 0)
88 : Prev(0), Next(0), BB(bb), Number(-1), xParent(0),
89 Alignment(0), IsLandingPad(false) {
90 Insts.parent = this;
91 }
92
93 ~MachineBasicBlock();
94
9575 /// getBasicBlock - Return the LLVM basic block that this instance
9676 /// corresponded to originally.
9777 ///
10282 const MachineFunction *getParent() const { return xParent; }
10383 MachineFunction *getParent() { return xParent; }
10484
105 typedef ilist::iterator iterator;
106 typedef ilist::const_iterator const_iterator;
85 typedef Instructions::iterator iterator;
86 typedef Instructions::const_iterator const_iterator;
10787 typedef std::reverse_iterator const_reverse_iterator;
10888 typedef std::reverse_iterator reverse_iterator;
10989
271251 Insts.splice(where, Other->Insts, From, To);
272252 }
273253
254 /// removeFromParent - This method unlinks 'this' from the containing
255 /// function, and returns it, but does not delete it.
256 MachineBasicBlock *removeFromParent();
257
258 /// eraseFromParent - This method unlinks 'this' from the containing
259 /// function and deletes it.
260 void eraseFromParent();
261
274262 /// ReplaceUsesOfBlockWith - Given a machine basic block that branched to
275263 /// 'Old', change the code and CFG so that it branches to 'New' instead.
276264 void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New);
298286 void setNumber(int N) { Number = N; }
299287
300288 private: // Methods used to maintain doubly linked list of blocks...
301 friend struct ilist_traits;
302
303 MachineBasicBlock *getPrev() const { return Prev; }
304 MachineBasicBlock *getNext() const { return Next; }
305 void setPrev(MachineBasicBlock *P) { Prev = P; }
306 void setNext(MachineBasicBlock *N) { Next = N; }
289 friend struct alist_traits;
307290
308291 // Machine-CFG mutators
309292
1717 #ifndef LLVM_CODEGEN_MACHINEFUNCTION_H
1818 #define LLVM_CODEGEN_MACHINEFUNCTION_H
1919
20 #include "llvm/ADT/alist.h"
2021 #include "llvm/CodeGen/MachineBasicBlock.h"
2122 #include "llvm/Support/Annotation.h"
23 #include "llvm/Support/Allocator.h"
24 #include "llvm/Support/Recycler.h"
2225
2326 namespace llvm {
2427
2932 class MachineConstantPool;
3033 class MachineJumpTableInfo;
3134
32 // ilist_traits
3335 template <>
34 class ilist_traits {
35 // this is only set by the MachineFunction owning the ilist
36 friend class MachineFunction;
37 MachineFunction* Parent;
38
36 class alist_traits {
37 typedef alist_iterator iterator;
3938 public:
40 ilist_traits() : Parent(0) { }
41
42 static MachineBasicBlock* getPrev(MachineBasicBlock* N) { return N->Prev; }
43 static MachineBasicBlock* getNext(MachineBasicBlock* N) { return N->Next; }
44
45 static const MachineBasicBlock*
46 getPrev(const MachineBasicBlock* N) { return N->Prev; }
47
48 static const MachineBasicBlock*
49 getNext(const MachineBasicBlock* N) { return N->Next; }
50
51 static void setPrev(MachineBasicBlock* N, MachineBasicBlock* prev) {
52 N->Prev = prev;
53 }
54 static void setNext(MachineBasicBlock* N, MachineBasicBlock* next) {
55 N->Next = next;
56 }
57
58 static MachineBasicBlock* createSentinel();
59 static void destroySentinel(MachineBasicBlock *MBB) { delete MBB; }
60 void addNodeToList(MachineBasicBlock* N);
61 void removeNodeFromList(MachineBasicBlock* N);
62 void transferNodesFromList(iplist
63 ilist_traits > &toList,
64 ilist_iterator first,
65 ilist_iterator last);
39 void addNodeToList(MachineBasicBlock* MBB);
40 void removeNodeFromList(MachineBasicBlock* MBB);
41 void transferNodesFromList(alist_traits &,
42 iterator,
43 iterator) {}
44 void deleteNode(MachineBasicBlock *MBB);
6645 };
6746
6847 /// MachineFunctionInfo - This class can be derived from and used by targets to
7756 const Function *Fn;
7857 const TargetMachine &Target;
7958
80 // List of machine basic blocks in function
81 ilist BasicBlocks;
82
8359 // RegInfo - Information about each register in use in the function.
8460 MachineRegisterInfo *RegInfo;
8561
10177 // numbered and this vector keeps track of the mapping from ID's to MBB's.
10278 std::vector MBBNumbering;
10379
80 // Pool-allocate MachineFunction-lifetime and IR objects.
81 BumpPtrAllocator Allocator;
82
83 // Allocation management for instructions in function.
84 Recycler InstructionRecycler;
85
86 // Allocation management for basic blocks in function.
87 Recycler BasicBlockRecycler;
88
89 // Allocation management for memoperands in function.
90 Recycler MemOperandRecycler;
91
92 // List of machine basic blocks in function
93 typedef alist BasicBlockListType;
94 BasicBlockListType BasicBlocks;
95
10496 public:
10597 MachineFunction(const Function *Fn, const TargetMachine &TM);
10698 ~MachineFunction();
115107
116108 /// getRegInfo - Return information about the registers currently in use.
117109 ///
118 MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
110 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
111 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
119112
120113 /// getFrameInfo - Return the frame info object for the current function.
121114 /// This object contains information about objects allocated on the stack
122115 /// frame of the current function in an abstract way.
123116 ///
124 MachineFrameInfo *getFrameInfo() const { return FrameInfo; }
117 MachineFrameInfo *getFrameInfo() { return FrameInfo; }
118 const MachineFrameInfo *getFrameInfo() const { return FrameInfo; }
125119
126120 /// getJumpTableInfo - Return the jump table info object for the current
127121 /// function. This object contains information about jump tables for switch
128122 /// instructions in the current function.
129123 ///
130 MachineJumpTableInfo *getJumpTableInfo() const { return JumpTableInfo; }
124 MachineJumpTableInfo *getJumpTableInfo() { return JumpTableInfo; }
125 const MachineJumpTableInfo *getJumpTableInfo() const { return JumpTableInfo; }
131126
132127 /// getConstantPool - Return the constant pool object for the current
133128 /// function.
134129 ///
135 MachineConstantPool *getConstantPool() const { return ConstantPool; }
130 MachineConstantPool *getConstantPool() { return ConstantPool; }
131 const MachineConstantPool *getConstantPool() const { return ConstantPool; }
136132
137133 /// MachineFunctionInfo - Keep track of various per-function pieces of
138134 /// information for backends that would like to do so.
139135 ///
140136 template
141137 Ty *getInfo() {
142 if (!MFInfo) MFInfo = new Ty(*this);
138 if (!MFInfo) MFInfo = new (Allocator.Allocate()) Ty(*this);
143139
144140 assert((void*)dynamic_cast(MFInfo) == (void*)MFInfo &&
145141 "Invalid concrete type or multiple inheritence for getInfo");
214210 static MachineFunction& get(const Function *F);
215211
216212 // Provide accessors for the MachineBasicBlock list...
217 typedef ilist BasicBlockListType;
218213 typedef BasicBlockListType::iterator iterator;
219214 typedef BasicBlockListType::const_iterator const_iterator;
220215 typedef std::reverse_iterator const_reverse_iterator;
221216 typedef std::reverse_iterator reverse_iterator;
222217
223 // Provide accessors for basic blocks...
224 const BasicBlockListType &getBasicBlockList() const { return BasicBlocks; }
225 BasicBlockListType &getBasicBlockList() { return BasicBlocks; }
226
227218 //===--------------------------------------------------------------------===//
228 // BasicBlock iterator forwarding functions
219 // BasicBlock accessor functions.
229220 //
230221 iterator begin() { return BasicBlocks.begin(); }
231222 const_iterator begin() const { return BasicBlocks.begin(); }
244235 const MachineBasicBlock & back() const { return BasicBlocks.back(); }
245236 MachineBasicBlock & back() { return BasicBlocks.back(); }
246237
238 void push_back (MachineBasicBlock *MBB) { BasicBlocks.push_back (MBB); }
239 void push_front(MachineBasicBlock *MBB) { BasicBlocks.push_front(MBB); }
240 void insert(iterator MBBI, MachineBasicBlock *MBB) {
241 BasicBlocks.insert(MBBI, MBB);
242 }
243 void splice(iterator InsertPt, iterator MBBI) {
244 BasicBlocks.splice(InsertPt, BasicBlocks, MBBI);
245 }
246
247 void remove(iterator MBBI) {
248 BasicBlocks.remove(MBBI);
249 }
250 void erase(iterator MBBI) {
251 BasicBlocks.erase(MBBI);
252 }
253
247254 //===--------------------------------------------------------------------===//
248255 // Internal functions used to automatically number MachineBasicBlocks
249256 //
263270 assert(N < MBBNumbering.size() && "Illegal basic block #");
264271 MBBNumbering[N] = 0;
265272 }
273
274 /// CreateMachineInstr - Allocate a new MachineInstr. Use this instead
275 /// of `new MachineInstr'.
276 ///
277 MachineInstr *CreateMachineInstr(const TargetInstrDesc &TID,
278 bool NoImp = false);
279
280 /// CloneMachineInstr - Create a new MachineInstr which is a copy of the
281 /// 'Orig' instruction, identical in all ways except the the instruction
282 /// has no parent, prev, or next.
283 ///
284 MachineInstr *CloneMachineInstr(const MachineInstr *Orig);
285
286 /// DeleteMachineInstr - Delete the given MachineInstr.
287 ///
288 void DeleteMachineInstr(MachineInstr *MI);
289
290 /// CreateMachineBasicBlock - Allocate a new MachineBasicBlock. Use this
291 /// instead of `new MachineBasicBlock'.
292 ///
293 MachineBasicBlock *CreateMachineBasicBlock(const BasicBlock *bb = 0);
294
295 /// DeleteMachineBasicBlock - Delete the given MachineBasicBlock.
296 ///
297 void DeleteMachineBasicBlock(MachineBasicBlock *MBB);
298
299 /// CreateMachineMemOperand - Allocate a new MachineMemOperand. Use this
300 /// instead of `new MachineMemOperand'.
301 ///
302 MachineMemOperand *CreateMachineMemOperand(const MachineMemOperand &MMO);
303
304 /// DeleteMachineMemOperand - Delete the given MachineMemOperand.
305 ///
306 void DeleteMachineMemOperand(MachineMemOperand *MMO);
266307 };
267308
268309 //===--------------------------------------------------------------------===//
1515 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
1616 #define LLVM_CODEGEN_MACHINEINSTR_H
1717
18 #include "llvm/ADT/alist.h"
1819 #include "llvm/CodeGen/MachineOperand.h"
1920 #include "llvm/CodeGen/MachineMemOperand.h"
2021 #include
2425 class TargetInstrDesc;
2526 class TargetInstrInfo;
2627 class TargetRegisterInfo;
27
28 template struct ilist_traits;
29 template struct ilist;
28 class MachineFunction;
3029
3130 //===----------------------------------------------------------------------===//
3231 /// MachineInstr - Representation of each machine instruction.
3736 // are determined at construction time).
3837
3938 std::vector Operands; // the operands
40 std::vector MemOperands;// information on memory references
41 MachineInstr *Prev, *Next; // Links for MBB's intrusive list.
39 alist MemOperands; // information on memory references
4240 MachineBasicBlock *Parent; // Pointer to the owning basic block.
4341
4442 // OperandComplete - Return true if it's illegal to add a new operand
4543 bool OperandsComplete() const;
4644
47 MachineInstr(const MachineInstr&);
45 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
4846 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
4947
5048 // Intrusive list support
51 friend struct ilist_traits;
52 friend struct ilist_traits>;
49 friend struct alist_traits>;
50 friend struct alist_traits;
5351 void setParent(MachineBasicBlock *P) { Parent = P; }
54 public:
52
53 /// MachineInstr ctor - This constructor creates a copy of the given
54 /// MachineInstr in the given MachineFunction.
55 MachineInstr(MachineFunction &, const MachineInstr &);
56
5557 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
5658 /// TID NULL and no operands.
5759 MachineInstr();
6971
7072 ~MachineInstr();
7173
74 // MachineInstrs are pool-allocated and owned by MachineFunction.
75 friend class MachineFunction;
76
77 public:
7278 const MachineBasicBlock* getParent() const { return Parent; }
7379 MachineBasicBlock* getParent() { return Parent; }
7480
98104 unsigned getNumExplicitOperands() const;
99105
100106 /// Access to memory operands of the instruction
101 unsigned getNumMemOperands() const { return (unsigned)MemOperands.size(); }
102
103 const MachineMemOperand& getMemOperand(unsigned i) const {
104 assert(i < getNumMemOperands() && "getMemOperand() out of range!");
105 return MemOperands[i];
106 }
107 MachineMemOperand& getMemOperand(unsigned i) {
108 assert(i < getNumMemOperands() && "getMemOperand() out of range!");
109 return MemOperands[i];
110 }
107 alist::iterator memoperands_begin()
108 { return MemOperands.begin(); }
109 alist::iterator memoperands_end()
110 { return MemOperands.end(); }
111 alist::const_iterator memoperands_begin() const
112 { return MemOperands.begin(); }
113 alist::const_iterator memoperands_end() const
114 { return MemOperands.end(); }
115 bool memoperands_empty() const { return MemOperands.empty(); }
111116
112117 /// isIdenticalTo - Return true if this instruction is identical to (same
113118 /// opcode and same operands as) the specified instruction.
121126 return true;
122127 }
123128
124 /// clone - Create a copy of 'this' instruction that is identical in
125 /// all ways except the the instruction has no parent, prev, or next.
126 MachineInstr* clone() const { return new MachineInstr(*this); }
127
128129 /// removeFromParent - This method unlinks 'this' from the containing basic
129130 /// block, and returns it, but does not delete it.
130131 MachineInstr *removeFromParent();
131132
132133 /// eraseFromParent - This method unlinks 'this' from the containing basic
133134 /// block and deletes it.
134 void eraseFromParent() {
135 delete removeFromParent();
136 }
135 void eraseFromParent();
137136
138137 /// isLabel - Returns true if the MachineInstr represents a label.
139138 ///
269268
270269 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
271270 /// referencing arbitrary storage.
272 void addMemOperand(const MachineMemOperand &MO) {
273 MemOperands.push_back(MO);
274 }
271 void addMemOperand(MachineFunction &MF,
272 const MachineMemOperand &MO);
273
274 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
275 void clearMemOperands(MachineFunction &MF);
275276
276277 private:
277278 /// getRegInfo - If this instruction is embedded into a MachineFunction,
8282 MI->addOperand(MachineOperand::CreateES(FnName, 0));
8383 return *this;
8484 }
85
86 /// addMemOperand - Add a memory operand to the machine instruction.
87 const MachineInstrBuilder &addMemOperand(const MachineMemOperand &MO) const {
88 MI->addMemOperand(MO);
89 return *this;
90 }
9185 };
9286
9387 /// BuildMI - Builder interface. Specify how to create the initial instruction
9488 /// itself.
9589 ///
96 inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID) {
97 return MachineInstrBuilder(new MachineInstr(TID));
90 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
91 const TargetInstrDesc &TID) {
92 return MachineInstrBuilder(MF.CreateMachineInstr(TID));
9893 }
9994
10095 /// BuildMI - This version of the builder sets up the first operand as a
10196 /// destination virtual register.
10297 ///
103 inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID,
98 inline MachineInstrBuilder BuildMI(MachineFunction &MF,
99 const TargetInstrDesc &TID,
104100 unsigned DestReg) {
105 return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
101 return MachineInstrBuilder(MF.CreateMachineInstr(TID)).addReg(DestReg, true);
106102 }
107103
108104 /// BuildMI - This version of the builder inserts the newly-built
113109 MachineBasicBlock::iterator I,
114110 const TargetInstrDesc &TID,
115111 unsigned DestReg) {
116 MachineInstr *MI = new MachineInstr(TID);
112 MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID);
117113 BB.insert(I, MI);
118114 return MachineInstrBuilder(MI).addReg(DestReg, true);
119115 }
125121 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
126122 MachineBasicBlock::iterator I,
127123 const TargetInstrDesc &TID) {
128 MachineInstr *MI = new MachineInstr(TID);
124 MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID);
129125 BB.insert(I, MI);
130126 return MachineInstrBuilder(MI);
131127 }
126126 }
127127
128128 // Remove the block.
129 MF->getBasicBlockList().erase(MBB);
129 MF->erase(MBB);
130130 }
131131
132132 /// OptimizeImpDefsBlock - If a basic block is just a bunch of implicit_def
374374 /// iterator. This returns the new MBB.
375375 MachineBasicBlock *BranchFolder::SplitMBBAt(MachineBasicBlock &CurMBB,
376376 MachineBasicBlock::iterator BBI1) {
377 MachineFunction &MF = *CurMBB.getParent();
378
377379 // Create the fall-through block.
378380 MachineFunction::iterator MBBI = &CurMBB;
379 MachineBasicBlock *NewMBB = new MachineBasicBlock(CurMBB.getBasicBlock());
380 CurMBB.getParent()->getBasicBlockList().insert(++MBBI, NewMBB);
381 MachineBasicBlock *NewMBB =MF.CreateMachineBasicBlock(CurMBB.getBasicBlock());
382 CurMBB.getParent()->insert(++MBBI, NewMBB);
381383
382384 // Move all the successors of this block to the specified block.
383385 NewMBB->transferSuccessors(&CurMBB);
11331133 void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
11341134 std::vector &Cond,
11351135 bool IgnoreBr) {
1136 MachineFunction &MF = *ToBBI.BB->getParent();
1137
11361138 for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
11371139 E = FromBBI.BB->end(); I != E; ++I) {
11381140 const TargetInstrDesc &TID = I->getDesc();
11411143 if (IgnoreBr && !isPredicated && TID.isBranch())
11421144 break;
11431145
1144 MachineInstr *MI = I->clone();
1146 MachineInstr *MI = MF.CloneMachineInstr(I);
11451147 ToBBI.BB->insert(ToBBI.BB->end(), MI);
11461148 ToBBI.NonPredSize++;
11471149
7272 // Release VNInfo memroy regions after all VNInfo objects are dtor'd.
7373 VNInfoAllocator.Reset();
7474 for (unsigned i = 0, e = ClonedMIs.size(); i != e; ++i)
75 delete ClonedMIs[i];
75 mf_->DeleteMachineInstr(ClonedMIs[i]);
7676 }
7777
7878 void LiveIntervals::computeNumbering() {
15611561 ReMatOrigDefs[VN] = ReMatDefMI;
15621562 // Original def may be modified so we have to make a copy here. vrm must
15631563 // delete these!
1564 ReMatDefs[VN] = ReMatDefMI = ReMatDefMI->clone();
1564 ReMatDefs[VN] = ReMatDefMI = mf_->CloneMachineInstr(ReMatDefMI);
15651565
15661566 bool CanDelete = true;
15671567 if (VNI->hasPHIKill) {
1717 #include "llvm/Target/TargetData.h"
1818 #include "llvm/Target/TargetInstrDesc.h"
1919 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Support/LeakDetector.h"
2120 #include
2221 using namespace llvm;
2322
24 MachineBasicBlock::~MachineBasicBlock() {
25 LeakDetector::removeGarbageObject(this);
23 MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
24 : BB(bb), Number(-1), xParent(&mf), Alignment(0), IsLandingPad(false) {
25 Insts.getTraits().Parent = this;
2626 }
2727
2828 std::ostream& llvm::operator<<(std::ostream &OS, const MachineBasicBlock &MBB) {
3737 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
3838 /// gets the next available unique MBB number. If it is removed from a
3939 /// MachineFunction, it goes back to being #-1.
40 void ilist_traits::addNodeToList(MachineBasicBlock* N) {
41 assert(N->getParent() == 0 && "machine instruction already in a basic block");
42 N->setParent(Parent);
43 N->Number = Parent->addToMBBNumbering(N);
40 void alist_traits::addNodeToList(MachineBasicBlock* N) {
41 MachineFunction &MF = *N->getParent();
42 N->Number = MF.addToMBBNumbering(N);
4443
4544 // Make sure the instructions have their operands in the reginfo lists.
46 MachineRegisterInfo &RegInfo = Parent->getRegInfo();
45 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4746 for (MachineBasicBlock::iterator I = N->begin(), E = N->end(); I != E; ++I)
4847 I->AddRegOperandsToUseLists(RegInfo);
49
50 LeakDetector::removeGarbageObject(N);
51 }
52
53 void ilist_traits::removeNodeFromList(MachineBasicBlock* N) {
54 assert(N->getParent() != 0 && "machine instruction not in a basic block");
48 }
49
50 void alist_traits::removeNodeFromList(MachineBasicBlock* N) {
5551 N->getParent()->removeFromMBBNumbering(N->Number);
5652 N->Number = -1;
57 N->setParent(0);
58
59 // Make sure the instructions have their operands removed from the reginfo
60 // lists.
61 for (MachineBasicBlock::iterator I = N->begin(), E = N->end(); I != E; ++I)
62 I->RemoveRegOperandsFromUseLists();
63
64 LeakDetector::addGarbageObject(N);
65 }
66
67
68 MachineInstr* ilist_traits::createSentinel() {
69 MachineInstr* dummy = new MachineInstr();
70 LeakDetector::removeGarbageObject(dummy);
71 return dummy;
72 }
53 }
54
7355
7456 /// addNodeToList (MI) - When we add an instruction to a basic block
7557 /// list, we update its parent pointer and add its operands from reg use/def
7658 /// lists if appropriate.
77 void ilist_traits::addNodeToList(MachineInstr* N) {
59 void alist_traits::addNodeToList(MachineInstr* N) {
7860 assert(N->getParent() == 0 && "machine instruction already in a basic block");
79 N->setParent(parent);
80 LeakDetector::removeGarbageObject(N);
81
82 // If the block is in a function, add the instruction's register operands to
83 // their corresponding use/def lists.
84 if (MachineFunction *MF = parent->getParent())
85 N->AddRegOperandsToUseLists(MF->getRegInfo());
61 N->setParent(Parent);
62
63 // Add the instruction's register operands to their corresponding
64 // use/def lists.
65 MachineFunction *MF = Parent->getParent();
66 N->AddRegOperandsToUseLists(MF->getRegInfo());
8667 }
8768
8869 /// removeNodeFromList (MI) - When we remove an instruction from a basic block
8970 /// list, we update its parent pointer and remove its operands from reg use/def
9071 /// lists if appropriate.
91 void ilist_traits::removeNodeFromList(MachineInstr* N) {
72 void alist_traits::removeNodeFromList(MachineInstr* N) {
9273 assert(N->getParent() != 0 && "machine instruction not in a basic block");
93 // If this block is in a function, remove from the use/def lists.
94 if (parent->getParent() != 0)
95 N->RemoveRegOperandsFromUseLists();
74
75 // Remove from the use/def lists.
76 N->RemoveRegOperandsFromUseLists();
9677
9778 N->setParent(0);
98 LeakDetector::addGarbageObject(N);
9979 }
10080
10181 /// transferNodesFromList (MI) - When moving a range of instructions from one
10282 /// MBB list to another, we need to update the parent pointers and the use/def
10383 /// lists.
104 void ilist_traits::transferNodesFromList(
105 iplist >& fromList,
106 ilist_iterator first,
107 ilist_iterator last) {
84 void alist_traits::transferNodesFromList(
85 alist_traits& fromList,
86 MachineBasicBlock::iterator first,
87 MachineBasicBlock::iterator last) {
10888 // Splice within the same MBB -> no change.
109 if (parent == fromList.parent) return;
89 if (Parent == fromList.Parent) return;
11090
11191 // If splicing between two blocks within the same function, just update the
11292 // parent pointers.
113 if (parent->getParent() == fromList.parent->getParent()) {
93 if (Parent->getParent() == fromList.Parent->getParent()) {
11494 for (; first != last; ++first)
115 first->setParent(parent);
95 first->setParent(Parent);
11696 return;
11797 }
11898
11999 // Otherwise, we have to update the parent and the use/def lists. The common
120100 // case when this occurs is if we're splicing from a block in a MF to a block
121101 // that is not in an MF.
122 bool HasOldMF = fromList.parent->getParent() != 0;
123 MachineFunction *NewMF = parent->getParent();
102 bool HasOldMF = fromList.Parent->getParent() != 0;
103 MachineFunction *NewMF = Parent->getParent();
124104
125105 for (; first != last; ++first) {
126106 if (HasOldMF) first->RemoveRegOperandsFromUseLists();
127 first->setParent(parent);
107 first->setParent(Parent);
128108 if (NewMF) first->AddRegOperandsToUseLists(NewMF->getRegInfo());
129109 }
110 }
111
112 void alist_traits::deleteNode(MachineInstr* MI) {
113 assert(!MI->getParent() && "MI is still in a block!");
114 Parent->getParent()->DeleteMachineInstr(MI);
130115 }
131116
132117 MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
210195 }
211196
212197 void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
213 MachineFunction::BasicBlockListType &BBList =getParent()->getBasicBlockList();
214 getParent()->getBasicBlockList().splice(NewAfter, BBList, this);
198 getParent()->splice(NewAfter, this);
215199 }
216200
217201 void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
218 MachineFunction::BasicBlockListType &BBList =getParent()->getBasicBlockList();
219202 MachineFunction::iterator BBI = NewBefore;
220 getParent()->getBasicBlockList().splice(++BBI, BBList, this);
203 getParent()->splice(++BBI, this);
221204 }
222205
223206
269252 std::find(Successors.begin(), Successors.end(), MBB);
270253 return I != Successors.end();
271254 }
255
256 /// removeFromParent - This method unlinks 'this' from the containing function,
257 /// and returns it, but does not delete it.
258 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
259 assert(getParent() && "Not embedded in a function!");
260 getParent()->remove(this);
261 return this;
262 }
263
264
265 /// eraseFromParent - This method unlinks 'this' from the containing function,
266 /// and deletes it.
267 void MachineBasicBlock::eraseFromParent() {
268 assert(getParent() && "Not embedded in a function!");
269 getParent()->erase(this);
270 }
271
272272
273273 /// ReplaceUsesOfBlockWith - Given a machine basic block that branched to
274274 /// 'Old', change the code and CFG so that it branches to 'New' instead.
308308 bool MadeChange = false;
309309 bool AddedFallThrough = false;
310310
311 MachineBasicBlock *FallThru = getNext();
311 MachineFunction::iterator FallThru = next(MachineFunction::iterator(this));
312312
313313 // If this block ends with a conditional branch that falls through to its
314314 // successor, set DestB as the successor.
2828 #include "llvm/Instructions.h"
2929 #include "llvm/Support/Compiler.h"
3030 #include "llvm/Support/GraphWriter.h"
31 #include "llvm/Support/LeakDetector.h"
3231 #include "llvm/ADT/STLExtras.h"
3332 #include "llvm/Config/config.h"
3433 #include
103102 // MachineFunction implementation
104103 //===---------------------------------------------------------------------===//
105104
106 MachineBasicBlock* ilist_traits::createSentinel() {
107 MachineBasicBlock* dummy = new MachineBasicBlock();
108 LeakDetector::removeGarbageObject(dummy);
109 return dummy;
110 }
111
112 void ilist_traits::transferNodesFromList(
113 iplist >& toList,
114 ilist_iterator first,
115 ilist_iterator last) {
116 // If splicing withing the same function, no change.
117 if (Parent == toList.Parent) return;
118
119 for (; first != last; ++first)
120 first->setParent(toList.Parent);
105 void alist_traits::deleteNode(MachineBasicBlock *MBB) {
106 MBB->getParent()->DeleteMachineBasicBlock(MBB);
121107 }
122108
123109 MachineFunction::MachineFunction(const Function *F,
124110 const TargetMachine &TM)
125111 : Annotation(MF_AID), Fn(F), Target(TM) {
126 RegInfo = new MachineRegisterInfo(*TM.getRegisterInfo());
112 RegInfo = new (Allocator.Allocate())
113 MachineRegisterInfo(*TM.getRegisterInfo());
127114 MFInfo = 0;
128 FrameInfo = new MachineFrameInfo(*TM.getFrameInfo());
129 ConstantPool = new MachineConstantPool(TM.getTargetData());
115 FrameInfo = new (Allocator.Allocate())
116 MachineFrameInfo(*TM.getFrameInfo());
117 ConstantPool = new (Allocator.Allocate())
118 MachineConstantPool(TM.getTargetData());
130119
131120 // Set up jump table.
132121 const TargetData &TD = *TM.getTargetData();
134123 unsigned EntrySize = IsPic ? 4 : TD.getPointerSize();
135124 unsigned Alignment = IsPic ? TD.getABITypeAlignment(Type::Int32Ty)
136125 : TD.getPointerABIAlignment();
137 JumpTableInfo = new MachineJumpTableInfo(EntrySize, Alignment);
138
139 BasicBlocks.Parent = this;
126 JumpTableInfo = new (Allocator.Allocate())
127 MachineJumpTableInfo(EntrySize, Alignment);
140128 }
141129
142130 MachineFunction::~MachineFunction() {
143131 BasicBlocks.clear();
144 delete RegInfo;
145 delete MFInfo;
146 delete FrameInfo;
147 delete ConstantPool;
148 delete JumpTableInfo;
132 InstructionRecycler.clear(Allocator);
133 BasicBlockRecycler.clear(Allocator);
134 MemOperandRecycler.clear(Allocator);
135 RegInfo->~MachineRegisterInfo(); Allocator.Deallocate(RegInfo);
136 if (MFInfo) {
137 MFInfo->~MachineFunctionInfo(); Allocator.Deallocate(MFInfo);
138 }
139 FrameInfo->~MachineFrameInfo(); Allocator.Deallocate(FrameInfo);
140 ConstantPool->~MachineConstantPool(); Allocator.Deallocate(ConstantPool);
141 JumpTableInfo->~MachineJumpTableInfo(); Allocator.Deallocate(JumpTableInfo);
149142 }
150143
151144
191184 MBBNumbering.resize(BlockNo);
192185 }
193186
194
195 void MachineFunction::dump() const { print(*cerr.stream()); }
187 /// CreateMachineInstr - Allocate a new MachineInstr. Use this instead
188 /// of `new MachineInstr'.
189 ///
190 MachineInstr *
191 MachineFunction::CreateMachineInstr(const TargetInstrDesc &TID, bool NoImp) {
192 return new (InstructionRecycler.Allocate(Allocator))
193 MachineInstr(TID, NoImp);
194 }
195
196 /// CloneMachineInstr - Create a new MachineInstr which is a copy of the
197 /// 'Orig' instruction, identical in all ways except the the instruction
198 /// has no parent, prev, or next.
199 ///
200 MachineInstr *
201 MachineFunction::CloneMachineInstr(const MachineInstr *Orig) {
202 return new (InstructionRecycler.Allocate(Allocator))
203 MachineInstr(*this, *Orig);
204 }
205
206 /// DeleteMachineInstr - Delete the given MachineInstr.
207 ///
208 void
209 MachineFunction::DeleteMachineInstr(MachineInstr *MI) {
210 // Clear the instructions memoperands. This must be done manually because
211 // the instruction's parent pointer is now null, so it can't properly
212 // deallocate them on its own.
213 MI->clearMemOperands(*this);
214
215 MI->~MachineInstr();
216 InstructionRecycler.Deallocate(Allocator, MI);
217 }
218
219 /// CreateMachineBasicBlock - Allocate a new MachineBasicBlock. Use this
220 /// instead of `new MachineBasicBlock'.
221 ///
222 MachineBasicBlock *
223 MachineFunction::CreateMachineBasicBlock(const BasicBlock *bb) {
224 return new (BasicBlockRecycler.Allocate(Allocator))
225 MachineBasicBlock(*this, bb);
226 }
227
228 /// DeleteMachineBasicBlock - Delete the given MachineBasicBlock.
229 ///
230 void
231 MachineFunction::DeleteMachineBasicBlock(MachineBasicBlock *MBB) {
232 assert(MBB->getParent() == this && "MBB parent mismatch!");
233 MBB->~MachineBasicBlock();
234 BasicBlockRecycler.Deallocate(Allocator, MBB);
235 }
236
237 /// CreateMachineMemOperand - Allocate a new MachineMemOperand. Use this
238 /// instead of `new MachineMemOperand'.
239 ///
240 MachineMemOperand *
241 MachineFunction::CreateMachineMemOperand(const MachineMemOperand &MMO) {
242 return new (MemOperandRecycler.Allocate(Allocator))
243 MachineMemOperand(MMO);
244 }
245
246 /// DeleteMachineMemOperand - Delete the given MachineMemOperand.
247 ///
248 void
249 MachineFunction::DeleteMachineMemOperand(MachineMemOperand *MO) {
250 MO->~MachineMemOperand();
251 MemOperandRecycler.Deallocate(Allocator, MO);
252 }
253
254 void MachineFunction::dump() const {
255 print(*cerr.stream());
256 }
196257
197258 void MachineFunction::print(std::ostream &OS) const {
198259 OS << "# Machine code for " << Fn->getName () << "():\n";
199260
200261 // Print Frame Information
201 getFrameInfo()->print(*this, OS);
262 FrameInfo->print(*this, OS);
202263
203264 // Print JumpTable Information
204 getJumpTableInfo()->print(OS);
265 JumpTableInfo->print(OS);
205266
206267 // Print Constant Pool
207 getConstantPool()->print(OS);
268 ConstantPool->print(OS);
208269
209270 const TargetRegisterInfo *TRI = getTarget().getRegisterInfo();
210271
2121 #include "llvm/Target/TargetInstrInfo.h"
2222 #include "llvm/Target/TargetInstrDesc.h"
2323 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/Support/LeakDetector.h"
2524 #include "llvm/Support/MathExtras.h"
2625 #include "llvm/Support/Streams.h"
2726 #include
256255 /// TID NULL and no operands.
257256 MachineInstr::MachineInstr()
258257 : TID(0), NumImplicitOps(0), Parent(0) {
259 // Make sure that we get added to a machine basicblock
260 LeakDetector::addGarbageObject(this);
261258 }
262259
263260 void MachineInstr::addImplicitDefUseOperands() {
284281 Operands.reserve(NumImplicitOps + TID->getNumOperands());
285282 if (!NoImp)
286283 addImplicitDefUseOperands();
287 // Make sure that we get added to a machine basicblock
288 LeakDetector::addGarbageObject(this);
289284 }
290285
291286 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
303298 NumImplicitOps++;
304299 Operands.reserve(NumImplicitOps + TID->getNumOperands());
305300 addImplicitDefUseOperands();
306 // Make sure that we get added to a machine basicblock
307 LeakDetector::addGarbageObject(this);
308301 MBB->push_back(this); // Add instruction to end of basic block!
309302 }
310303
311304 /// MachineInstr ctor - Copies MachineInstr arg exactly
312305 ///
313 MachineInstr::MachineInstr(const MachineInstr &MI) {
306 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) {
314307 TID = &MI.getDesc();
315308 NumImplicitOps = MI.NumImplicitOps;
316309 Operands.reserve(MI.getNumOperands());
317 MemOperands = MI.MemOperands;
318310
319311 // Add operands
320312 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
322314 Operands.back().ParentMI = this;
323315 }
324316
325 // Set parent, next, and prev to null
317 // Add memory operands.
318 for (alist::const_iterator i = MI.memoperands_begin(),
319 j = MI.memoperands_end(); i != j; ++i)
320 addMemOperand(MF, *i);
321
322 // Set parent to null.
326323 Parent = 0;
327 Prev = 0;
328 Next = 0;
329 }
330
324 }
331325
332326 MachineInstr::~MachineInstr() {
333 LeakDetector::removeGarbageObject(this);
327 assert(MemOperands.empty() &&
328 "MachineInstr being deleted with live memoperands!");
334329 #ifndef NDEBUG
335330 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
336331 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
498493 }
499494 }
500495
496 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
497 /// referencing arbitrary storage.
498 void MachineInstr::addMemOperand(MachineFunction &MF,
499 const MachineMemOperand &MO) {
500 MemOperands.push_back(MF.CreateMachineMemOperand(MO));
501 }
502
503 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
504 void MachineInstr::clearMemOperands(MachineFunction &MF) {
505 while (!MemOperands.empty())
506 MF.DeleteMachineMemOperand(MemOperands.remove(MemOperands.begin()));
507 }
508
501509
502510 /// removeFromParent - This method unlinks 'this' from the containing basic
503511 /// block, and returns it, but does not delete it.
505513 assert(getParent() && "Not embedded in a basic block!");
506514 getParent()->remove(this);
507515 return this;
516 }
517
518
519 /// eraseFromParent - This method unlinks 'this' from the containing basic
520 /// block, and deletes it.
521 void MachineInstr::eraseFromParent() {
522 assert(getParent() && "Not embedded in a basic block!");
523 getParent()->erase(this);
508524 }
509525
510526
709725 getOperand(i).print(OS, TM);
710726 }
711727
712 if (getNumMemOperands() > 0) {
728 if (!memoperands_empty()) {
713729 OS << ", Mem:";
714 for (unsigned i = 0; i < getNumMemOperands(); i++) {
715 const MachineMemOperand &MRO = getMemOperand(i);
730 for (alist::const_iterator i = memoperands_begin(),
731 e = memoperands_end(); i != e; ++i) {
732 const MachineMemOperand &MRO = *i;
716733 const Value *V = MRO.getValue();
717734
718735 assert((MRO.isLoad() || MRO.isStore()) &&
353353 }
354354
355355 // Really delete the PHI instruction now!
356 delete MPhi;
356 MF.DeleteMachineInstr(MPhi);
357357 ++NumAtomic;
358358 }
359359
669669 }
670670
671671 void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
672 MI->addMemOperand(MO);
672 MI->addMemOperand(*MF, MO);
673673 }
674674
675675 /// getSubRegisterRegClass - Returns the register class of specified register
725725 unsigned SubIdx = cast(Node->getOperand(1))->getValue();
726726
727727 // Create the extract_subreg machine instruction.
728 MachineInstr *MI = BuildMI(TII->get(TargetInstrInfo::EXTRACT_SUBREG));
728 MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
729729
730730 // Figure out the register class to create for the destreg.
731731 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
771771 }
772772
773773 // Create the insert_subreg or subreg_to_reg machine instruction.
774 MachineInstr *MI = BuildMI(TII->get(Opc));
774 MachineInstr *MI = BuildMI(*MF, TII->get(Opc));
775775 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
776776
777777 // If creating a subreg_to_reg, then the first input operand
828828 #endif
829829
830830 // Create the new machine instruction.
831 MachineInstr *MI = BuildMI(II);
831 MachineInstr *MI = BuildMI(*MF, II);
832832
833833 // Add result register values for things that are defined by this
834834 // instruction.
852852 else {
853853 DOUT << "Sched: COMMUTED TO: " << *NewMI;
854854 if (MI != NewMI) {
855 delete MI;
855 MF->DeleteMachineInstr(MI);
856856 MI = NewMI;
857857 }
858858 ++NumCommutes;
927927 --NumOps; // Ignore the flag operand.
928928
929929 // Create the inline asm machine instruction.
930 MachineInstr *MI = BuildMI(TII->get(TargetInstrInfo::INLINEASM));
930 MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::INLINEASM));
931931
932932 // Add the asm string as an external symbol operand.
933933 const char *AsmStr =
3939 // Create a new instruction.
4040 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
4141 bool Reg0IsDead = MI->getOperand(0).isDead();
42 return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead)
42 MachineFunction &MF = *MI->getParent()->getParent();
43 return BuildMI(MF, MI->getDesc())
44 .addReg(Reg0, true, false, false, Reg0IsDead)
4345 .addReg(Reg2, false, false, Reg2IsKill)
4446 .addReg(Reg1, false, false, Reg1IsKill);
4547 }
103105 MachineBasicBlock::iterator I,
104106 unsigned DestReg,
105107 const MachineInstr *Orig) const {
106 MachineInstr *MI = Orig->clone();
108 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
107109 MI->getOperand(0).setReg(DestReg);
108110 MBB.insert(I, MI);
109111 }
603603 return false;
604604
605605 bool FoundUse = false, Done = false;
606 MachineBasicBlock::iterator E = NewDef;
606 MachineBasicBlock::iterator E = &NewDef;
607607 ++I; ++E;
608608 for (; !Done && I != E; ++I) {
609609 MachineInstr *NMI = I;
972972 MBB.erase(&MI);
973973 return true;
974974 }
975 delete NewMI;
975 MF.DeleteMachineInstr(NewMI);
976976 }
977977 }
978978 return false;
10311031 SmallVector Ops;
10321032 Ops.push_back(NewDstIdx);
10331033 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS);
1034 delete CommutedMI; // Not needed since foldMemoryOperand returns new MI.
1034 // Not needed since foldMemoryOperand returns new MI.
1035 MF.DeleteMachineInstr(CommutedMI);
10351036 if (!FoldedMI)
10361037 return false;
10371038
10391040 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
10401041 // Insert new def MI and spill MI.
10411042 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
1042 TII->storeRegToStackSlot(MBB, MI, NewReg, true, SS, RC);
1043 TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC);
10431044 MII = prior(MII);
10441045 MachineInstr *StoreMI = MII;
10451046 VRM.addSpillSlotUse(SS, StoreMI);
13401341 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
13411342 MI.getOperand(i).setReg(RReg);
13421343 if (VRM.isImplicitlyDefined(VirtReg))
1343 BuildMI(MBB, MI, TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg);
1344 BuildMI(MBB, &MI, TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg);
13441345 continue;
13451346 }
13461347
18131814 ProcessNextInst:
18141815 DistanceMap.insert(std::make_pair(&MI, Dist++));
18151816 if (!Erased && !BackTracked) {
1816 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
1817 for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II)
18171818 UpdateKills(*II, RegKills, KillOps);
18181819 }
18191820 MII = NextMII;
287287 void ARMConstantIslands::DoInitialPlacement(MachineFunction &Fn,
288288 std::vector &CPEMIs){
289289 // Create the basic block to hold the CPE's.
290 MachineBasicBlock *BB = new MachineBasicBlock();
291 Fn.getBasicBlockList().push_back(BB);
290 MachineBasicBlock *BB = Fn.CreateMachineBasicBlock();
291 Fn.push_back(BB);
292292
293293 // Add all of the constants from the constant pool to the end block, use an
294294 // identity mapping of CPI's to CPE's.
557557 /// account for this change and returns the newly created block.
558558 MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) {
559559 MachineBasicBlock *OrigBB = MI->getParent();
560 MachineFunction &MF = *OrigBB->getParent();
560561
561562 // Create a new MBB for the code after the OrigBB.
562 MachineBasicBlock *NewBB = new MachineBasicBlock(OrigBB->getBasicBlock());
563 MachineBasicBlock *NewBB = MF.CreateMachineBasicBlock(OrigBB->getBasicBlock());
563564 MachineFunction::iterator MBBI = OrigBB; ++MBBI;
564 OrigBB->getParent()->getBasicBlockList().insert(MBBI, NewBB);
565 MF.insert(MBBI, NewBB);
565566
566567 // Splice the instructions starting with MI over to NewBB.
567568 NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
589590 // Update internal data structures to account for the newly inserted MBB.
590591 // This is almost the same as UpdateForInsertedWaterBlock, except that
591592 // the Water goes after OrigBB, not NewBB.
592 NewBB->getParent()->RenumberBlocks(NewBB);
593 MF.RenumberBlocks(NewBB);
593594
594595 // Insert a size into BBSizes to align it properly with the (newly
595596 // renumbered) block numbers.
10301031 }
10311032
10321033 // Okay, we know we can put an island before NewMBB now, do it!
1033 MachineBasicBlock *NewIsland = new MachineBasicBlock();
1034 Fn.getBasicBlockList().insert(NewMBB, NewIsland);
1034 MachineBasicBlock *NewIsland = Fn.CreateMachineBasicBlock();
1035 Fn.insert(NewMBB, NewIsland);
10351036
10361037 // Update internal data structures to account for the newly inserted MBB.
10371038 UpdateForInsertedWaterBlock(NewIsland);
12001201
12011202 NumCBrFixed++;
12021203 if (BMI != MI) {
1203 if (next(MachineBasicBlock::iterator(MI)) == MBB->back() &&
1204 if (next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
12041205 BMI->getOpcode() == Br.UncondBr) {
12051206 // Last MI in the BB is a unconditional branch. Can we simply invert the
12061207 // condition and swap destinations:
14451445 // destination vreg to set, the condition code register to branch on, the
14461446 // true/false values to select between, and a branch opcode to use.
14471447 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1448 ilist::iterator It = BB;
1448 MachineFunction::iterator It = BB;
14491449 ++It;
14501450
14511451 // thisMBB:
14551455 // bCC copy1MBB
14561456 // fallthrough --> copy0MBB
14571457 MachineBasicBlock *thisMBB = BB;
1458 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1459 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1458 MachineFunction *F = BB->getParent();
1459 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1460 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
14601461 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
14611462 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1462 MachineFunction *F = BB->getParent();
1463 F->getBasicBlockList().insert(It, copy0MBB);
1464 F->getBasicBlockList().insert(It, sinkMBB);
1463 F->insert(It, copy0MBB);
1464 F->insert(It, sinkMBB);
14651465 // Update machine-CFG edges by first adding all successors of the current
14661466 // block to the new block which will contain the Phi node for the select.
14671467 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
14901490 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
14911491 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
14921492
1493 delete MI; // The pseudo instruction is gone now.
1493 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
14941494 return BB;
14951495 }
14961496 }
151151 return;
152152 }
153153
154 MachineInstr *MI = Orig->clone();
154 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
155155 MI->getOperand(0).setReg(DestReg);
156156 MBB.insert(I, MI);
157157 }
195195 return NULL;
196196
197197 MachineInstr *MI = MBBI;
198 MachineFunction &MF = *MI->getParent()->getParent();
198199 unsigned TSFlags = MI->getDesc().TSFlags;
199200 bool isPre = false;
200201 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
239240 // Can't encode it in a so_imm operand. This transformation will
240241 // add more than 1 instruction. Abandon!
241242 return NULL;
242 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
243 UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
243244 .addReg(BaseReg).addImm(SOImmVal)
244245 .addImm(Pred).addReg(0).addReg(0);
245246 } else if (Amt != 0) {
246247 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
247248 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
248 UpdateMI = BuildMI(get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
249 UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
249250 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
250251 .addImm(Pred).addReg(0).addReg(0);
251252 } else
252 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
253 UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
253254 .addReg(BaseReg).addReg(OffReg)
254255 .addImm(Pred).addReg(0).addReg(0);
255256 break;
259260 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
260261 if (OffReg == 0)
261262 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
262 UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
263 UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
263264 .addReg(BaseReg).addImm(Amt)
264265 .addImm(Pred).addReg(0).addReg(0);
265266 else
266 UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
267 UpdateMI = BuildMI(MF, get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
267268 .addReg(BaseReg).addReg(OffReg)
268269 .addImm(Pred).addReg(0).addReg(0);
269270 break;
273274 std::vector NewMIs;
274275 if (isPre) {
275276 if (isLoad)
276 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
277 MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg())
277278 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
278279 else
279 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
280 MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg())
280281 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
281282 NewMIs.push_back(MemMI);
282283 NewMIs.push_back(UpdateMI);
283284 } else {
284285 if (isLoad)
285 MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
286 MemMI = BuildMI(MF, get(MemOpc), MI->getOperand(0).getReg())
286287 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
287288 else
288 MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
289 MemMI = BuildMI(MF, get(MemOpc)).addReg(MI->getOperand(1).getReg())
289290 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
290291 if (WB.isDead())
291292 UpdateMI->getOperand(0).setIsDead();
536537 if (AFI->isThumbFunction()) {
537538 Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
538539 MachineInstrBuilder MIB =
539 BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
540 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
540541 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
541542 MIB = ARMInstrAddOperand(MIB, Addr[i]);
542543 NewMIs.push_back(MIB);
551552 }
552553
553554 MachineInstrBuilder MIB =
554 BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
555 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
555556 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
556557 MIB = ARMInstrAddOperand(MIB, Addr[i]);
557558 AddDefaultPred(MIB);
591592 ARMFunctionInfo *AFI = MF.getInfo();
592593 if (AFI->isThumbFunction()) {
593594 Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
594 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
595 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
595596 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
596597 MIB = ARMInstrAddOperand(MIB, Addr[i]);
597598 NewMIs.push_back(MIB);
605606 Opc = ARM::FLDS;
606607 }
607608
608 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
609 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
609610 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
610611 MIB = ARMInstrAddOperand(MIB, Addr[i]);
611612 AddDefaultPred(MIB);
640641 return false;
641642
642643 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
643 MachineInstr *PopMI = new MachineInstr(get(ARM::tPOP));
644 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP));
644645 MBB.insert(MI, PopMI);
645646 for (unsigned i = CSI.size(); i != 0; --i) {
646647 unsigned Reg = CSI[i-1].getReg();
677678 if (OpNum == 0) { // move -> store
678679 unsigned SrcReg = MI->getOperand(1).getReg();
679680 bool isKill = MI->getOperand(1).isKill();
680 NewMI = BuildMI(get(ARM::STR)).addReg(SrcReg, false, false, isKill)
681 NewMI = BuildMI(MF, get(ARM::STR)).addReg(SrcReg, false, false, isKill)
681682 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
682683 } else { // move -> load
683684 unsigned DstReg = MI->getOperand(0).getReg();
684685 bool isDead = MI->getOperand(0).isDead();
685 NewMI = BuildMI(get(ARM::LDR)).addReg(DstReg, true, false, false, isDead)
686 NewMI = BuildMI(MF, get(ARM::LDR)).addReg(DstReg, true, false, false, isDead)
686687 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
687688 }
688689 break;
694695 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
695696 // tSpill cannot take a high register operand.
696697 break;
697 NewMI = BuildMI(get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
698 NewMI = BuildMI(MF, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
698699 .addFrameIndex(FI).addImm(0);
699700 } else { // move -> load
700701 unsigned DstReg = MI->getOperand(0).getReg();
702703 // tRestore cannot target a high register operand.
703704 break;
704705 bool isDead = MI->getOperand(0).isDead();
705 NewMI = BuildMI(get(ARM::tRestore))
706 NewMI = BuildMI(MF, get(ARM::tRestore))
706707 .addReg(DstReg, true, false, false, isDead)
707708 .addFrameIndex(FI).addImm(0);
708709 }
713714 unsigned PredReg = MI->getOperand(3).getReg();
714715 if (OpNum == 0) { // move -> store
715716 unsigned SrcReg = MI->getOperand(1).getReg();
716 NewMI = BuildMI(get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
717 NewMI = BuildMI(MF, get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
717718 .addImm(0).addImm(Pred).addReg(PredReg);
718719 } else { // move -> load
719720 unsigned DstReg = MI->getOperand(0).getReg();
720 NewMI = BuildMI(get(ARM::FLDS), DstReg).addFrameIndex(FI)
721 NewMI = BuildMI(MF, get(ARM::FLDS), DstReg).addFrameIndex(FI)
721722 .addImm(0).addImm(Pred).addReg(PredReg);
722723 }
723724 break;
728729 if (OpNum == 0) { // move -> store
729730 unsigned SrcReg = MI->getOperand(1).getReg();
730731 bool isKill = MI->getOperand(1).isKill();
731 NewMI = BuildMI(get(ARM::FSTD)).addReg(SrcReg, false, false, isKill)
732 NewMI = BuildMI(MF, get(ARM::FSTD)).addReg(SrcReg, false, false, isKill)
732733 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
733734 } else { // move -> load
734735 unsigned DstReg = MI->getOperand(0).getReg();
735736 bool isDead = MI->getOperand(0).isDead();
736 NewMI = BuildMI(get(ARM::FLDD)).addReg(DstReg, true, false, false, isDead)
737 NewMI = BuildMI(MF, get(ARM::FLDD)).addReg(DstReg, true, false, false, isDead)
737738 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
738739 }
739740 break;
923924 MachineOperand JTOP =
924925 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
925926 unsigned JTI = JTOP.getIndex();
926 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
927 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
927928 const std::vector &JT = MJTI->getJumpTables();
928929 assert(JTI < JT.size());
929930 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
661661 //test sc and maybe branck to start
662662 //exit:
663663 const BasicBlock *LLVM_BB = BB->getBasicBlock();
664 ilist::iterator It = BB;
664 MachineFunction::iterator It = BB;
665665 ++It;
666666
667667 MachineBasicBlock *thisMBB = BB;
668 MachineBasicBlock *llscMBB = new MachineBasicBlock(LLVM_BB);
669 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
668 MachineFunction *F = BB->getParent();
669 MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
670 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
670671
671672 sinkMBB->transferSuccessors(thisMBB);
672673
673 MachineFunction *F = BB->getParent();
674 F->getBasicBlockList().insert(It, llscMBB);
675 F->getBasicBlockList().insert(It, sinkMBB);
674 F->insert(It, llscMBB);
675 F->insert(It, sinkMBB);
676676
677677 BuildMI(thisMBB, TII->get(Alpha::BR)).addMBB(llscMBB);
678678
718718 thisMBB->addSuccessor(llscMBB);
719719 llscMBB->addSuccessor(llscMBB);
720720 llscMBB->addSuccessor(sinkMBB);
721 delete MI; // The pseudo instruction is gone now.
721 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
722722
723723 return sinkMBB;
724724 }
193193 else
194194 abort();
195195 MachineInstrBuilder MIB =
196 BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
196 BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
197197 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
198198 MachineOperand &MO = Addr[i];
199199 if (MO.isRegister())
238238 else
239239 abort();
240240 MachineInstrBuilder MIB =
241 BuildMI(get(Opc), DestReg);
241 BuildMI(MF, get(Opc), DestReg);
242242 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
243243 MachineOperand &MO = Addr[i];
244244 if (MO.isRegister())
271271 bool isKill = MI->getOperand(1).isKill();
272272 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
273273 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
274 NewMI = BuildMI(get(Opc)).addReg(InReg, false, false, isKill)
274 NewMI = BuildMI(MF, get(Opc)).addReg(InReg, false, false, isKill)
275275 .addFrameIndex(FrameIndex)
276276 .addReg(Alpha::F31);
277277 } else { // load -> move
279279 bool isDead = MI->getOperand(0).isDead();
280280 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
281281 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
282 NewMI = BuildMI(get(Opc)).addReg(OutReg, true, false, false, isDead)
282 NewMI = BuildMI(MF, get(Opc)).addReg(OutReg, true, false, false, isDead)
283283 .addFrameIndex(FrameIndex)
284284 .addReg(Alpha::F31);
285285 }
102102 // if frame pointer elimination is disabled.
103103 //
104104 bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
105 MachineFrameInfo *MFI = MF.getFrameInfo();
105 const MachineFrameInfo *MFI = MF.getFrameInfo();
106106 return MFI->hasVarSizedObjects();
107107 }
108108
124124
125125 MachineInstr *New;
126126 if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
127 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
127 New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30)
128128 .addImm(-Amount).addReg(Alpha::R30);
129129 } else {
130130 assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
131 New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
131 New=BuildMI(MF, TII.get(Alpha::LDA), Alpha::R30)
132132 .addImm(Amount).addReg(Alpha::R30);
133133 }
134134
187187 MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
188188 MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
189189 //insert the new
190 MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
190 MachineInstr* nMI=BuildMI(MF, TII.get(Alpha::LDAH), Alpha::R28)
191191 .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
192192 MBB.insert(II, nMI);
193193 } else {
290290 assert(0 && "Unknown regclass!");
291291 abort();
292292 }
293 MachineInstrBuilder MIB = BuildMI(get(Opc))
293 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
294294 .addReg(SrcReg, false, false, isKill);
295295 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
296296 MachineOperand &MO = Addr[i];
377377 assert(0 && "Unknown regclass!");
378378 abort();
379379 }
380 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
380 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
381381 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
382382 MachineOperand &MO = Addr[i];
383383 if (MO.isRegister())
413413 unsigned InReg = MI->getOperand(1).getReg();
414414 bool isKill = MI->getOperand(1).isKill();
415415 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
416 NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32))
416 NewMI = addFrameReference(BuildMI(MF, TII.get(SPU::STQDr32))
417417 .addReg(InReg, false, false, isKill),
418418 FrameIndex);
419419 }
422422 bool isDead = MI->getOperand(0).isDead();
423423 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
424424 ? SPU::STQDr32 : SPU::STQXr32;
425 NewMI = addFrameReference(BuildMI(TII.get(Opc))
425 NewMI = addFrameReference(BuildMI(MF, TII.get(Opc))
426426 .addReg(OutReg, true, false, false, isDead), FrameIndex);
427427 }
428428 }
116116 "sorry, I don't know how to store this sort of reg\n");
117117 }
118118
119 MachineInstrBuilder MIB = BuildMI(get(Opc));
119 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
120120 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
121121 MachineOperand &MO = Addr[i];
122122 if (MO.isRegister())
168168 "sorry, I don't know how to store this sort of reg\n");
169169 }
170170
171 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
171 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
172172 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
173173 MachineOperand &MO = Addr[i];
174174 if (MO.isRegister())
9393 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
9494 Amount = (Amount+Align-1)/Align*Align;
9595
96 MachineInstr *New;
96 // Replace the pseudo instruction with a new instruction...
9797 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
98 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
98 BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
9999 .addImm(-Amount);
100100 } else {
101101 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
102 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
102 BuildMI(MBB, I, TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
103103 .addImm(Amount);
104104 }
105
106 // Replace the pseudo instruction with a new instruction...
107 MBB.insert(I, New);
108105 }
109106 }
110107
147144 // Fix up the old:
148145 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
149146 //insert the new
150 MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22)
147 BuildMI(MBB, II, TII.get(IA64::ADDIMM22), IA64::r22)
151148 .addReg(BaseRegister).addImm(Offset);
152 MBB.insert(II, nMI);
153149 } else { // it's big
154150 //fix up the old:
155151 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
156 MachineInstr* nMI;
157 nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
158 MBB.insert(II, nMI);
159 nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
152 BuildMI(MBB, II, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
153 BuildMI(MBB, II, TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
160154 .addReg(IA64::r22);
161 MBB.insert(II, nMI);
162155 }
163156
164157 }
167160 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
168161 MachineBasicBlock::iterator MBBI = MBB.begin();
169162 MachineFrameInfo *MFI = MF.getFrameInfo();
170 MachineInstr *MI;
171163 bool FP = hasFP(MF);
172164
173165 // first, we handle the 'alloc' instruction, that should be right up the
211203 }
212204 }
213205
214 MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \
206 BuildMI(MBB, MBBI, TII.get(IA64::ALLOC)).
207 addReg(dstRegOfPseudoAlloc).addImm(0).
215208 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
216 MBB.insert(MBBI, MI);
217209
218210 // Get the number of bytes to allocate from the FrameInfo
219211 unsigned NumBytes = MFI->getStackSize();
236228
237229 // adjust stack pointer: r12 -= numbytes
238230 if (NumBytes <= 8191) {
239 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
231 BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
240232 addImm(-NumBytes);
241 MBB.insert(MBBI, MI);
242233 } else { // we use r22 as a scratch register here
243 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
234 // first load the decrement into r22
235 BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
244236 // FIXME: MOVLSI32 expects a _u_32imm
245 MBB.insert(MBBI, MI); // first load the decrement into r22
246 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
247 MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
237 // then add (subtract) it to r12 (stack ptr)
238 BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12)
239 .addReg(IA64::r12).addReg(IA64::r22);
240
248241 }
249242
250243 // now if we need to, save the old FP and set the new
251244 if (FP) {
252 MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
253 MBB.insert(MBBI, MI);
245 BuildMI(MBB, MBBI, TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
254246 // this must be the last instr in the prolog ? (XXX: why??)
255 MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
256 MBB.insert(MBBI, MI);
247 BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
257248 }
258249
259250 }
262253 MachineBasicBlock &MBB) const {
263254 const MachineFrameInfo *MFI = MF.getFrameInfo();
264255 MachineBasicBlock::iterator MBBI = prior(MBB.end());
265 MachineInstr *MI;
266256 assert(MBBI->getOpcode() == IA64::RET &&
267257 "Can only insert epilog into returning blocks");
268258
275265 if (FP)
276266 {
277267 //copy the FP into the SP (discards allocas)
278 MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
279 MBB.insert(MBBI, MI);
268 BuildMI(MBB, MBBI, TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
280269 //restore the FP
281 MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
282 MBB.insert(MBBI, MI);
270 BuildMI(MBB, MBBI, TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
283271 }
284272
285273 if (NumBytes != 0)
286274 {
287275 if (NumBytes <= 8191) {
288 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
276 BuildMI(MBB, MBBI, TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
289277 addImm(NumBytes);
290 MBB.insert(MBBI, MI);
291278 } else {
292 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes);
293 MBB.insert(MBBI, MI);
294 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
279 BuildMI(MBB, MBBI, TII.get(IA64::MOVLIMM64), IA64::r22).
280 addImm(NumBytes);
281 BuildMI(MBB, MBBI, TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
295282 addReg(IA64::r22);
296 MBB.insert(MBBI, MI);
297283 }
298284 }
299285
168168 // destination vreg to set, the condition code register to branch on, the
169169 // true/false values to select between, and a branch opcode to use.
170170 const BasicBlock *LLVM_BB = BB->getBasicBlock();
171 ilist::iterator It = BB;
171 MachineFunction::iterator It = BB;
172172 ++It;
173173
174174 // thisMBB:
178178 // bNE r1, r0, copy1MBB
179179 // fallthrough --> copy0MBB
180180 MachineBasicBlock *thisMBB = BB;
181 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
182 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
181 MachineFunction *F = BB->getParent();
182 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
183 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
183184 BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
184185 .addReg(Mips::ZERO).addMBB(sinkMBB);
185 MachineFunction *F = BB->getParent();
186 F->getBasicBlockList().insert(It, copy0MBB);
187 F->getBasicBlockList().insert(It, sinkMBB);
186 F->insert(It, copy0MBB);
187 F->insert(It, sinkMBB);
188188 // Update machine-CFG edges by first adding all successors of the current
189189 // block to the new block which will contain the Phi node for the select.
190190 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
213213 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
214214 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
215215
216 delete MI; // The pseudo instruction is gone now.
216 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
217217 return BB;
218218 }
219219 }
189189 else
190190 assert(0 && "Can't store this register");
191191
192 MachineInstrBuilder MIB = BuildMI(get(Opc))
192 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
193193 .addReg(SrcReg, false, false, isKill);
194194 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
195195 MachineOperand &MO = Addr[i];
240240 else
241241 assert(0 && "Can't load this register");
242242
243 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
243 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
244244 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
245245 MachineOperand &MO = Addr[i];
246246 if (MO.isRegister())
272272 if (Ops[0] == 0) { // COPY -> STORE
273273 unsigned SrcReg = MI->getOperand(2).getReg();
274274 bool isKill = MI->getOperand(2).isKill();
275 NewMI = BuildMI(get(Mips::SW)).addFrameIndex(FI)
275 NewMI = BuildMI(MF, get(Mips::SW)).addFrameIndex(FI)
276276 .addImm(0).addReg(SrcReg, false, false, isKill);
277277 } else { // COPY -> LOAD
278278 unsigned DstReg = MI->getOperand(0).getReg();
279279 bool isDead = MI->getOperand(0).isDead();
280 NewMI = BuildMI(get(Mips::LW))
280 NewMI = BuildMI(MF, get(Mips::LW))
281281 .addReg(DstReg, true, false, false, isDead)
282282 .addImm(0).addFrameIndex(FI);
283283 }
303303 if (Ops[0] == 0) { // COPY -> STORE
304304 unsigned SrcReg = MI->getOperand(1).getReg();
305305 bool isKill = MI->getOperand(1).isKill();
306 NewMI = BuildMI(get(StoreOpc)).addFrameIndex(FI)
306 NewMI = BuildMI(MF, get(StoreOpc)).addFrameIndex(FI)
307307 .addImm(0).addReg(SrcReg, false, false, isKill);
308308 } else { // COPY -> LOAD
309309 unsigned DstReg = MI->getOperand(0).getReg();
310310 bool isDead = MI->getOperand(0).isDead();
311 NewMI = BuildMI(get(LoadOpc))
311 NewMI = BuildMI(MF, get(LoadOpc))
312312 .addReg(DstReg, true, false, false, isDead)
313313 .addImm(0).addFrameIndex(FI);
314314 }
6060 unsigned DestReg,
6161 const MachineInstr *Orig) const
6262 {
63 MachineInstr *MI = Orig->clone();
63 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
6464 MI->getOperand(0).setReg(DestReg);
6565 MBB.insert(I, MI);
6666 }
39913991 // to set, the condition code register to branch on, the true/false values to
39923992 // select between, and a branch opcode to use.
39933993 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3994 ilist::iterator It = BB;
3994 MachineFunction::iterator It = BB;
39953995 ++It;
39963996
39973997 // thisMBB:
40014001 // bCC copy1MBB
40024002 // fallthrough --> copy0MBB
40034003 MachineBasicBlock *thisMBB = BB;
4004 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4005 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4004 MachineFunction *F = BB->getParent();
4005 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4006 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
40064007 unsigned SelectPred = MI->getOperand(4).getImm();
40074008 BuildMI(BB, TII->get(PPC::BCC))
40084009 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4009 MachineFunction *F = BB->getParent();
4010 F->getBasicBlockList().insert(It, copy0MBB);
4011 F->getBasicBlockList().insert(It, sinkMBB);
4010 F->insert(It, copy0MBB);
4011 F->insert(It, sinkMBB);
40124012 // Update machine-CFG edges by transferring all successors of the current
40134013 // block to the new block which will contain the Phi node for the select.
40144014 sinkMBB->transferSuccessors(BB);
40324032 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
40334033 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
40344034
4035 delete MI; // The pseudo instruction is gone now.
4035 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
40364036 return BB;
40374037 }
40384038
137137 // rotate amt is zero. We also have to munge the immediates a bit.
138138 MachineInstr *
139139 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
140 MachineFunction &MF = *MI->getParent()->getParent();
141
140142 // Normal instructions can be commuted the obvious way.
141143 if (MI->getOpcode() != PPC::RLWIMI)
142144 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
177179 // Create a new instruction.
178180 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
179181 bool Reg0IsDead = MI->getOperand(0).isDead();
180 return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead)
182 return BuildMI(MF, MI->getDesc())
183 .addReg(Reg0, true, false, false, Reg0IsDead)
181184 .addReg(Reg2, false, false, Reg2IsKill)
182185 .addReg(Reg1, false, false, Reg1IsKill)
183186 .addImm((ME+1) & 31)
342345 }
343346
344347 bool
345 PPCInstrInfo::StoreRegToStackSlot(unsigned SrcReg, bool isKill,
348 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
349 unsigned SrcReg, bool isKill,
346350 int FrameIdx,
347351 const TargetRegisterClass *RC,
348352 SmallVectorImpl &NewMIs) const{
349353 if (RC == PPC::GPRCRegisterClass) {
350354 if (SrcReg != PPC::LR) {
351 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
355 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
352356 .addReg(SrcReg, false, false, isKill),
353357 FrameIdx));
354358 } else {
355359 // FIXME: this spills LR immediately to memory in one step. To do this,
356360 // we use R11, which we know cannot be used in the prolog/epilog. This is
357361 // a hack.
358 NewMIs.push_back(BuildMI(get(PPC::MFLR), PPC::R11));
359 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
362 NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
363 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
360364 .addReg(PPC::R11, false, false, isKill),
361365 FrameIdx));
362366 }
363367 } else if (RC == PPC::G8RCRegisterClass) {
364368 if (SrcReg != PPC::LR8) {
365 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD))
369 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
366370 .addReg(SrcReg, false, false, isKill), FrameIdx));
367371 } else {
368372 // FIXME: this spills LR immediately to memory in one step. To do this,
369373 // we use R11, which we know cannot be used in the prolog/epilog. This is
370374 // a hack.
371 NewMIs.push_back(BuildMI(get(PPC::MFLR8), PPC::X11));
372 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD))
375 NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
376 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
373377 .addReg(PPC::X11, false, false, isKill), FrameIdx));
374378 }
375379 } else if (RC == PPC::F8RCRegisterClass) {
376 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFD))
380 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
377381 .addReg(SrcReg, false, false, isKill), FrameIdx));
378382 } else if (RC == PPC::F4RCRegisterClass) {
379 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFS))
383 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
380384 .addReg(SrcReg, false, false, isKill), FrameIdx));
381385 } else if (RC == PPC::CRRCRegisterClass) {
382386 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
383387 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
384388 // FIXME (64-bit): Enable
385 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::SPILL_CR))
389 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
386390 .addReg(SrcReg, false, false, isKill),
387391 FrameIdx));
388392 return true;
390394 // FIXME: We use R0 here, because it isn't available for RA. We need to
391395 // store the CR in the low 4-bits of the saved value. First, issue a MFCR
392396 // to save all of the CRBits.
393 NewMIs.push_back(BuildMI(get(PPC::MFCR), PPC::R0));
397 NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
394398
395399 // If the saved register wasn't CR0, shift the bits left so that they are
396400 // in CR0's slot.
397401 if (SrcReg != PPC::CR0) {
398402 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
399403 // rlwinm r0, r0, ShiftBits, 0, 31.
400 NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0)
404 NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
401405 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
402406 }
403407
404 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
408 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
405409 .addReg(PPC::R0, false, false, isKill),
406410 FrameIdx));
407411 }
428432 else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
429433 Reg = PPC::CR7;
430434
431 return StoreRegToStackSlot(Reg, isKill, FrameIdx,
435 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
432436 PPC::CRRCRegisterClass, NewMIs);
433437
434438 } else if (RC == PPC::VRRCRegisterClass) {
437441 // STVX VAL, 0, R0
438442 //
439443 // FIXME: We use R0 here, because it isn't available for RA.
440 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0),
444 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
441445 FrameIdx, 0, 0));
442 NewMIs.push_back(BuildMI(get(PPC::STVX))
446 NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
443447 .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
444448 } else {
445449 assert(0 && "Unknown regclass!");
454458 MachineBasicBlock::iterator MI,
455459 unsigned SrcReg, bool isKill, int FrameIdx,
456460 const TargetRegisterClass *RC) const {
461 MachineFunction &MF = *MBB.getParent();
457462 SmallVector NewMIs;
458463
459 if (StoreRegToStackSlot(SrcReg, isKill, FrameIdx, RC, NewMIs)) {
460 PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo();
464 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
465 PPCFunctionInfo *FuncInfo = MF.getInfo();
461466 FuncInfo->setSpillsCR();
462467 }
463468
471476 const TargetRegisterClass *RC,
472477 SmallVectorImpl &NewMIs) const{
473478 if (Addr[0].isFrameIndex()) {
474 if (StoreRegToStackSlot(SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs)) {
479 if (StoreRegToStackSlot(MF, SrcReg, isKill,
480 Addr[0].getIndex(), RC, NewMIs)) {
475481 PPCFunctionInfo *FuncInfo = MF.getInfo();
476482 FuncInfo->setSpillsCR();
477483 }
494500 assert(0 && "Unknown regclass!");
495501 abort();
496502 }
497 MachineInstrBuilder MIB = BuildMI(get(Opc))
503 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
498504 .addReg(SrcReg, false, false, isKill);
499505 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
500506 MachineOperand &MO = Addr[i];
510516 }
511517
512518 void
513 PPCInstrInfo::LoadRegFromStackSlot(unsigned DestReg, int FrameIdx,
519 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF,
520 unsigned DestReg, int FrameIdx,
514521 const TargetRegisterClass *RC,
515522 SmallVectorImpl &NewMIs)const{
516523 if (RC == PPC::GPRCRegisterClass) {
517524 if (DestReg != PPC::LR) {
518 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), DestReg),
525 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg),
519526 FrameIdx));
520527 } else {
521 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R11),
528 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11),
522529 FrameIdx));
523 NewMIs.push_back(BuildMI(get(PPC::MTLR)).addReg(PPC::R11));
530 NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11));
524531 }
525532 } else if (RC == PPC::G8RCRegisterClass) {
526533 if (DestReg != PPC::LR8) {
527 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), DestReg),
534 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg),
528535 FrameIdx));
529536 } else {
530 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), PPC::R11),
537 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11),
531538 FrameIdx));
532 NewMIs.push_back(BuildMI(get(PPC::MTLR8)).addReg(PPC::R11));
539 NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11));
533540 }
534541 } else if (RC == PPC::F8RCRegisterClass) {
535 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFD), DestReg),
542 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg),
536543 FrameIdx));
537544 } else if (RC == PPC::F4RCRegisterClass) {
538 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFS), DestReg),
545 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg),
539546 FrameIdx));
540547 } else if (RC == PPC::CRRCRegisterClass) {
541548 // FIXME: We use R0 here, because it isn't available for RA.
542 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R0),
549 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0),
543550 FrameIdx));
544551
545552 // If the reloaded register isn't CR0, shift the bits right so that they are
547554 if (DestReg != PPC::CR0) {
548555 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
549556 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
550 NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0)
557 NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
551558 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
552559 }
553560
554 NewMIs.push_back(BuildMI(get(PPC::MTCRF), DestReg).addReg(PPC::R0));
561 NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
555562 } else if (RC == PPC::CRBITRCRegisterClass) {
556563
557564 unsigned Reg = 0;
572579 else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
573580 Reg = PPC::CR7;
574581
575 return LoadRegFromStackSlot(Reg, FrameIdx,
582 return LoadRegFromStackSlot(MF, Reg, FrameIdx,
576583 PPC::CRRCRegisterClass, NewMIs);
577584
578585 } else if (RC == PPC::VRRCRegisterClass) {
581588 // Dest = LVX 0, R0
582589 //
583590 // FIXME: We use R0 here, because it isn't available for RA.
584 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0),
591 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
585592 FrameIdx, 0, 0));
586 NewMIs.push_back(BuildMI(get(PPC::LVX),DestReg).addReg(PPC::R0)
593 NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0)
587594 .addReg(PPC::R0));
588595 } else {
589596 assert(0 && "Unknown regclass!");
596603 MachineBasicBlock::iterator MI,
597604 unsigned DestReg, int FrameIdx,
598605 const TargetRegisterClass *RC) const {
606 MachineFunction &MF = *MBB.getParent();
599607 SmallVector NewMIs;
600 LoadRegFromStackSlot(DestReg, FrameIdx, RC, NewMIs);
608 LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs);
601609 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
602610 MBB.insert(MI, NewMIs[i]);
603611 }
607615 const TargetRegisterClass *RC,
608616 SmallVectorImpl &NewMIs)const{
609617 if (Addr[0].isFrameIndex()) {
610 LoadRegFromStackSlot(DestReg, Addr[0].getIndex(), RC, NewMIs);
618 LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
611619 return;
612620 }
613621
628636 assert(0 && "Unknown regclass!");
629637 abort();
630638 }
631 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
639 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
632640 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
633641 MachineOperand &MO = Addr[i];
634642 if (MO.isRegister())
661669 if (OpNum == 0) { // move -> store
662670 unsigned InReg = MI->getOperand(1).getReg();
663671 bool isKill = MI->getOperand(1).isKill();
664 NewMI = addFrameReference(BuildMI(get(PPC::STW))
672 NewMI = addFrameReference(BuildMI(MF, get(PPC::STW))
665673 .addReg(InReg, false, false, isKill),
666674 FrameIndex);
667675 } else { // move -> load
668676 unsigned OutReg = MI->getOperand(0).getReg();
669677 bool isDead = MI->getOperand(0).isDead();
670 NewMI = addFrameReference(BuildMI(get(PPC::LWZ))
678 NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ))
671679 .addReg(OutReg, true, false, false, isDead),
672680 FrameIndex);
673681 }
676684 if (OpNum == 0) { // move -> store
677685 unsigned InReg = MI->getOperand(1).getReg();
678686 bool isKill = MI->getOperand(1).isKill();
679 NewMI = addFrameReference(BuildMI(get(PPC::STD))
687 NewMI = addFrameReference(BuildMI(MF, get(PPC::STD))
680688 .addReg(InReg, false, false, isKill),
681689 FrameIndex);
682690 } else { // move -> load
683691 unsigned OutReg = MI->getOperand(0).getReg();
684692 bool isDead = MI->getOperand(0).isDead();
685 NewMI = addFrameReference(BuildMI(get(PPC::LD))
693 NewMI = addFrameReference(BuildMI(MF, get(PPC::LD))
686694 .addReg(OutReg, true, false, false, isDead),
687695 FrameIndex);
688696 }
690698 if (OpNum == 0) { // move -> store
691699 unsigned InReg = MI->getOperand(1).getReg();
692700 bool isKill = MI->getOperand(1).isKill();
693 NewMI = addFrameReference(BuildMI(get(PPC::STFD))
701 NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD))
694702 .addReg(InReg, false, false, isKill),
695703 FrameIndex);
696704 } else { // move -> load
697705 unsigned OutReg = MI->getOperand(0).getReg();
698706 bool isDead = MI->getOperand(0).isDead();
699 NewMI = addFrameReference(BuildMI(get(PPC::LFD))
707 NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD))
700708 .addReg(OutReg, true, false, false, isDead),
701709 FrameIndex);
702710 }
704712 if (OpNum == 0) { // move -> store
705713 unsigned InReg = MI->getOperand(1).getReg();
706714 bool isKill = MI->getOperand(1).isKill();
707 NewMI = addFrameReference(BuildMI(get(PPC::STFS))
715 NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS))
708716 .addReg(InReg, false, false, isKill),
709717 FrameIndex);
710718 } else { // move -> load
711719 unsigned OutReg = MI->getOperand(0).getReg();
712720 bool isDead = MI->getOperand(0).isDead();
713 NewMI = addFrameReference(BuildMI(get(PPC::LFS))
721 NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS))
714722 .addReg(OutReg, true, false, false, isDead),
715723 FrameIndex);
716724 }
6464 PPCTargetMachine &TM;
6565 const PPCRegisterInfo RI;
6666
67 bool StoreRegToStackSlot(unsigned SrcReg, bool isKill, int FrameIdx,
67 bool StoreRegToStackSlot(MachineFunction &MF,
68 unsigned SrcReg, bool isKill, int FrameIdx,
6869 const TargetRegisterClass *RC,
6970 SmallVectorImpl &NewMIs) const;
70 void LoadRegFromStackSlot(unsigned DestReg, int FrameIdx,
71 void LoadRegFromStackSlot(MachineFunction &MF,
72 unsigned DestReg, int FrameIdx,
7173 const TargetRegisterClass *RC,
7274 SmallVectorImpl &NewMIs) const;
7375 public:
900900 // to set, the condition code register to branch on, the true/false values to
901901 // select between, and a branch opcode to use.
902902 const BasicBlock *LLVM_BB = BB->getBasicBlock();
903 ilist::iterator It = BB;
903 MachineFunction::iterator It = BB;
904904 ++It;
905905
906906 // thisMBB:
909909 // [f]bCC copy1MBB
910910 // fallthrough --> copy0MBB
911911 MachineBasicBlock *thisMBB = BB;
912 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
913 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
912 MachineFunction *F = BB->getParent();
913 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
914 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
914915 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
915 MachineFunction *F = BB->getParent();
916 F->getBasicBlockList().insert(It, copy0MBB);
917 F->getBasicBlockList().insert(It, sinkMBB);
916 F->insert(It, copy0MBB);
917 F->insert(It, sinkMBB);
918918 // Update machine-CFG edges by transferring all successors of the current
919919 // block to the new block which will contain the Phi node for the select.
920920 sinkMBB->transferSuccessors(BB);
938938 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
939939 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
940940
941 delete MI; // The pseudo instruction is gone now.
941 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
942942 return BB;
943943 }
944944
161161 Opc = SP::STDFri;
162162 else
163163 assert(0 && "Can't load this register");
164 MachineInstrBuilder MIB = BuildMI(get(Opc));
164 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
165165 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
166166 MachineOperand &MO = Addr[i];
167167 if (MO.isRegister())
205205 Opc = SP::LDDFri;
206206 else
207207 assert(0 && "Can't load this register");
208 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
208 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
209209 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
210210 MachineOperand &MO = Addr[i];
211211 if (MO.isReg())
235235 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
236236 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
237237 if (OpNum == 0) // COPY -> STORE
238 NewMI = BuildMI(get(SP::STri)).addFrameIndex(FI).addImm(0)
238 NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0)
239239 .addReg(MI->getOperand(2).getReg());
240240 else // COPY -> LOAD
241 NewMI = BuildMI(get(SP::LDri), MI->getOperand(0).getReg())
241 NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg())
242242 .addFrameIndex(FI).addImm(0);
243243 }
244244 break;
249249 if (OpNum == 0) { // COPY -> STORE
250250 unsigned SrcReg = MI->getOperand(1).getReg();
251251 bool isKill = MI->getOperand(1).isKill();
252 NewMI = BuildMI(get(isFloat ? SP::STFri : SP::STDFri))
252 NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri))
253253 .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill);
254254 } else { // COPY -> LOAD
255255 unsigned DstReg = MI->getOperand(0).getReg();
256256 bool isDead = MI->getOperand(0).isDead();
257 NewMI = BuildMI(get(isFloat ? SP::LDFri : SP::LDDFri))
257 NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri))
258258 .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0);
259259 }
260260 break;
857857 assert(UpdatedSlot < StackTop && Dest < 7);
858858 Stack[UpdatedSlot] = Dest;
859859 RegMap[Dest] = UpdatedSlot;
860 delete MI; // Remove the old instruction
860 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
861861 }
862862
863863 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
59545954 // fallthrough -->nextMBB
59555955 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
59565956 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
5957 ilist::iterator MBBIter = MBB;
5957 MachineFunction::iterator MBBIter = MBB;
59585958 ++MBBIter;
59595959
59605960 /// First build the CFG
59615961 MachineFunction *F = MBB->getParent();
59625962 MachineBasicBlock *thisMBB = MBB;
5963 MachineBasicBlock *newMBB = new MachineBasicBlock(LLVM_BB);
5964 MachineBasicBlock *nextMBB = new MachineBasicBlock(LLVM_BB);
5965 F->getBasicBlockList().insert(MBBIter, newMBB);
5966 F->getBasicBlockList().insert(MBBIter, nextMBB);
5963 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
5964 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
5965 F->insert(MBBIter, newMBB);
5966 F->insert(MBBIter, nextMBB);
59675967
59685968 // Move all successors to thisMBB to nextMBB
59695969 nextMBB->transferSuccessors(thisMBB);
60236023 // insert branch
60246024 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
60256025
6026 delete bInstr; // The pseudo instruction is gone now.
6026 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
60276027 return nextMBB;
60286028 }
60296029
60466046 //
60476047 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
60486048 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6049 ilist::iterator MBBIter = MBB;
6049 MachineFunction::iterator MBBIter = MBB;
60506050 ++MBBIter;
60516051
60526052 /// First build the CFG
60536053 MachineFunction *F = MBB->getParent();
60546054 MachineBasicBlock *thisMBB = MBB;
6055 MachineBasicBlock *newMBB = new MachineBasicBlock(LLVM_BB);
6056 MachineBasicBlock *nextMBB = new MachineBasicBlock(LLVM_BB);
6057 F->getBasicBlockList().insert(MBBIter, newMBB);
6058 F->getBasicBlockList().insert(MBBIter, nextMBB);
6055 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6056 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6057 F->insert(MBBIter, newMBB);
6058 F->insert(MBBIter, nextMBB);
60596059
60606060 // Move all successors to thisMBB to nextMBB
60616061 nextMBB->transferSuccessors(thisMBB);
61206120 // insert branch
61216121 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
61226122
6123 delete mInstr; // The pseudo instruction is gone now.
6123 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
61246124 return nextMBB;
61256125 }
61266126
61416141 // destination vreg to set, the condition code register to branch on, the
61426142 // true/false values to select between, and a branch opcode to use.
61436143 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6144 ilist::iterator It = BB;
6144 MachineFunction::iterator It = BB;
61456145 ++It;
61466146
61476147 // thisMBB:
61516151 // bCC copy1MBB
61526152 // fallthrough --> copy0MBB
61536153 MachineBasicBlock *thisMBB = BB;
6154 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
6155 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
6154 MachineFunction *F = BB->getParent();
6155 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6156 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
61566157 unsigned Opc =
61576158 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
61586159 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
6159 MachineFunction *F = BB->getParent();
6160 F->getBasicBlockList().insert(It, copy0MBB);
6161 F->getBasicBlockList().insert(It, sinkMBB);
6160 F->insert(It, copy0MBB);
6161 F->insert(It, sinkMBB);
61626162 // Update machine-CFG edges by transferring all successors of the current
61636163 // block to the new block which will contain the Phi node for the select.
61646164 sinkMBB->transferSuccessors(BB);
61836183 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
61846184 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
61856185
6186 delete MI; // The pseudo instruction is gone now.
6186 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
61876187 return BB;
61886188 }
61896189
62606260 // Reload the original control word now.
62616261 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
62626262
6263 delete MI; // The pseudo instruction is gone now.
6263 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
62646264 return BB;
62656265 }
62666266 case X86::ATOMAND32:
749749
750750 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
751751 /// X86::MOVPC32r.
752 static bool regIsPICBase(unsigned BaseReg, MachineRegisterInfo &MRI) {
752 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
753753 bool isPICBase = false;
754754 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
755755 E = MRI.def_end(); I != E; ++I) {
798798 // Allow re-materialization of PIC load.
799799 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
800800 return false;
801 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
801 const MachineFunction &MF = *MI->getParent()->getParent();
802 const MachineRegisterInfo &MRI = MF.getRegInfo();
802803 bool isPICBase = false;
803804 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
804805 E = MRI.def_end(); I != E; ++I) {
824825 if (BaseReg == 0)
825826 return true;
826827 // Allow re-materialization of lea PICBase + x.
827 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
828 const MachineFunction &MF = *MI->getParent()->getParent();
829 const MachineRegisterInfo &MRI = MF.getRegInfo();
828830 return regIsPICBase(BaseReg, MRI);
829831 }
830832 return false;
908910 }
909911
910912 if (!Emitted) {
911 MachineInstr *MI = Orig->clone();
913 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
912914 MI->getOperand(0).setReg(DestReg);
913915 MBB.insert(I, MI);
914916 }
984986 MachineBasicBlock::iterator &MBBI,
985987 LiveVariables *LV) const {
986988 MachineInstr *MI = MBBI;
989 MachineFunction &MF = *MI->getParent()->getParent();
987990 // All instructions input are two-addr instructions. Get the known operands.
988991 unsigned Dest = MI->getOperand(0).getReg();
989992 unsigned Src = MI->getOperand(1).getReg();
10061009 if (B != C) return 0;
10071010 unsigned A = MI->getOperand(0).getReg();
10081011 unsigned M = MI->getOperand(3).getImm();
1009 NewMI = BuildMI(get(X86::PSHUFDri)).addReg(A, true, false, false, isDead)
1012 NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead)
10101013 .addReg(B, false, false, isKill).addImm(M);
10111014 break;
10121015 }
10171020 unsigned ShAmt = MI->getOperand(2).getImm();
10181021 if (ShAmt == 0 || ShAmt >= 4) return 0;
10191022
1020 NewMI = BuildMI(get(X86::LEA64r)).addReg(Dest, true, false, false, isDead)
1023 NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead)
10211024 .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0);
10221025 break;
10231026 }
10301033
10311034 unsigned Opc = TM.getSubtarget().is64Bit() ?
10321035 X86::LEA64_32r : X86::LEA32r;
1033 NewMI = BuildMI(get(Opc)).addReg(Dest, true, false, false, isDead)
1036 NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead)
10341037 .addReg(0).addImm(1 << ShAmt)
10351038 .addReg(Src, false, false, isKill).addImm(0);
10361039 break;
10521055
10531056 // Build and insert into an implicit UNDEF value. This is OK because
10541057 // well be shifting and then extracting the lower 16-bits.
1055 MachineInstr *Undef = BuildMI(get(X86::IMPLICIT_DEF), leaInReg);
1056 MachineInstr *InsMI = BuildMI(get(X86::INSERT_SUBREG),leaInReg)
1058 BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg);
1059 MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg)
10571060 .addReg(leaInReg).addReg(Src, false, false, isKill)
10581061 .addImm(X86::SUBREG_16BIT);
10591062
1060 NewMI = BuildMI(get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt)
1063 NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt)
10611064 .addReg(leaInReg, false, false, true).addImm(0);
10621065
1063 MachineInstr *ExtMI = BuildMI(get(X86::EXTRACT_SUBREG))
1066 MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG))
10641067 .addReg(Dest, true, false, false, isDead)
10651068 .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT);
1066
1067 MFI->insert(MBBI, Undef);
1068 MFI->insert(MBBI, InsMI); // Insert the insert_subreg
1069 MFI->insert(MBBI, NewMI); // Insert the lea inst
1070 MFI->insert(MBBI, ExtMI); // Insert the extract_subreg
10711069 if (LV) {
10721070 // Update live variables
10731071 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
10791077 }
10801078 return ExtMI;
10811079 } else {
1082 NewMI = BuildMI(get(X86::LEA16r)).addReg(Dest, true, false, false, isDead)
1080 NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead)
10831081 .addReg(0).addImm(1 << ShAmt)
10841082 .addReg(Src, false, false, isKill).addImm(0);
10851083 }
11001098 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
11011099 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
11021100 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1103 NewMI = addRegOffset(BuildMI(get(Opc))
1101 NewMI = addRegOffset(BuildMI(MF, get(Opc))
11041102 .addReg(Dest, true, false, false, isDead),
11051103 Src, isKill, 1);
11061104 break;
11091107 case X86::INC64_16r:
11101108 if (DisableLEA16) return 0;
11111109 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1112 NewMI = addRegOffset(BuildMI(get(X86::LEA16r))
1110 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
11131111 .addReg(Dest, true, false, false, isDead),
11141112 Src, isKill, 1);
11151113 break;
11181116 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
11191117 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
11201118 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1121 NewMI = addRegOffset(BuildMI(get(Opc))
1119 NewMI = addRegOffset(BuildMI(MF, get(Opc))
11221120 .addReg(Dest, true, false, false, isDead),
11231121 Src, isKill, -1);
11241122 break;
11271125 case X86::DEC64_16r:
11281126 if (DisableLEA16) return 0;
11291127 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1130 NewMI = addRegOffset(BuildMI(get(X86::LEA16r))
1128 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
11311129 .addReg(Dest, true, false, false, isDead),
11321130 Src, isKill, -1);
11331131 break;
11381136 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
11391137 unsigned Src2 = MI->getOperand(2).getReg();
11401138 bool isKill2 = MI->getOperand(2).isKill();
1141 NewMI = addRegReg(BuildMI(get(Opc))
1139 NewMI = addRegReg(BuildMI(MF, get(Opc))
11421140 .addReg(Dest, true, false, false, isDead),
11431141 Src, isKill, Src2, isKill2);
11441142 if (LV && isKill2)
11501148 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
11511149 unsigned Src2 = MI->getOperand(2).getReg();
11521150 bool isKill2 = MI->getOperand(2).isKill();
1153 NewMI = addRegReg(BuildMI(get(X86::LEA16r))
1151 NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r))
11541152 .addReg(Dest, true, false, false, isDead),
11551153 Src, isKill, Src2, isKill2);
11561154 if (LV && isKill2)
11611159 case X86::ADD64ri8:
11621160 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
11631161 if (MI->getOperand(2).isImmediate())
1164 NewMI = addRegOffset(BuildMI(get(X86::LEA64r))
1162 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r))
11651163 .addReg(Dest, true, false, false, isDead),
11661164 Src, isKill, MI->getOperand(2).getImm());
11671165 break;
11701168 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
11711169 if (MI->getOperand(2).isImmediate()) {
11721170 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1173 NewMI = addRegOffset(BuildMI(get(Opc))
1171 NewMI = addRegOffset(BuildMI(MF, get(Opc))
11741172 .addReg(Dest, true, false, false, isDead),
11751173 Src, isKill, MI->getOperand(2).getImm());
11761174 }
11801178 if (DisableLEA16) return 0;
11811179 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
11821180 if (MI->getOperand(2).isImmediate())
1183 NewMI = addRegOffset(BuildMI(get(X86::LEA16r))
1181 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
11841182 .addReg(Dest, true, false, false, isDead),
11851183 Src, isKill, MI->getOperand(2).getImm());
11861184 break;
11981196 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
11991197 : (MIOpc == X86::SHL32ri
12001198 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1201 NewMI = addFullAddress(BuildMI(get(Opc))
1199 NewMI = addFullAddress(BuildMI(MF, get(Opc))
12021200 .addReg(Dest, true, false, false, isDead), AM);
12031201 if (isKill)
12041202 NewMI->getOperand(3).setIsKill(true);
12611259 A = C;
12621260 CisKill = false;
12631261 }
1264 return BuildMI(get(Opc)).addReg(A, true, false, false, AisDead)
1262 MachineFunction &MF = *MI->getParent()->getParent();
1263 return BuildMI(MF, get(Opc))
1264 .addReg(A, true, false, false, AisDead)
12651265 .addReg(C, false, false, CisKill)
12661266 .addReg(B, false, false, BisKill).addImm(Size-Amt);
12671267 }
17491749 const TargetRegisterClass *RC,
17501750 SmallVectorImpl &NewMIs) const {
17511751 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
1752 MachineInstrBuilder MIB = BuildMI(get(Opc));
1752 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
17531753 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
17541754 MIB = X86InstrAddOperand(MIB, Addr[i]);
17551755 MIB.addReg(SrcReg, false, false, isKill);
18081808 const TargetRegisterClass *RC,
18091809 SmallVectorImpl &NewMIs) const {
18101810 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
1811 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
1811 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
18121812 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
18131813 MIB = X86InstrAddOperand(MIB, Addr[i]);
18141814 NewMIs.push_back(MIB);
18531853 return true;
18541854 }
18551855
1856 static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
1856 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
18571857 SmallVector &MOs,
18581858 MachineInstr *MI, const TargetInstrInfo &TII) {
18591859 // Create the base instruction with the memory operand as the first part.
1860 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1860 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
18611861 MachineInstrBuilder MIB(NewMI);
18621862 unsigned NumAddrOps = MOs.size();
18631863 for (unsigned i = 0; i != NumAddrOps; ++i)
18781878 return MIB;
18791879 }
18801880
1881 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
1881 static MachineInstr *FuseInst(MachineFunction &MF,
1882 unsigned Opcode, unsigned OpNo,
18821883 SmallVector &MOs,
18831884 MachineInstr *MI, const TargetInstrInfo &TII) {
1884 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1885 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
18851886 MachineInstrBuilder MIB(NewMI);
18861887
18871888 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
19031904 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
19041905 SmallVector &MOs,
19051906 MachineInstr *MI) {
1906 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
1907 MachineFunction &MF = *MI->getParent()->getParent();
1908 MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode));
19071909
19081910 unsigned NumAddrOps = MOs.size();
19091911 for (unsigned i = 0; i != NumAddrOps; ++i)
19141916 }
19151917
19161918 MachineInstr*
1917 X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
1919 X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1920 MachineInstr *MI, unsigned i,
19181921 SmallVector &MOs) const {
19191922 const DenseMap *OpcodeTablePtr = NULL;
19201923 bool isTwoAddrFold = false;
19581961 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
19591962 if (I != OpcodeTablePtr->end()) {
19601963 if (isTwoAddrFold)
1961 NewMI = FuseTwoAddrInst(I->second, MOs, MI, *this);
1964 NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this);
19621965 else
1963 NewMI = FuseInst(I->second, i, MOs, MI, *this);
1966 NewMI = FuseInst(MF, I->second, i, MOs, MI, *this);
19641967 return NewMI;
19651968 }
19661969 }
20162019
20172020 SmallVector MOs;
20182021 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2019 return foldMemoryOperand(MI, Ops[0], MOs);
2022 return foldMemoryOperand(MF, MI, Ops[0], MOs);
20202023 }
20212024
20222025 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
20272030 if (NoFusing) return NULL;
20282031
20292032 unsigned Alignment = 0;
2030 for (unsigned i = 0, e = LoadMI->getNumMemOperands(); i != e; ++i) {
2031 const MachineMemOperand &MRO = LoadMI->getMemOperand(i);
2033 for (alist::iterator i = LoadMI->memoperands_begin(),
2034 e = LoadMI->memoperands_end(); i != e; ++i) {
2035 const MachineMemOperand &MRO = *i;
20322036 unsigned Align = MRO.getAlignment();
20332037 if (Align > Alignment)
20342038 Alignment = Align;
20712075 unsigned NumOps = LoadMI->getDesc().getNumOperands();
20722076 for (unsigned i = NumOps - 4; i != NumOps; ++i)
20732077 MOs.push_back(LoadMI->getOperand(i));
2074 return foldMemoryOperand(MI, Ops[0], MOs);
2078 return foldMemoryOperand(MF, MI, Ops[0], MOs);
20752079 }
20762080
20772081
21842188 }
21852189
21862190 // Emit the data processing instruction.
2187 MachineInstr *DataMI = new MachineInstr(TID, true);
2191 MachineInstr *DataMI = MF.CreateMachineInstr(TID, true);
21882192 MachineInstrBuilder MIB(DataMI);
21892193
21902194 if (FoldedStore)
413413 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
414414
415415 private:
416 MachineInstr* foldMemoryOperand(MachineInstr* MI,
417 unsigned OpNum,
418 SmallVector &MOs) const;
416 MachineInstr* foldMemoryOperand(MachineFunction &MF,
417 MachineInstr* MI,
418 unsigned OpNum,
419 SmallVector &MOs) const;
419420 };
420421
421422 } // End llvm namespace
182182 return CalleeSavedRegs64Bit;
183183 } else {
184184 if (MF) {
185 MachineFrameInfo *MFI = MF->getFrameInfo();
186 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
185 const MachineFrameInfo *MFI = MF->getFrameInfo();
186 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
187187 if (MMI && MMI->callsEHReturn())
188188 return CalleeSavedRegs32EHRet;
189189 }
221221 return CalleeSavedRegClasses64Bit;
222222 } else {
223223 if (MF) {
224 MachineFrameInfo *MFI = MF->getFrameInfo();
225 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
224 const MachineFrameInfo *MFI = MF->getFrameInfo();
225 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
226226 if (MMI && MMI->callsEHReturn())
227227 return CalleeSavedRegClasses32EHRet;
228228 }
268268 // if frame pointer elimination is disabled.
269269 //
270270 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
271 MachineFrameInfo *MFI = MF.getFrameInfo();
272 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
271 const MachineFrameInfo *MFI = MF.getFrameInfo();
272 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
273273
274274 return (NoFramePointerElim ||
275275 needsStackRealignment(MF) ||
279279 }
280280
281281 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
282 MachineFrameInfo *MFI = MF.getFrameInfo();;
282 const MachineFrameInfo *MFI = MF.getFrameInfo();;
283283
284284 // FIXME: Currently we don't support stack realignment for functions with
285285 // variable-sized allocas
342342
343343 MachineInstr *New = 0;
344344 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
345 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
345 New=BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
346346 .addReg(StackPtr).addImm(Amount);
347347 } else {
348348 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
353353 unsigned Opc = (Amount < 128) ?
354354 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
355355 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
356 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
356 New = BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
357357 }
358358 }
359359
369369 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
370370 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
371371 MachineInstr *New =
372 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
372 BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
373373 MBB.insert(I, New);
374374 }
375375 }
748748 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
749749 .addExternalSymbol("_alloca");
750750 // Restore EAX
751 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
751 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
752752 StackPtr, false, NumBytes-4);
753753 MBB.insert(MBBI, MI);
754754 }
844844 } else if (MFI->hasVarSizedObjects()) {
845845 if (CSSize) {
846846 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
847 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
847 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
848848 FramePtr, false, -CSSize);
849849 MBB.insert(MBBI, MI);
850850 } else