llvm.org GIT mirror llvm / 8e1d151
[DAGCombine] Remainder of fix to r225380 (More FMA folding opportunities) As pointed out by Aditya (and Owen), when we elide an FP extend to form an FMA, we need to extend the incoming operands so that the resulting node will really be legal. This is currently enabled only for PowerPC, and it happens to work there regardless, but this should fix the functionality for everyone else should anyone else wish to use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225492 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 5 years ago
1 changed file(s) with 24 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
69276927 SDValue N00 = N0.getOperand(0);
69286928 if (N00.getOpcode() == ISD::FMUL)
69296929 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6930 N00.getOperand(0), N00.getOperand(1), N1);
6930 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6931 N00.getOperand(0)),
6932 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6933 N00.getOperand(1)), N1);
69316934 }
69326935
69336936 // fold (fadd x, (fpext (fmul y, z)), z) -> (fma y, z, x)
69366939 SDValue N10 = N1.getOperand(0);
69376940 if (N10.getOpcode() == ISD::FMUL)
69386941 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6939 N10.getOperand(0), N10.getOperand(1), N0);
6942 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6943 N10.getOperand(0)),
6944 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
6945 N10.getOperand(1)), N0);
69406946 }
69416947 }
69426948 }
70727078 SDValue N00 = N0.getOperand(0);
70737079 if (N00.getOpcode() == ISD::FMUL)
70747080 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
7075 N00.getOperand(0),
7076 N00.getOperand(1),
7081 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7082 N00.getOperand(0)),
7083 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7084 N00.getOperand(1)),
70777085 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N1));
70787086 }
70797087
70847092 if (N10.getOpcode() == ISD::FMUL)
70857093 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
70867094 DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7087 N10.getOperand(0)),
7088 N10.getOperand(1),
7095 DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
7096 VT, N10.getOperand(0))),
7097 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7098 N10.getOperand(1)),
70897099 N0);
70907100 }
70917101
70987108 if (N000.getOpcode() == ISD::FMUL) {
70997109 return DAG.getNode(ISD::FMA, dl, VT,
71007110 DAG.getNode(ISD::FNEG, dl, VT,
7101 N000.getOperand(0)),
7102 N000.getOperand(1),
7111 DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
7112 VT, N000.getOperand(0))),
7113 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7114 N000.getOperand(1)),
71037115 DAG.getNode(ISD::FNEG, dl, VT, N1));
71047116 }
71057117 }
71147126 if (N000.getOpcode() == ISD::FMUL) {
71157127 return DAG.getNode(ISD::FMA, dl, VT,
71167128 DAG.getNode(ISD::FNEG, dl, VT,
7117 N000.getOperand(0)),
7118 N000.getOperand(1),
7129 DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
7130 VT, N000.getOperand(0))),
7131 DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT,
7132 N000.getOperand(1)),
71197133 DAG.getNode(ISD::FNEG, dl, VT, N1));
71207134 }
71217135 }