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[X86] Remove isTypePromotionOfi1ZeroUpBits and its helpers. This was trying to optimize concat_vectors with zero of setcc or kand instructions. But I think it produced the same code we produce for a concat_vectors with 0 even it it doesn't come from one of those operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364463 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 4 months ago
1 changed file(s) with 0 addition(s) and 71 deletion(s). Raw diff Collapse all Expand all
55255525 Subs.push_back(Builder(DAG, DL, SubOps));
55265526 }
55275527 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Subs);
5528 }
5529
5530 // Return true if the instruction zeroes the unused upper part of the
5531 // destination and accepts mask.
5532 static bool isMaskedZeroUpperBitsvXi1(unsigned int Opcode) {
5533 switch (Opcode) {
5534 default:
5535 return false;
5536 case X86ISD::CMPM:
5537 case X86ISD::CMPM_SAE:
5538 case ISD::SETCC:
5539 return true;
5540 }
55415528 }
55425529
55435530 /// Insert i1-subvector to i1-vector.
96899676 return Vec;
96909677 }
96919678
9692 // Return true if all the operands of the given CONCAT_VECTORS node are zeros
9693 // except for the first one. (CONCAT_VECTORS Op, 0, 0,...,0)
9694 static bool isExpandWithZeros(const SDValue &Op) {
9695 assert(Op.getOpcode() == ISD::CONCAT_VECTORS &&
9696 "Expand with zeros only possible in CONCAT_VECTORS nodes!");
9697
9698 for (unsigned i = 1; i < Op.getNumOperands(); i++)
9699 if (!ISD::isBuildVectorAllZeros(Op.getOperand(i).getNode()))
9700 return false;
9701
9702 return true;
9703 }
9704
97059679 // Returns true if the given node is a type promotion (by concatenating i1
97069680 // zeros) of the result of a node that already zeros all upper bits of
97079681 // k-register.
9708 static SDValue isTypePromotionOfi1ZeroUpBits(SDValue Op) {
9709 unsigned Opc = Op.getOpcode();
9710
9711 assert(Opc == ISD::CONCAT_VECTORS &&
9712 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
9713 "Unexpected node to check for type promotion!");
9714
9715 // As long as we are concatenating zeros to the upper part of a previous node
9716 // result, climb up the tree until a node with different opcode is
9717 // encountered
9718 while (Opc == ISD::INSERT_SUBVECTOR || Opc == ISD::CONCAT_VECTORS) {
9719 if (Opc == ISD::INSERT_SUBVECTOR) {
9720 if (ISD::isBuildVectorAllZeros(Op.getOperand(0).getNode()) &&
9721 Op.getConstantOperandVal(2) == 0)
9722 Op = Op.getOperand(1);
9723 else
9724 return SDValue();
9725 } else { // Opc == ISD::CONCAT_VECTORS
9726 if (isExpandWithZeros(Op))
9727 Op = Op.getOperand(0);
9728 else
9729 return SDValue();
9730 }
9731 Opc = Op.getOpcode();
9732 }
9733
9734 // Check if the first inserted node zeroes the upper bits, or an 'and' result
9735 // of a node that zeros the upper bits (its masked version).
9736 if (isMaskedZeroUpperBitsvXi1(Op.getOpcode()) ||
9737 (Op.getOpcode() == ISD::AND &&
9738 (isMaskedZeroUpperBitsvXi1(Op.getOperand(0).getOpcode()) ||
9739 isMaskedZeroUpperBitsvXi1(Op.getOperand(1).getOpcode())))) {
9740 return Op;
9741 }
9742
9743 return SDValue();
9744 }
9745
97469682 // TODO: Merge this with LowerAVXCONCAT_VECTORS?
97479683 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
97489684 const X86Subtarget &Subtarget,
97539689
97549690 assert(NumOperands > 1 && isPowerOf2_32(NumOperands) &&
97559691 "Unexpected number of operands in CONCAT_VECTORS");
9756
9757 // If this node promotes - by concatenating zeroes - the type of the result
9758 // of a node with instruction that zeroes all upper (irrelevant) bits of the
9759 // output register, mark it as legal and catch the pattern in instruction
9760 // selection to avoid emitting extra instructions (for zeroing upper bits).
9761 if (SDValue Promoted = isTypePromotionOfi1ZeroUpBits(Op))
9762 return widenSubVector(ResVT, Promoted, true, Subtarget, DAG, dl);
97639692
97649693 unsigned NumZero = 0;
97659694 unsigned NumNonZero = 0;